^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc2385 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 set max framerate to strictly 30FPS for cts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GC2385_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GC2385_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GC2385_LINK_FREQ_MHZ 328000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GC2385_PIXEL_RATE (GC2385_LINK_FREQ_MHZ * 2 * 1 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC2385_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHIP_ID 0x2385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GC2385_REG_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GC2385_REG_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC2385_REG_SET_PAGE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GC2385_SET_PAGE_ONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GC2385_REG_CTRL_MODE 0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC2385_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC2385_MODE_STREAMING 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC2385_REG_EXPOSURE_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC2385_REG_EXPOSURE_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC2385_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0x3F) /* 6 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC2385_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GC2385_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC2385_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC2385_VTS_MAX 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC2385_REG_AGAIN 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC2385_REG_DGAIN_INT 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC2385_REG_DGAIN_FRAC 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC2385_GAIN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC2385_GAIN_MAX 1092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC2385_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC2385_GAIN_DEFAULT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC2385_REG_VTS_H 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC2385_REG_VTS_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC2385_NAME "gc2385"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const gc2385_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GC2385_NUM_SUPPLIES ARRAY_SIZE(gc2385_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct gc2385_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct gc2385 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regulator_bulk_data supplies[GC2385_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct gc2385_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define to_gc2385(sd) container_of(sd, struct gc2385, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct regval gc2385_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * mipi_datarate per lane 656Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct regval gc2385_1600x1200_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0xf2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0xf4, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0xf8, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0xf9, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0xfa, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0xe7, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x88, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x03, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x04, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x05, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x06, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x0a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x0c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x17, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x18, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x19, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x1c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x20, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x21, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x22, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x29, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x2f, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0xcd, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0xce, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0xd1, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0xd7, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0xd8, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0xda, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0xd9, 0xb5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0xdb, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0xe3, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0xe4, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x40, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x43, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x4e, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x4f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0xb0, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0xb1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x90, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x92, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x94, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x95, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x96, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x97, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x98, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0xed, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x02, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x03, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x04, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x06, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x11, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x12, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x13, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x1b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x1c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x21, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x22, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x23, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x24, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x25, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x26, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x29, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x2a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x2b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct gc2385_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .width = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .height = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .exp_def = 0x0480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .hts_def = 0x10DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .vts_def = 0x04F0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .reg_list = gc2385_1600x1200_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GC2385_LINK_FREQ_MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int gc2385_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "gc2385 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int gc2385_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = gc2385_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int gc2385_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "gc2385 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int gc2385_get_reso_dist(const struct gc2385_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct gc2385_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) gc2385_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dist = gc2385_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int gc2385_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct gc2385_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mode = gc2385_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) gc2385->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __v4l2_ctrl_modify_range(gc2385->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) __v4l2_ctrl_modify_range(gc2385->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GC2385_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int gc2385_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const struct gc2385_mode *mode = gc2385->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int gc2385_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int gc2385_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int gc2385_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const struct gc2385_mode *mode = gc2385->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void gc2385_get_module_inf(struct gc2385 *gc2385,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) strlcpy(inf->base.sensor, GC2385_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) strlcpy(inf->base.module, gc2385->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) strlcpy(inf->base.lens, gc2385->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static long gc2385_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) gc2385_get_module_inf(gc2385, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GC2385_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GC2385_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GC2385_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GC2385_REG_SET_PAGE, GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GC2385_REG_CTRL_MODE, GC2385_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static long gc2385_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = gc2385_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = gc2385_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = gc2385_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int __gc2385_start_stream(struct gc2385 *gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = gc2385_write_array(gc2385->client, gc2385->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = v4l2_ctrl_handler_setup(&gc2385->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GC2385_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GC2385_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GC2385_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int __gc2385_stop_stream(struct gc2385 *gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GC2385_REG_SET_PAGE, GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GC2385_REG_CTRL_MODE, GC2385_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int gc2385_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct i2c_client *client = gc2385->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (on == gc2385->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = __gc2385_start_stream(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __gc2385_stop_stream(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) gc2385->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int gc2385_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct i2c_client *client = gc2385->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (gc2385->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = gc2385_write_array(gc2385->client, gc2385_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) gc2385->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gc2385->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static inline u32 gc2385_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return DIV_ROUND_UP(cycles, GC2385_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int __gc2385_power_on(struct gc2385 *gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct device *dev = &gc2385->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!IS_ERR_OR_NULL(gc2385->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = pinctrl_select_state(gc2385->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) gc2385->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = clk_set_rate(gc2385->xvclk, GC2385_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (clk_get_rate(gc2385->xvclk) != GC2385_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = clk_prepare_enable(gc2385->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!IS_ERR(gc2385->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) gpiod_set_value_cansleep(gc2385->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = regulator_bulk_enable(GC2385_NUM_SUPPLIES, gc2385->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!IS_ERR(gc2385->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) gpiod_set_value_cansleep(gc2385->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!IS_ERR(gc2385->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) gpiod_set_value_cansleep(gc2385->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) delay_us = gc2385_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) clk_disable_unprepare(gc2385->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static void __gc2385_power_off(struct gc2385 *gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!IS_ERR(gc2385->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) gpiod_set_value_cansleep(gc2385->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) clk_disable_unprepare(gc2385->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!IS_ERR(gc2385->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) gpiod_set_value_cansleep(gc2385->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!IS_ERR_OR_NULL(gc2385->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = pinctrl_select_state(gc2385->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) gc2385->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_dbg(&gc2385->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) regulator_bulk_disable(GC2385_NUM_SUPPLIES, gc2385->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int gc2385_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return __gc2385_power_on(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int gc2385_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) __gc2385_power_off(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int gc2385_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) const struct gc2385_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mutex_lock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mutex_unlock(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int gc2385_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int gc2385_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) val = 1 << (GC2385_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const struct dev_pm_ops gc2385_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) SET_RUNTIME_PM_OPS(gc2385_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) gc2385_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct v4l2_subdev_internal_ops gc2385_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .open = gc2385_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct v4l2_subdev_core_ops gc2385_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .s_power = gc2385_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .ioctl = gc2385_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .compat_ioctl32 = gc2385_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct v4l2_subdev_video_ops gc2385_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .s_stream = gc2385_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .g_frame_interval = gc2385_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const struct v4l2_subdev_pad_ops gc2385_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .enum_mbus_code = gc2385_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .enum_frame_size = gc2385_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .enum_frame_interval = gc2385_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .get_fmt = gc2385_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .set_fmt = gc2385_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .get_mbus_config = gc2385_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const struct v4l2_subdev_ops gc2385_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .core = &gc2385_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .video = &gc2385_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .pad = &gc2385_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define GC2385_ANALOG_GAIN_1 64 /*1.00x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define GC2385_ANALOG_GAIN_2 92 // 1.43x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define GC2385_ANALOG_GAIN_3 127 // 1.99x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define GC2385_ANALOG_GAIN_4 183 // 2.86x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define GC2385_ANALOG_GAIN_5 257 // 4.01x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define GC2385_ANALOG_GAIN_6 369 // 5.76x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define GC2385_ANALOG_GAIN_7 531 //8.30x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define GC2385_ANALOG_GAIN_8 750 // 11.72x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define GC2385_ANALOG_GAIN_9 1092 // 17.06x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int gc2385_set_gain_reg(struct gc2385 *gc2385, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GC2385_REG_SET_PAGE, GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (a_gain >= GC2385_ANALOG_GAIN_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) a_gain < GC2385_ANALOG_GAIN_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GC2385_REG_AGAIN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) temp = 256 * a_gain / GC2385_ANALOG_GAIN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) } else if (a_gain >= GC2385_ANALOG_GAIN_2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) a_gain < GC2385_ANALOG_GAIN_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GC2385_REG_AGAIN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) temp = 256 * a_gain / GC2385_ANALOG_GAIN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) } else if (a_gain >= GC2385_ANALOG_GAIN_3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) a_gain < GC2385_ANALOG_GAIN_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) GC2385_REG_AGAIN, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) temp = 256 * a_gain / GC2385_ANALOG_GAIN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) } else if (a_gain >= GC2385_ANALOG_GAIN_4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) a_gain < GC2385_ANALOG_GAIN_5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) GC2385_REG_AGAIN, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) temp = 256 * a_gain / GC2385_ANALOG_GAIN_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) } else if (a_gain >= GC2385_ANALOG_GAIN_5 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) a_gain < GC2385_ANALOG_GAIN_6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) GC2385_REG_AGAIN, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) temp = 256 * a_gain / GC2385_ANALOG_GAIN_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) } else if (a_gain >= GC2385_ANALOG_GAIN_6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) a_gain < GC2385_ANALOG_GAIN_7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) GC2385_REG_AGAIN, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) temp = 256 * a_gain / GC2385_ANALOG_GAIN_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) } else if (a_gain >= GC2385_ANALOG_GAIN_7 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) a_gain < GC2385_ANALOG_GAIN_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) GC2385_REG_AGAIN, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) temp = 256 * a_gain / GC2385_ANALOG_GAIN_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) } else if (a_gain >= GC2385_ANALOG_GAIN_8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) a_gain < GC2385_ANALOG_GAIN_9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) GC2385_REG_AGAIN, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) temp = 256 * a_gain / GC2385_ANALOG_GAIN_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret |= gc2385_write_reg(gc2385->client, 0x20, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret |= gc2385_write_reg(gc2385->client, 0x22, 0xa4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) GC2385_REG_AGAIN, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) temp = 256 * a_gain / GC2385_ANALOG_GAIN_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) GC2385_REG_DGAIN_INT, (temp >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) GC2385_REG_DGAIN_FRAC, temp & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int gc2385_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct gc2385 *gc2385 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct gc2385, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct i2c_client *client = gc2385->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) max = gc2385->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) __v4l2_ctrl_modify_range(gc2385->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) gc2385->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) gc2385->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) gc2385->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GC2385_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GC2385_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GC2385_FETCH_HIGH_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GC2385_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GC2385_FETCH_LOW_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = gc2385_set_gain_reg(gc2385, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GC2385_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GC2385_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ((ctrl->val - 32) >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret |= gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GC2385_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) (ctrl->val - 32) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const struct v4l2_ctrl_ops gc2385_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .s_ctrl = gc2385_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int gc2385_initialize_controls(struct gc2385 *gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) const struct gc2385_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) handler = &gc2385->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) mode = gc2385->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) handler->lock = &gc2385->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) 0, GC2385_PIXEL_RATE, 1, GC2385_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) gc2385->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (gc2385->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) gc2385->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) gc2385->vblank = v4l2_ctrl_new_std(handler, &gc2385_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) GC2385_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) gc2385->exposure = v4l2_ctrl_new_std(handler, &gc2385_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) V4L2_CID_EXPOSURE, GC2385_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) exposure_max, GC2385_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) gc2385->anal_gain = v4l2_ctrl_new_std(handler, &gc2385_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) V4L2_CID_ANALOGUE_GAIN, GC2385_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GC2385_GAIN_MAX, GC2385_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GC2385_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(&gc2385->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) gc2385->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int gc2385_check_sensor_id(struct gc2385 *gc2385,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct device *dev = &gc2385->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u8 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u8 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ret = gc2385_write_reg(gc2385->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GC2385_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GC2385_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret |= gc2385_read_reg(client, GC2385_REG_CHIP_ID_H, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ret |= gc2385_read_reg(client, GC2385_REG_CHIP_ID_L, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int gc2385_configure_regulators(struct gc2385 *gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) for (i = 0; i < GC2385_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) gc2385->supplies[i].supply = gc2385_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return devm_regulator_bulk_get(&gc2385->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) GC2385_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) gc2385->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int gc2385_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct gc2385 *gc2385;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) gc2385 = devm_kzalloc(dev, sizeof(*gc2385), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (!gc2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) &gc2385->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) &gc2385->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) &gc2385->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) &gc2385->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) gc2385->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) gc2385->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) gc2385->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (IS_ERR(gc2385->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) gc2385->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (IS_ERR(gc2385->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) gc2385->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (IS_ERR(gc2385->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = gc2385_configure_regulators(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) gc2385->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (!IS_ERR(gc2385->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) gc2385->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pinctrl_lookup_state(gc2385->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (IS_ERR(gc2385->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) gc2385->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pinctrl_lookup_state(gc2385->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (IS_ERR(gc2385->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) mutex_init(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) sd = &gc2385->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) v4l2_i2c_subdev_init(sd, client, &gc2385_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = gc2385_initialize_controls(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = __gc2385_power_on(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = gc2385_check_sensor_id(gc2385, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) sd->internal_ops = &gc2385_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) gc2385->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = media_entity_pads_init(&sd->entity, 1, &gc2385->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (strcmp(gc2385->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) gc2385->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) GC2385_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) __gc2385_power_off(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) v4l2_ctrl_handler_free(&gc2385->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) mutex_destroy(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int gc2385_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct gc2385 *gc2385 = to_gc2385(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) v4l2_ctrl_handler_free(&gc2385->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) mutex_destroy(&gc2385->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) __gc2385_power_off(gc2385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static const struct of_device_id gc2385_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) { .compatible = "galaxycore,gc2385" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) MODULE_DEVICE_TABLE(of, gc2385_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct i2c_device_id gc2385_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { "galaxycore,gc2385", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static struct i2c_driver gc2385_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .name = GC2385_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .pm = &gc2385_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .of_match_table = of_match_ptr(gc2385_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .probe = &gc2385_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .remove = &gc2385_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .id_table = gc2385_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return i2c_add_driver(&gc2385_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) i2c_del_driver(&gc2385_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) MODULE_DESCRIPTION("GalaxyCore gc2385 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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