^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc2355 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GC2355_LINK_FREQ_420MHZ 420000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* pixel rate = link frequency * 1 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GC2355_PIXEL_RATE (GC2355_LINK_FREQ_420MHZ * 2 * 1 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GC2355_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CHIP_ID 0x2355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GC2355_REG_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC2355_REG_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GC2355_PAGE_SELECT 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GC2355_MODE_SELECT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GC2355_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC2355_MODE_STREAMING 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GC2355_REG_EXPOSURE_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GC2355_REG_EXPOSURE_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC2355_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC2355_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GC2355_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC2355_ANALOG_GAIN_1 64 /*1.00x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC2355_ANALOG_GAIN_2 88 /*1.375x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC2355_ANALOG_GAIN_3 122 /*1.90x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GC2355_ANALOG_GAIN_4 168 /*2.625x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC2355_ANALOG_GAIN_5 239 /*3.738x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC2355_ANALOG_GAIN_6 330 /*5.163x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC2355_ANALOG_GAIN_7 470 /*7.350x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC2355_ANALOG_GAIN_REG 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC2355_PREGAIN_H_REG 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC2355_PREGAIN_L_REG 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC2355_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC2355_GAIN_MAX 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GC2355_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC2355_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GC2355_REG_VTS_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GC2355_REG_VTS_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GC2355_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC2355_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GC2355_NAME "gc2355"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const char * const gc2355_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GC2355_NUM_SUPPLIES ARRAY_SIZE(gc2355_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct gc2355_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gc2355 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct regulator_bulk_data supplies[GC2355_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct gc2355_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define to_gc2355(sd) container_of(sd, struct gc2355, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct regval gc2355_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ////////////////////// SYS //////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0xf2, 0x00}, //sync_pad_io_ebi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0xf6, 0x00}, //up down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0xfc, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0xf7, 0x19}, //19 //clk_double pll enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0xf8, 0x06}, //Pll mode 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0xf9, 0x0e}, //de//[0] pll enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0xfa, 0x00}, //div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) //////////////// ANALOG & CISCTL ////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x03, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x04, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x05, 0x01}, //HB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x06, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x07, 0x00}, //VB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x08, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x0a, 0x00}, //row start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x0c, 0x04}, //0c//col start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x0e, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x0f, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x10, 0x50}, //Window setting 1616x1216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x17, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x19, 0x0b}, //09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x1b, 0x49}, //48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x1c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x1d, 0x10}, //double reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x1e, 0xbc}, //a8//col_r/rowclk_mode/rsthigh_en FPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x1f, 0xc8}, //08//rsgl_s_mode/vpix_s_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x20, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x21, 0x20}, //rsg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x22, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x23, 0x51}, //01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x24, 0x19}, //0b //55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x27, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x28, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x2b, 0x81}, //80 //00 sf_s_mode FPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x2c, 0x38}, //50 //5c ispg FPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x2e, 0x16}, //05//eq width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x2f, 0x14}, //[3:0]tx_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x30, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x31, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x32, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x33, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x34, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x35, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x36, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ////////////////////// gain /////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0xb0, 0x50}, //1.25x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xb1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0xb2, 0xe0}, //2.86x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0xb3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0xb4, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0xb5, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0xb6, 0x03}, //2.8x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ////////////////////// crop /////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x92, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x95, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x96, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x97, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x98, 0x40}, //out window set 1600x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ////////////////////// BLK /////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x18, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x1a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x40, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x41, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x44, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x45, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x46, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x47, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x48, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x49, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x4a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x4b, 0x00}, //clear offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x4e, 0x3c}, //BLK select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x4f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x5e, 0x00}, //offset ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x66, 0x20}, //dark ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x6a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x6b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x6c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x6d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x6e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x6f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x70, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x71, 0x02}, //manual offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ////////////////// Dark sun /////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x87, 0x03}, //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xe0, 0xe7}, //dark sun en/extend mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xe3, 0xc0}, //clamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ////////////////////// MIPI /////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /////////////////////////////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x01, 0x83}, //0x87 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x03, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x04, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x06, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x10, 0x00}, //94//1lane raw8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x11, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x12, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x13, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* p3:0x15 [1:0]clklane_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 00 : Enter LP mode between Frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * 01: Enter LP mode between Row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 10: Continuous HS mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x15, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x21, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x22, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x23, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x24, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x25, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x26, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x27, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x29, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x2a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x2b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x41, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x42, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x43, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * mipi_datarate per lane 1008Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct regval gc2355_1600x1200_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct gc2355_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .width = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .height = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .exp_def = 0x04d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .hts_def = 0x08cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .vts_def = 0x04d9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .reg_list = gc2355_1600x1200_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) GC2355_LINK_FREQ_420MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int gc2355_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_info(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_info(&client->dev, "gc2355 write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "gc2355 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int gc2355_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "gc2355 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int gc2355_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = gc2355_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int gc2355_get_reso_dist(const struct gc2355_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct gc2355_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gc2355_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dist = gc2355_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int gc2355_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) const struct gc2355_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mutex_lock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mode = gc2355_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) gc2355->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __v4l2_ctrl_modify_range(gc2355->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __v4l2_ctrl_modify_range(gc2355->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GC2355_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int gc2355_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const struct gc2355_mode *mode = gc2355->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mutex_lock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int gc2355_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int gc2355_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int gc2355_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const struct gc2355_mode *mode = gc2355->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mutex_lock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void gc2355_get_module_inf(struct gc2355 *gc2355,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) strlcpy(inf->base.sensor, GC2355_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) strlcpy(inf->base.module, gc2355->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) strlcpy(inf->base.lens, gc2355->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static long gc2355_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) gc2355_get_module_inf(gc2355, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret |= gc2355_write_reg(gc2355->client, GC2355_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GC2355_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret |= gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret |= gc2355_write_reg(gc2355->client, GC2355_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GC2355_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret |= gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static long gc2355_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = gc2355_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = gc2355_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = gc2355_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int __gc2355_start_stream(struct gc2355 *gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = gc2355_write_array(gc2355->client, gc2355_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = gc2355_write_array(gc2355->client, gc2355->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = v4l2_ctrl_handler_setup(&gc2355->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_lock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = gc2355_write_reg(gc2355->client, GC2355_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GC2355_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int __gc2355_stop_stream(struct gc2355 *gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = gc2355_write_reg(gc2355->client, GC2355_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GC2355_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = gc2355_write_reg(gc2355->client, GC2355_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int gc2355_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct i2c_client *client = gc2355->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mutex_lock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (on == gc2355->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = __gc2355_start_stream(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __gc2355_stop_stream(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) gc2355->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static inline u32 gc2355_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return DIV_ROUND_UP(cycles, GC2355_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int __gc2355_power_on(struct gc2355 *gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct device *dev = &gc2355->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!IS_ERR_OR_NULL(gc2355->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = pinctrl_select_state(gc2355->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) gc2355->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = clk_set_rate(gc2355->xvclk, GC2355_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (clk_get_rate(gc2355->xvclk) != GC2355_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = clk_prepare_enable(gc2355->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!IS_ERR(gc2355->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) gpiod_set_value_cansleep(gc2355->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = regulator_bulk_enable(GC2355_NUM_SUPPLIES, gc2355->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!IS_ERR(gc2355->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) gpiod_set_value_cansleep(gc2355->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!IS_ERR(gc2355->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) gpiod_set_value_cansleep(gc2355->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) delay_us = gc2355_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) clk_disable_unprepare(gc2355->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void __gc2355_power_off(struct gc2355 *gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct device *dev = &gc2355->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!IS_ERR(gc2355->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) gpiod_set_value_cansleep(gc2355->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) clk_disable_unprepare(gc2355->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!IS_ERR(gc2355->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) gpiod_set_value_cansleep(gc2355->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!IS_ERR_OR_NULL(gc2355->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = pinctrl_select_state(gc2355->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) gc2355->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regulator_bulk_disable(GC2355_NUM_SUPPLIES, gc2355->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int gc2355_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return __gc2355_power_on(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int gc2355_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) __gc2355_power_off(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int gc2355_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) const struct gc2355_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_lock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mutex_unlock(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int gc2355_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int gc2355_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) val = 1 << (GC2355_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const struct dev_pm_ops gc2355_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SET_RUNTIME_PM_OPS(gc2355_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) gc2355_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct v4l2_subdev_internal_ops gc2355_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .open = gc2355_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const struct v4l2_subdev_core_ops gc2355_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .ioctl = gc2355_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .compat_ioctl32 = gc2355_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct v4l2_subdev_video_ops gc2355_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .s_stream = gc2355_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .g_frame_interval = gc2355_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .g_mbus_config = gc2355_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const struct v4l2_subdev_pad_ops gc2355_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .enum_mbus_code = gc2355_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .enum_frame_size = gc2355_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .enum_frame_interval = gc2355_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .get_fmt = gc2355_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .set_fmt = gc2355_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const struct v4l2_subdev_ops gc2355_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .core = &gc2355_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .video = &gc2355_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .pad = &gc2355_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int gc2355_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct gc2355 *gc2355 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct gc2355, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct i2c_client *client = gc2355->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) s32 usGain, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) max = gc2355->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) __v4l2_ctrl_modify_range(gc2355->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) gc2355->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) gc2355->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) gc2355->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) GC2355_PAGE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GC2355_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) (ctrl->val >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) GC2355_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) usGain = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) GC2355_PAGE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if ((usGain >= GC2355_ANALOG_GAIN_1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) (usGain < GC2355_ANALOG_GAIN_2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) GC2355_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) temp = usGain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) GC2355_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) GC2355_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) } else if ((usGain >= GC2355_ANALOG_GAIN_2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) (usGain < GC2355_ANALOG_GAIN_3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) GC2355_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) temp = 64 * usGain / GC2355_ANALOG_GAIN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) GC2355_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GC2355_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } else if ((usGain >= GC2355_ANALOG_GAIN_3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) (usGain < GC2355_ANALOG_GAIN_4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) GC2355_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) temp = 64 * usGain / GC2355_ANALOG_GAIN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) GC2355_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) GC2355_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) } else if (usGain >= GC2355_ANALOG_GAIN_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) GC2355_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) temp = 64 * usGain / GC2355_ANALOG_GAIN_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) GC2355_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) GC2355_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) GC2355_PAGE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = gc2355_write_reg(gc2355->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GC2355_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ((ctrl->val + gc2355->cur_mode->height) >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret = gc2355_write_reg(gc2355->client, GC2355_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) (ctrl->val + gc2355->cur_mode->height) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const struct v4l2_ctrl_ops gc2355_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .s_ctrl = gc2355_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int gc2355_initialize_controls(struct gc2355 *gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) const struct gc2355_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct device *dev = &gc2355->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_info(dev, "Enter %s(%d) !\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) handler = &gc2355->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) mode = gc2355->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) handler->lock = &gc2355->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) 0, GC2355_PIXEL_RATE, 1, GC2355_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) gc2355->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (gc2355->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) gc2355->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) gc2355->vblank = v4l2_ctrl_new_std(handler, &gc2355_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GC2355_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) gc2355->exposure = v4l2_ctrl_new_std(handler, &gc2355_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) V4L2_CID_EXPOSURE, GC2355_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) exposure_max, GC2355_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) gc2355->anal_gain = v4l2_ctrl_new_std(handler, &gc2355_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) V4L2_CID_ANALOGUE_GAIN, GC2355_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GC2355_GAIN_MAX, GC2355_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GC2355_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dev_err(&gc2355->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) gc2355->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int gc2355_check_sensor_id(struct gc2355 *gc2355,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct device *dev = &gc2355->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u8 pid, ver = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unsigned short id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = gc2355_read_reg(client, GC2355_REG_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(dev, "Read chip ID H register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = gc2355_read_reg(client, GC2355_REG_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(dev, "Read chip ID L register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int gc2355_configure_regulators(struct gc2355 *gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) for (i = 0; i < GC2355_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) gc2355->supplies[i].supply = gc2355_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return devm_regulator_bulk_get(&gc2355->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GC2355_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) gc2355->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int gc2355_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct gc2355 *gc2355;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) gc2355 = devm_kzalloc(dev, sizeof(*gc2355), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!gc2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) &gc2355->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) &gc2355->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) &gc2355->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) &gc2355->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) gc2355->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) gc2355->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) gc2355->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (IS_ERR(gc2355->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) gc2355->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (IS_ERR(gc2355->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) gc2355->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (IS_ERR(gc2355->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) gc2355->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!IS_ERR(gc2355->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) gc2355->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pinctrl_lookup_state(gc2355->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (IS_ERR(gc2355->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) gc2355->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) pinctrl_lookup_state(gc2355->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (IS_ERR(gc2355->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = gc2355_configure_regulators(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mutex_init(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) sd = &gc2355->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) v4l2_i2c_subdev_init(sd, client, &gc2355_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = gc2355_initialize_controls(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ret = __gc2355_power_on(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = gc2355_check_sensor_id(gc2355, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sd->internal_ops = &gc2355_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) gc2355->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = media_entity_pads_init(&sd->entity, 1, &gc2355->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (strcmp(gc2355->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) gc2355->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) GC2355_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) __gc2355_power_off(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) v4l2_ctrl_handler_free(&gc2355->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) mutex_destroy(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static int gc2355_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct gc2355 *gc2355 = to_gc2355(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) v4l2_ctrl_handler_free(&gc2355->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) mutex_destroy(&gc2355->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) __gc2355_power_off(gc2355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const struct of_device_id gc2355_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { .compatible = "galaxycore,gc2355" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) MODULE_DEVICE_TABLE(of, gc2355_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static const struct i2c_device_id gc2355_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) { "galaxycore,gc2355", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static struct i2c_driver gc2355_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .name = GC2355_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .pm = &gc2355_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .of_match_table = of_match_ptr(gc2355_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .probe = &gc2355_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .remove = &gc2355_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .id_table = gc2355_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return i2c_add_driver(&gc2355_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) i2c_del_driver(&gc2355_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) MODULE_DESCRIPTION("GC2355 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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