^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc2053 sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GC2053_NAME "gc2053"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GC2053_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGRBG10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIPI_FREQ_297M 297000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC2053_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC2053_PAGE_SELECT 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GC2053_REG_CHIP_ID_H 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GC2053_REG_CHIP_ID_L 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GC2053_REG_EXP_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GC2053_REG_EXP_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC2053_REG_VTS_H 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC2053_REG_VTS_L 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC2053_REG_CTRL_MODE 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC2053_MODE_SW_STANDBY 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC2053_MODE_STREAMING 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC2053_CHIP_ID 0x2053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC2053_VTS_MAX 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC2053_HTS_MAX 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC2053_EXPOSURE_MAX 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC2053_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC2053_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GC2053_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC2053_GAIN_MAX 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC2053_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GC2053_GAIN_DEFAULT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC2053_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GC2053_FLIP_MIRROR_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GC_MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GC_FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const gc2053_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GC2053_NUM_SUPPLIES ARRAY_SIZE(gc2053_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define to_gc2053(sd) container_of(sd, struct gc2053, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gc2053_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct gc2053 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regulator_bulk_data supplies[GC2053_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct gc2053_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct rkmodule_lsc_cfg lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * window_size=1920*1080 mipi@2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * mclk=24mhz,mipi_clk=594Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * pixel_line_total=2200,line_frame_total=1125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * row_time=29.629us,frame_rate=30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct regval gc2053_1920x1080_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /****system****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0xf2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0xf3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0xf4, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0xf5, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0xf6, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0xf8, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0xf9, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /****CISCTL & ANALOG****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x87, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0xee, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0xd0, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x03, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x04, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x05, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x06, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x08, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x0a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x0c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x0d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x12, 0xe2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x13, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x19, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x21, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x28, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x29, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x2b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x32, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x37, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x39, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x43, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x44, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x46, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x4b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x4e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x55, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x66, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x67, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x77, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x78, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x7c, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x8c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x8d, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x9d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0xce, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0xd2, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0xd3, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0xe6, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0xb6, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0xb0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0xb1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xb3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0xb4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0xb8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0xb9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*blk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x26, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x40, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x55, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x60, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0xfe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x14, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x15, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x16, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x17, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*window*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x92, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x94, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x95, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x96, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x97, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x98, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x01, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x02, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x04, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x07, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x08, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x09, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x0a, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x0b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x0c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x0f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x50, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x89, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0xfe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x28, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x29, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x2a, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x2b, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x2c, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x2d, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x2e, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x2f, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x30, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x31, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x32, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x33, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x34, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x35, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x36, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x37, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x38, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x39, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3a, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3b, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3c, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3e, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3f, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /****DVP & MIPI****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x9a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x7b, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x23, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x01, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x02, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x03, 0xb6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x12, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x13, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x15, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3e, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct gc2053_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .exp_def = 0x460,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .hts_def = 0x898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .vts_def = 0x465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .reg_list = gc2053_1920x1080_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MIPI_FREQ_297M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int gc2053_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "gc2053 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int gc2053_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = gc2053_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int gc2053_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "gc2053 read reg(0x%x val:0x%x) failed !\n", reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int gc2053_get_reso_dist(const struct gc2053_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct gc2053_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gc2053_find_best_fit(struct gc2053 *gc2053, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (i = 0; i < gc2053->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dist = gc2053_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const uint8_t gain_reg_table[29][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x00, 0x00, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x00, 0x10, 0x01, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x00, 0x20, 0x01, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x00, 0x30, 0x01, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x00, 0x40, 0x01, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x00, 0x50, 0x02, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x00, 0x60, 0x02, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x00, 0x70, 0x03, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x00, 0x80, 0x04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x00, 0x90, 0x04, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x00, 0xa0, 0x05, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x00, 0xb0, 0x06, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x00, 0xc0, 0x08, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x00, 0x5a, 0x09, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x00, 0x83, 0x0b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x00, 0x93, 0x0d, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x00, 0x84, 0x10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x00, 0x94, 0x12, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x01, 0x2c, 0x1a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x01, 0x3c, 0x1b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x00, 0x8c, 0x20, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x00, 0x9c, 0x26, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x02, 0x64, 0x36, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x02, 0x74, 0x37, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x00, 0xc6, 0x3d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x00, 0xdc, 0x3f, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x02, 0x85, 0x3f, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x02, 0x95, 0x3f, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x00, 0xce, 0x3f, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const uint32_t gain_level_table[30] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 305,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 437,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 516,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 601,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 719,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 1210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 1538,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 1760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 2063,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 2439,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 2881,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 3393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 3970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 4737,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 5572,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 6552,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 7713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int gc2053_set_gain(struct gc2053 *gc2053, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) uint8_t i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uint8_t total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint32_t temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) total = sizeof(gain_level_table) / sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (i = 0; i <= total; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((gain_level_table[i] <= gain) && (gain < gain_level_table[i+1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (i > total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) i = total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = gc2053_write_reg(gc2053->client, 0xb4, gain_reg_table[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret |= gc2053_write_reg(gc2053->client, 0xb3, gain_reg_table[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret |= gc2053_write_reg(gc2053->client, 0xb8, gain_reg_table[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret |= gc2053_write_reg(gc2053->client, 0xb9, gain_reg_table[i][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) temp = 64 * gain / gain_level_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret |= gc2053_write_reg(gc2053->client, 0xb1, (temp >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret |= gc2053_write_reg(gc2053->client, 0xb2, (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int gc2053_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct gc2053 *gc2053 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct gc2053, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct i2c_client *client = gc2053->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) max = gc2053->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) __v4l2_ctrl_modify_range(gc2053->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) gc2053->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) gc2053->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gc2053->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = gc2053_write_reg(gc2053->client, GC2053_REG_EXP_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) (ctrl->val >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret |= gc2053_write_reg(gc2053->client, GC2053_REG_EXP_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) gc2053_set_gain(gc2053, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) vts = ctrl->val + gc2053->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = gc2053_write_reg(gc2053->client, GC2053_REG_VTS_H, (vts >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret |= gc2053_write_reg(gc2053->client, GC2053_REG_VTS_L, vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) gc2053->flip |= GC_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) gc2053->flip &= ~GC_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) gc2053->flip |= GC_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) gc2053->flip &= ~GC_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct v4l2_ctrl_ops gc2053_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .s_ctrl = gc2053_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int gc2053_configure_regulators(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (i = 0; i < GC2053_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gc2053->supplies[i].supply = gc2053_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return devm_regulator_bulk_get(&gc2053->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GC2053_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gc2053->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int gc2053_parse_of(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct device *dev = &gc2053->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) gc2053->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (2 == gc2053->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) gc2053->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) gc2053->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /*pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) gc2053->pixel_rate = MIPI_FREQ_297M * 2U * (gc2053->lane_num) / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) gc2053->lane_num, gc2053->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_info(dev, "gc2053 can not support the lane num(%d)\n", gc2053->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int gc2053_initialize_controls(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const struct gc2053_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) handler = &gc2053->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mode = gc2053->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) handler->lock = &gc2053->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0, gc2053->pixel_rate, 1, gc2053->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gc2053->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (gc2053->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) gc2053->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gc2053->vblank = v4l2_ctrl_new_std(handler, &gc2053_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GC2053_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) gc2053->exposure = v4l2_ctrl_new_std(handler, &gc2053_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) V4L2_CID_EXPOSURE, GC2053_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) exposure_max, GC2053_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) gc2053->anal_gain = v4l2_ctrl_new_std(handler, &gc2053_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) V4L2_CID_ANALOGUE_GAIN, GC2053_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GC2053_GAIN_MAX, GC2053_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GC2053_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) gc2053->h_flip = v4l2_ctrl_new_std(handler, &gc2053_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) gc2053->v_flip = v4l2_ctrl_new_std(handler, &gc2053_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) gc2053->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&gc2053->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) gc2053->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static inline u32 gc2053_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return DIV_ROUND_UP(cycles, GC2053_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int __gc2053_power_on(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct device *dev = &gc2053->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!IS_ERR_OR_NULL(gc2053->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = pinctrl_select_state(gc2053->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) gc2053->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = clk_set_rate(gc2053->xvclk, GC2053_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (clk_get_rate(gc2053->xvclk) != GC2053_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = clk_prepare_enable(gc2053->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = regulator_bulk_enable(GC2053_NUM_SUPPLIES, gc2053->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!IS_ERR(gc2053->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) gpiod_set_value_cansleep(gc2053->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!IS_ERR(gc2053->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) gpiod_set_value_cansleep(gc2053->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!IS_ERR(gc2053->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) gpiod_set_value_cansleep(gc2053->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!IS_ERR(gc2053->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) gpiod_set_value_cansleep(gc2053->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) usleep_range(3000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) delay_us = gc2053_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) clk_disable_unprepare(gc2053->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static void __gc2053_power_off(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct device *dev = &gc2053->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!IS_ERR(gc2053->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) gpiod_set_value_cansleep(gc2053->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) clk_disable_unprepare(gc2053->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!IS_ERR(gc2053->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) gpiod_set_value_cansleep(gc2053->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!IS_ERR_OR_NULL(gc2053->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = pinctrl_select_state(gc2053->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) gc2053->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!IS_ERR(gc2053->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) gpiod_set_value_cansleep(gc2053->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) regulator_bulk_disable(GC2053_NUM_SUPPLIES, gc2053->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int gc2053_check_sensor_id(struct gc2053 *gc2053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct device *dev = &gc2053->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 pid = 0, ver = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Check sensor revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = gc2053_read_reg(client, GC2053_REG_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret |= gc2053_read_reg(client, GC2053_REG_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(&client->dev, "gc2053_read_reg failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (id != GC2053_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "Sensor detection failed (%04X,%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_info(dev, "Detected GC%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int gc2053_set_flip(struct gc2053 *gc2053, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u8 match_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) gc2053_read_reg(gc2053->client, GC2053_FLIP_MIRROR_REG, &match_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (mode == GC_FLIP_BIT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) match_reg |= GC_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) match_reg &= ~GC_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else if (mode == GC_MIRROR_BIT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) match_reg |= GC_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) match_reg &= ~GC_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) } else if (mode == (GC_MIRROR_BIT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GC_FLIP_BIT_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) match_reg |= GC_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) match_reg |= GC_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) match_reg &= ~GC_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) match_reg &= ~GC_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return gc2053_write_reg(gc2053->client, GC2053_FLIP_MIRROR_REG, match_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int __gc2053_start_stream(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = gc2053_write_array(gc2053->client, gc2053->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = v4l2_ctrl_handler_setup(&gc2053->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = gc2053_set_flip(gc2053, gc2053->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return gc2053_write_reg(gc2053->client, GC2053_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GC2053_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int __gc2053_stop_stream(struct gc2053 *gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return gc2053_write_reg(gc2053->client, GC2053_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GC2053_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static void gc2053_get_module_inf(struct gc2053 *gc2053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) strlcpy(inf->base.sensor, GC2053_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) strlcpy(inf->base.module, gc2053->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) strlcpy(inf->base.lens, gc2053->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static void gc2053_set_awb_cfg(struct gc2053 *gc2053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) memcpy(&gc2053->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static void gc2053_set_lsc_cfg(struct gc2053 *gc2053,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct rkmodule_lsc_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) memcpy(&gc2053->lsc_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static long gc2053_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) hdr_cfg->hdr_mode = gc2053->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) gc2053_get_module_inf(gc2053, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) gc2053_set_awb_cfg(gc2053, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) gc2053_set_lsc_cfg(gc2053, (struct rkmodule_lsc_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = gc2053_write_reg(gc2053->client, GC2053_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GC2053_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret = gc2053_write_reg(gc2053->client, GC2053_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) GC2053_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static long gc2053_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct rkmodule_awb_cfg *awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct rkmodule_lsc_cfg *lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = gc2053_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) awb_cfg = kzalloc(sizeof(*awb_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!awb_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ret = copy_from_user(awb_cfg, up, sizeof(*awb_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = gc2053_ioctl(sd, cmd, awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) kfree(awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) lsc_cfg = kzalloc(sizeof(*lsc_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!lsc_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = copy_from_user(lsc_cfg, up, sizeof(*lsc_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = gc2053_ioctl(sd, cmd, lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) kfree(lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = gc2053_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = gc2053_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = gc2053_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = gc2053_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int gc2053_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct i2c_client *client = gc2053->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (on == gc2053->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = __gc2053_start_stream(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) __gc2053_stop_stream(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) gc2053->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int gc2053_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) const struct gc2053_mode *mode = gc2053->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int gc2053_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) const struct gc2053_mode *mode = gc2053->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) val = 1 << (GC2053_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int gc2053_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) code->code = GC2053_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int gc2053_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (fse->index >= gc2053->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (fse->code != GC2053_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int gc2053_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (fie->index >= gc2053->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) fie->code = GC2053_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int gc2053_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) const struct gc2053_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) mode = gc2053_find_best_fit(gc2053, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) fmt->format.code = GC2053_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) gc2053->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) __v4l2_ctrl_modify_range(gc2053->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) __v4l2_ctrl_modify_range(gc2053->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) GC2053_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static int gc2053_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) const struct gc2053_mode *mode = gc2053->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) fmt->format.code = GC2053_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int gc2053_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) const struct gc2053_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) try_fmt->code = GC2053_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const struct v4l2_subdev_internal_ops gc2053_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .open = gc2053_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int gc2053_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct i2c_client *client = gc2053->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mutex_lock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (gc2053->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) gc2053->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) gc2053->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mutex_unlock(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const struct v4l2_subdev_core_ops gc2053_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .s_power = gc2053_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .ioctl = gc2053_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .compat_ioctl32 = gc2053_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static const struct v4l2_subdev_video_ops gc2053_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .s_stream = gc2053_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .g_frame_interval = gc2053_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static const struct v4l2_subdev_pad_ops gc2053_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .enum_mbus_code = gc2053_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .enum_frame_size = gc2053_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .enum_frame_interval = gc2053_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .get_fmt = gc2053_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .set_fmt = gc2053_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .get_mbus_config = gc2053_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const struct v4l2_subdev_ops gc2053_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .core = &gc2053_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .video = &gc2053_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .pad = &gc2053_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int gc2053_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) __gc2053_power_on(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int gc2053_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) __gc2053_power_off(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const struct dev_pm_ops gc2053_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) SET_RUNTIME_PM_OPS(gc2053_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) gc2053_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int gc2053_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct gc2053 *gc2053;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) gc2053 = devm_kzalloc(dev, sizeof(*gc2053), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (!gc2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) gc2053->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) &gc2053->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) &gc2053->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) &gc2053->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) &gc2053->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) gc2053->xvclk = devm_clk_get(&client->dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (IS_ERR(gc2053->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(&client->dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) gc2053->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (IS_ERR(gc2053->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) gc2053->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (IS_ERR(gc2053->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dev_info(dev, "Failed to get pwdn-gpios, maybe no used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) gc2053->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (IS_ERR(gc2053->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) dev_warn(dev, "Failed to get power-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = gc2053_configure_regulators(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = gc2053_parse_of(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) gc2053->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (!IS_ERR(gc2053->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) gc2053->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) pinctrl_lookup_state(gc2053->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (IS_ERR(gc2053->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) gc2053->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) pinctrl_lookup_state(gc2053->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (IS_ERR(gc2053->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mutex_init(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) sd = &gc2053->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) v4l2_i2c_subdev_init(sd, client, &gc2053_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = gc2053_initialize_controls(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret = __gc2053_power_on(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ret = gc2053_check_sensor_id(gc2053, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) sd->internal_ops = &gc2053_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) gc2053->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = media_entity_pads_init(&sd->entity, 1, &gc2053->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (strcmp(gc2053->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) gc2053->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) GC2053_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) __gc2053_power_off(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) v4l2_ctrl_handler_free(&gc2053->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mutex_destroy(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int gc2053_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct gc2053 *gc2053 = to_gc2053(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) v4l2_ctrl_handler_free(&gc2053->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) mutex_destroy(&gc2053->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) __gc2053_power_off(gc2053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const struct i2c_device_id gc2053_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) { "gc2053", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static const struct of_device_id gc2053_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) { .compatible = "galaxycore,gc2053" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) MODULE_DEVICE_TABLE(of, gc2053_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static struct i2c_driver gc2053_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .name = GC2053_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .pm = &gc2053_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .of_match_table = of_match_ptr(gc2053_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .probe = &gc2053_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .remove = &gc2053_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .id_table = gc2053_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return i2c_add_driver(&gc2053_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) i2c_del_driver(&gc2053_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) MODULE_DESCRIPTION("GC2035 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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