^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc08a3 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 init first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GC08A3_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GC08A3_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC08A3_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC08A3_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GC08A3_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GC08A3_MIPI_FREQ_150MHZ 150000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GC08A3_MIPI_FREQ_350MHZ 350000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC08A3_MIPI_FREQ_700MHZ 700000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GC08A3_PIXEL_RATE 288000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC08A3_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CHIP_ID 0x08a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC08A3_REG_CHIP_ID_H 0x03f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC08A3_REG_CHIP_ID_L 0x03f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC08A3_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GC08A3_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC08A3_MODE_STREAMING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC08A3_REG_EXPOSURE_H 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC08A3_REG_EXPOSURE_L 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC08A3_FETCH_HIGH_BYTE(VAL) (((VAL) >> 8) & 0xFF) /* 4 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC08A3_FETCH_LOW_BYTE(VAL) ((VAL) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC08A3_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC08A3_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC08A3_VTS_MAX 0xfffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GC08A3_REG_GAIN_H 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC08A3_REG_GAIN_L 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GC08A3_AGAIN_MIN 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GC08A3_AGAIN_MAX 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC08A3_AGAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GC08A3_AGAIN_DEFAULT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GC08A3_REG_VTS_H 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC08A3_REG_VTS_L 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GC08A3_NAME "gc08a3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GC08A3_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char * const gc08a3_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GC08A3_NUM_SUPPLIES ARRAY_SIZE(gc08a3_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct gc08a3_id_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) char name[RKMODULE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct gc08a3_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct regval *global_reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct gc08a3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regulator_bulk_data supplies[GC08A3_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct gc08a3_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct gc08a3_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct rkmodule_inf module_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define to_gc08a3(sd) container_of(sd, struct gc08a3, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #undef GC08A3_MIRROR_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #undef GC08A3_MIRROR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #undef GC08A3_MIRROR_V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #undef GC08A3_MIRROR_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* SENSOR MIRROR FLIP INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GC08A3_MIRROR_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GC08A3_MIRROR_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GC08A3_MIRROR_V 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GC08A3_MIRROR_HV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #if GC08A3_MIRROR_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GC08A3_MIRROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FULL_STARTY 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FULL_STARTX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BINNING_STARTY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BINNING_STARTX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #elif GC08A3_MIRROR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GC08A3_MIRROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FULL_STARTY 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FULL_STARTX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BINNING_STARTY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BINNING_STARTX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #elif GC08A3_MIRROR_V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GC08A3_MIRROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FULL_STARTY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FULL_STARTX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BINNING_STARTY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BINNING_STARTX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #elif GC08A3_MIRROR_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GC08A3_MIRROR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FULL_STARTY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FULL_STARTX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BINNING_STARTY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BINNING_STARTX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GC08A3_MIRROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FULL_STARTY 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FULL_STARTX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define BINNING_STARTY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BINNING_STARTX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct regval gc08a3_global_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*system*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x031c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x0337, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x0335, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x0336, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x0383, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x0321, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x0327, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x0325, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x0326, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x0314, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x0315, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x0324, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x031c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x039a, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x0084, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x02b3, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x0057, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x05c3, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x0311, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x05a0, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x0074, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x0059, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x0070, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x0101, GC08A3_MIRROR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*analog*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x0345, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0347, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0348, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x0349, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x034a, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x034b, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x0202, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x0203, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x0340, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x0341, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x0342, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x0343, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0219, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x0226, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x0227, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x0e0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x0e0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x0e24, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x0e25, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x0e26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x0e27, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x0e01, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x0e03, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x0e04, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x0e05, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x0e06, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x0e0c, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x0e17, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x0e18, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x0e19, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x0e1a, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x0e28, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x0e2b, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x0e2c, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x0e2d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x0e34, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x0e35, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x0e36, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x0e38, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x0210, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x0218, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x0241, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x0e32, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x0e33, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x0e42, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x0e43, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x0e44, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x0e45, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x0e4f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x057a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x0381, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x0382, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x0384, 0xfb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x0389, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x038a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x0390, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x0391, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x0392, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x0393, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x0396, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x0398, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*cisctl reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x0360, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x0360, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x0316, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x0a67, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x0313, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x0a53, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x0a65, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x0a68, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x0a58, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x0ace, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x00a4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x00a5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x00a7, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x00a8, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x00a9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x00aa, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x0a8a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0a8b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x0a8c, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x0a8d, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x0a90, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x0a91, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0a92, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x0a71, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x0a72, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x0a73, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x0a75, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x0a70, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0313, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x00a0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0080, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0081, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x0087, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x0089, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x009b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x05a0, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x05ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x05ad, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x05ae, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x0800, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x0801, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0802, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x0803, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0804, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x0805, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x0806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x0807, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x0808, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x080a, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x080b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x080c, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x080d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x080e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x080f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x0810, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x0811, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x0812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x0813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x0814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x0815, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x0816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x0817, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x0818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x0819, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x081a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x081b, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x081c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x081d, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x081e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x081f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x0820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x0821, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x0822, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x0823, 0xd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x0824, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x0825, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x0826, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x0827, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x0828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x0829, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x082a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x082b, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x082c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x082d, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x082e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x082f, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x0830, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x0831, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x0832, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0833, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0834, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0835, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x0836, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x0837, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x0838, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x0839, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x05ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x059a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x059b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x059c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x0598, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x0597, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x05ab, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x05a4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x05a3, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x05a0, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x0207, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*GAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x0208, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x0209, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x0204, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x0040, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x0041, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x0043, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x0044, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x0046, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x0047, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x0048, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x004b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x004c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0050, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x0051, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x005b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x00c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x00c1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x00c2, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x00c3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0460, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0462, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x0464, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x0466, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x0468, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x046a, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x046c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x046e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x0461, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x0463, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x0465, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x0467, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x0469, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x046b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x046d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x046f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x0470, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x0472, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x0474, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x0476, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x0478, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x047a, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x047c, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x047e, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x0471, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x0473, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x0475, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x0477, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x0479, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x047b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x047d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x047f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * mipi_datarate per lane 700Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct regval gc08a3_3264x2448_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*system*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x031c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x0337, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x0335, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x0336, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x0383, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x0321, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x0327, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x0325, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x0326, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x0314, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x0315, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x0324, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x031c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x0345, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x0347, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x0348, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x0349, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x034a, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x034b, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x0202, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x0203, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x0340, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x0341, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x0342, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x0343, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x0226, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x0227, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x0e38, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x0210, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x0218, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x0241, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x0392, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x00a2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x00a3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x00ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x00ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x05a0, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x05ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x05ad, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x05ae, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x0800, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x0801, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x0802, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x0803, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x0804, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x0805, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x0806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x0807, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x0808, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x0809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x080a, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x080b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x080c, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x080d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x080e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x080f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x0810, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x0811, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x0812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x0813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x0814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x0815, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x0816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x0817, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x0818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x0819, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x081a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x081b, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x081c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x081d, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x081e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x081f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x0820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x0821, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x0822, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x0823, 0xd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x0824, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x0825, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x0826, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x0827, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x0828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x0829, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x082a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x082b, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x082c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x082d, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x082e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x082f, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x0830, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x0831, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x0832, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x0833, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x0834, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x0835, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x0836, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x0837, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x0838, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x0839, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x05ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x059a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x059b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x059c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x0598, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x0597, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x05ab, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x05a4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x05a3, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x05a0, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x0207, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*GAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x0204, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x0050, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x0051, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*out window*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x009a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x0351, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x0352, FULL_STARTY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x0353, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x0354, FULL_STARTX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x034c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x034d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x034e, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x034f, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*MIPI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x0180, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x0181, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x0115, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x011b, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x011c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x0121, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x0122, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x0123, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x0124, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x0125, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x0126, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x0129, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x012a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x012b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x0a73, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x0a70, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x0313, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x0a70, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x00a4, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x0a67, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x0084, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x0102, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * mipi_datarate per lane 350Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const struct regval gc08a3_1280x720_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*system*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x031c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x0337, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x0335, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x0336, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x0383, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x0321, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x0327, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x0325, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x0326, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x0314, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x0315, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x0324, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x031c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x0344, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x0345, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x0346, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x0347, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x0348, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x0349, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x034a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x034b, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x0202, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x0203, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x0340, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x0341, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x0342, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x0343, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x0226, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x0227, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x0e38, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x0210, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x0218, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x0241, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x0392, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x00a2, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x00a3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x00ab, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x00ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x05a0, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x05ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x05ad, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x05ae, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x0800, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x0801, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x0802, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x0803, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x0804, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x0805, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x0806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x0807, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x0808, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x0809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x080a, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x080b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x080c, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x080d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x080e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x080f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x0810, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x0811, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x0812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x0813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x0814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x0815, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x0816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x0817, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x0818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x0819, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x081a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x081b, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x081c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x081d, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x081e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x081f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x0820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x0821, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x0822, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x0823, 0xd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x0824, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x0825, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x0826, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x0827, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x0828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x0829, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x082a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x082b, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x082c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x082d, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x082e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x082f, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x0830, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x0831, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x0832, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x0833, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x0834, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x0835, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x0836, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x0837, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x0838, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x0839, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x05ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x059a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x059b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x059c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x0598, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x0597, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x05ab, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x05a4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x05a3, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x05a0, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x0207, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*GAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x0204, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x0050, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x0051, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*out window*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x009a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x0351, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x0352, BINNING_STARTY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x0353, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x0354, BINNING_STARTX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x034c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x034d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x034e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x034f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*MIPI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x0180, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x0181, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x0115, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x011b, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x011c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x0121, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x0122, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x0123, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x0124, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x0125, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x0126, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x0129, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x012a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x012b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x0a73, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x0a70, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x0313, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x0a70, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x00a4, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x0a67, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x0084, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x0102, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * mipi_datarate per lane 350Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const struct regval gc08a3_1280x800_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*system*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x031c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x0337, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x0335, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x0336, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x0383, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x0321, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x0327, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x0325, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x0326, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x0314, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x0315, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x0324, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x031c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x0344, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x0345, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x0346, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x0347, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x0348, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x0349, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x034a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x034b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x0202, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x0203, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x0340, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x0341, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x0342, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x0343, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x0226, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x0227, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x0e38, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x0210, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x0218, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x0241, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x0392, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x031c, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x00a2, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x00a3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x00ab, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x00ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x05a0, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x05ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x05ad, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x05ae, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x0800, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x0801, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x0802, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x0803, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x0804, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x0805, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x0806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x0807, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x0808, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x0809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x080a, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x080b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x080c, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x080d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x080e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x080f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {0x0810, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x0811, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {0x0812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x0813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x0814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x0815, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x0816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x0817, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x0818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x0819, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {0x081a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x081b, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x081c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0x081d, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {0x081e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x081f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x0820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x0821, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x0822, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x0823, 0xd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x0824, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x0825, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x0826, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x0827, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x0828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x0829, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x082a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x082b, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x082c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x082d, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x082e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x082f, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x0830, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x0831, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x0832, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x0833, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x0834, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x0835, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x0836, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x0837, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {0x0838, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {0x0839, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {0x05ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {0x059a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {0x059b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {0x059c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {0x0598, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {0x0597, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x05ab, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x05a4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x05a3, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x05a0, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x0207, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*GAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x0204, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x0050, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x0051, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*out window*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x009a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x0351, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x0352, BINNING_STARTY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x0353, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x0354, BINNING_STARTX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x034c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x034d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x034e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x034f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /*MIPI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x0180, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x0181, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x0115, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x011b, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x011c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x0121, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x0122, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {0x0123, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {0x0124, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {0x0125, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {0x0126, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {0x0129, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {0x012a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {0x012b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {0x0a73, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {0x0a70, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {0x0313, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {0x0aff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {0x0a70, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {0x00a4, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {0x0316, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {0x0a67, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {0x0084, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {0x0102, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const struct gc08a3_mode supported_modes_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .width = 3264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .height = 2448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .exp_def = 0x0900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .hts_def = 0x0568 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .vts_def = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .reg_list = gc08a3_3264x2448_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .global_reg_list = gc08a3_global_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .height = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .exp_def = 0x0900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .hts_def = 0x0568 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .vts_def = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .reg_list = gc08a3_1280x800_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .global_reg_list = gc08a3_global_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .exp_def = 0x0900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .hts_def = 0x0568 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .vts_def = 0x0a04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .reg_list = gc08a3_1280x720_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .global_reg_list = gc08a3_global_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) GC08A3_MIPI_FREQ_150MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GC08A3_MIPI_FREQ_350MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GC08A3_MIPI_FREQ_700MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int gc08a3_write_reg(struct i2c_client *client, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) buf[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "gc08a3 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int gc08a3_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = gc08a3_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static int gc08a3_read_reg(struct i2c_client *client, u16 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "gc08a3 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static int gc08a3_get_reso_dist(const struct gc08a3_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static const struct gc08a3_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) gc08a3_find_best_fit(struct gc08a3 *gc08a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (i = 0; i < gc08a3->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dist = gc08a3_get_reso_dist(&gc08a3->support_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return &gc08a3->support_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int gc08a3_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) const struct gc08a3_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) mode = gc08a3_find_best_fit(gc08a3, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) fmt->format.code = GC08A3_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) gc08a3->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) __v4l2_ctrl_modify_range(gc08a3->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) __v4l2_ctrl_modify_range(gc08a3->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) GC08A3_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) __v4l2_ctrl_s_ctrl(gc08a3->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_info(&gc08a3->client->dev, "%s: mode->mipi_freq_idx(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) __func__, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static int gc08a3_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) const struct gc08a3_mode *mode = gc08a3->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) fmt->format.code = GC08A3_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int gc08a3_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) code->code = GC08A3_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static int gc08a3_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (fse->index >= gc08a3->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (fse->code != GC08A3_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) fse->min_width = gc08a3->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) fse->max_width = gc08a3->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) fse->max_height = gc08a3->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) fse->min_height = gc08a3->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int gc08a3_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) const struct gc08a3_mode *mode = gc08a3->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void gc08a3_get_module_inf(struct gc08a3 *gc08a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) strscpy(inf->base.sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) GC08A3_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) strscpy(inf->base.module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) gc08a3->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) strscpy(inf->base.lens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) gc08a3->len_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static void gc08a3_set_module_inf(struct gc08a3 *gc08a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) memcpy(&gc08a3->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static int gc08a3_get_channel_info(struct gc08a3 *gc08a3, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ch_info->vc = gc08a3->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ch_info->width = gc08a3->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ch_info->height = gc08a3->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ch_info->bus_fmt = GC08A3_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static long gc08a3_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) gc08a3_get_module_inf(gc08a3, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) gc08a3_set_module_inf(gc08a3, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) GC08A3_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) GC08A3_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) GC08A3_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) GC08A3_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = gc08a3_get_channel_info(gc08a3, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static long gc08a3_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ret = gc08a3_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = gc08a3_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = gc08a3_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = gc08a3_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int __gc08a3_start_stream(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = gc08a3_write_array(gc08a3->client, gc08a3->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ret = v4l2_ctrl_handler_setup(&gc08a3->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) GC08A3_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) GC08A3_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int __gc08a3_stop_stream(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ret = gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) GC08A3_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) GC08A3_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int gc08a3_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct i2c_client *client = gc08a3->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) gc08a3->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) gc08a3->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) DIV_ROUND_CLOSEST(gc08a3->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) gc08a3->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (on == gc08a3->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ret = __gc08a3_start_stream(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) __gc08a3_stop_stream(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) gc08a3->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static int gc08a3_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct i2c_client *client = gc08a3->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (gc08a3->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ret = gc08a3_write_array(gc08a3->client, gc08a3->cur_mode->global_reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) gc08a3->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) gc08a3->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static inline u32 gc08a3_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return DIV_ROUND_UP(cycles, GC08A3_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static int __gc08a3_power_on(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct device *dev = &gc08a3->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (!IS_ERR(gc08a3->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) gpiod_set_value_cansleep(gc08a3->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (!IS_ERR_OR_NULL(gc08a3->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ret = pinctrl_select_state(gc08a3->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) gc08a3->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ret = clk_set_rate(gc08a3->xvclk, GC08A3_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (clk_get_rate(gc08a3->xvclk) != GC08A3_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ret = clk_prepare_enable(gc08a3->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (!IS_ERR(gc08a3->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) gpiod_set_value_cansleep(gc08a3->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ret = regulator_bulk_enable(GC08A3_NUM_SUPPLIES, gc08a3->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (!IS_ERR(gc08a3->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) gpiod_set_value_cansleep(gc08a3->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (!IS_ERR(gc08a3->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) gpiod_set_value_cansleep(gc08a3->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) delay_us = gc08a3_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) clk_disable_unprepare(gc08a3->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static void __gc08a3_power_off(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (!IS_ERR(gc08a3->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) gpiod_set_value_cansleep(gc08a3->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) clk_disable_unprepare(gc08a3->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (!IS_ERR(gc08a3->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) gpiod_set_value_cansleep(gc08a3->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (!IS_ERR_OR_NULL(gc08a3->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ret = pinctrl_select_state(gc08a3->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) gc08a3->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dev_dbg(&gc08a3->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (!IS_ERR(gc08a3->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) gpiod_set_value_cansleep(gc08a3->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) regulator_bulk_disable(GC08A3_NUM_SUPPLIES, gc08a3->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static int gc08a3_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return __gc08a3_power_on(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static int gc08a3_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) __gc08a3_power_off(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int gc08a3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) const struct gc08a3_mode *def_mode = &gc08a3->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) mutex_lock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) try_fmt->code = GC08A3_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) mutex_unlock(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static int gc08a3_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (fie->index >= gc08a3->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (fie->code != GC08A3_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) fie->width = gc08a3->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) fie->height = gc08a3->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) fie->interval = gc08a3->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static int gc08a3_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct gc08a3 *sensor = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct device *dev = &sensor->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (2 == sensor->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) config->flags = V4L2_MBUS_CSI2_2_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) } else if (4 == sensor->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) config->flags = V4L2_MBUS_CSI2_4_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dev_err(&sensor->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) "unsupported lane_num(%d)\n", sensor->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static const struct dev_pm_ops gc08a3_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) SET_RUNTIME_PM_OPS(gc08a3_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) gc08a3_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const struct v4l2_subdev_internal_ops gc08a3_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .open = gc08a3_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static const struct v4l2_subdev_core_ops gc08a3_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .s_power = gc08a3_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .ioctl = gc08a3_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .compat_ioctl32 = gc08a3_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static const struct v4l2_subdev_video_ops gc08a3_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .s_stream = gc08a3_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .g_frame_interval = gc08a3_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static const struct v4l2_subdev_pad_ops gc08a3_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .enum_mbus_code = gc08a3_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .enum_frame_size = gc08a3_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .enum_frame_interval = gc08a3_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .get_fmt = gc08a3_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .set_fmt = gc08a3_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .get_mbus_config = gc08a3_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const struct v4l2_subdev_ops gc08a3_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .core = &gc08a3_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .video = &gc08a3_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .pad = &gc08a3_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static int gc08a3_set_exposure_reg(struct gc08a3 *gc08a3, u32 exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u32 cal_shutter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) cal_shutter = exposure >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) cal_shutter = cal_shutter << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) GC08A3_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) GC08A3_FETCH_HIGH_BYTE(cal_shutter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) GC08A3_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) GC08A3_FETCH_LOW_BYTE(cal_shutter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static int gc08a3_set_gain_reg(struct gc08a3 *gc08a3, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) u32 temp_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (a_gain < GC08A3_AGAIN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) temp_gain = GC08A3_AGAIN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) else if (a_gain > GC08A3_AGAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) temp_gain = GC08A3_AGAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) temp_gain = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) GC08A3_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) GC08A3_FETCH_HIGH_BYTE(temp_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /* gain effect when 0x0205 is written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) GC08A3_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) GC08A3_FETCH_LOW_BYTE(temp_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static int gc08a3_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct gc08a3 *gc08a3 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct gc08a3, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) struct i2c_client *client = gc08a3->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) max = gc08a3->cur_mode->height + ctrl->val - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) __v4l2_ctrl_modify_range(gc08a3->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) gc08a3->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) gc08a3->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) gc08a3->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_info(&client->dev, "set exposure value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ret = gc08a3_set_exposure_reg(gc08a3, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) dev_info(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret = gc08a3_set_gain_reg(gc08a3, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) dev_info(&client->dev, "set vb value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ret = gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) GC08A3_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) (ctrl->val + gc08a3->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret |= gc08a3_write_reg(gc08a3->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) GC08A3_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) (ctrl->val + gc08a3->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static const struct v4l2_ctrl_ops gc08a3_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .s_ctrl = gc08a3_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static int gc08a3_initialize_controls(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) const struct gc08a3_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) handler = &gc08a3->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) mode = gc08a3->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) handler->lock = &gc08a3->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) gc08a3->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) V4L2_CID_LINK_FREQ, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) 0, gc08a3->pixel_rate, 1, gc08a3->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) __v4l2_ctrl_s_ctrl(gc08a3->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) gc08a3->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (gc08a3->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) gc08a3->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) gc08a3->vblank = v4l2_ctrl_new_std(handler, &gc08a3_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) GC08A3_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) gc08a3->exposure = v4l2_ctrl_new_std(handler, &gc08a3_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) V4L2_CID_EXPOSURE, GC08A3_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) exposure_max, GC08A3_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) gc08a3->anal_gain = v4l2_ctrl_new_std(handler, &gc08a3_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) V4L2_CID_ANALOGUE_GAIN, GC08A3_AGAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) GC08A3_AGAIN_MAX, GC08A3_AGAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) GC08A3_AGAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) dev_err(&gc08a3->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) gc08a3->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static int gc08a3_check_sensor_id(struct gc08a3 *gc08a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct device *dev = &gc08a3->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) u8 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) u8 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ret = gc08a3_read_reg(client, GC08A3_REG_CHIP_ID_H, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ret |= gc08a3_read_reg(client, GC08A3_REG_CHIP_ID_L, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static int gc08a3_configure_regulators(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) for (i = 0; i < GC08A3_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) gc08a3->supplies[i].supply = gc08a3_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) return devm_regulator_bulk_get(&gc08a3->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) GC08A3_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) gc08a3->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static int gc08a3_parse_of(struct gc08a3 *gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) struct device *dev = &gc08a3->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) gc08a3->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (4 == gc08a3->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) gc08a3->cur_mode = &supported_modes_4lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) gc08a3->support_modes = supported_modes_4lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) gc08a3->cfg_num = ARRAY_SIZE(supported_modes_4lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) fps = DIV_ROUND_CLOSEST(gc08a3->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) gc08a3->cur_mode->max_fps.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) gc08a3->pixel_rate = gc08a3->cur_mode->vts_def *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) gc08a3->cur_mode->hts_def * fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) gc08a3->lane_num, gc08a3->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) } else if (2 == gc08a3->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* TODO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) dev_err(dev, "unsupported lane_num(%d)\n", gc08a3->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static int gc08a3_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) struct gc08a3 *gc08a3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) gc08a3 = devm_kzalloc(dev, sizeof(*gc08a3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (!gc08a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) &gc08a3->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) &gc08a3->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) &gc08a3->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) &gc08a3->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) gc08a3->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) gc08a3->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (IS_ERR(gc08a3->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) gc08a3->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (IS_ERR(gc08a3->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) gc08a3->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (IS_ERR(gc08a3->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) gc08a3->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (IS_ERR(gc08a3->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ret = gc08a3_configure_regulators(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ret = gc08a3_parse_of(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) gc08a3->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (!IS_ERR(gc08a3->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) gc08a3->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) pinctrl_lookup_state(gc08a3->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (IS_ERR(gc08a3->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) gc08a3->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pinctrl_lookup_state(gc08a3->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (IS_ERR(gc08a3->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) mutex_init(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) sd = &gc08a3->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) v4l2_i2c_subdev_init(sd, client, &gc08a3_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ret = gc08a3_initialize_controls(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ret = __gc08a3_power_on(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) ret = gc08a3_check_sensor_id(gc08a3, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) sd->internal_ops = &gc08a3_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) gc08a3->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ret = media_entity_pads_init(&sd->entity, 1, &gc08a3->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (strcmp(gc08a3->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) gc08a3->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) GC08A3_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) __gc08a3_power_off(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) v4l2_ctrl_handler_free(&gc08a3->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) mutex_destroy(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static int gc08a3_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) struct gc08a3 *gc08a3 = to_gc08a3(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) v4l2_ctrl_handler_free(&gc08a3->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) mutex_destroy(&gc08a3->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) __gc08a3_power_off(gc08a3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static const struct of_device_id gc08a3_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) { .compatible = "galaxycore,gc08a3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) MODULE_DEVICE_TABLE(of, gc08a3_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static const struct i2c_device_id gc08a3_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) { "galaxycore,gc08a3", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static struct i2c_driver gc08a3_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .name = GC08A3_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .pm = &gc08a3_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .of_match_table = of_match_ptr(gc08a3_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .probe = &gc08a3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .remove = &gc08a3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .id_table = gc08a3_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return i2c_add_driver(&gc08a3_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) i2c_del_driver(&gc08a3_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) MODULE_DESCRIPTION("GalaxyCore gc08a3 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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