^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GC032A CMOS Image Sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X01 init driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X02 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X03 set sensor in stream off state by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * to avoid sending abnormal data in the early stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/media.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRIVER_NAME "gc032a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC032A_PIXEL_RATE (96 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) //#define GC032A_AUTO_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * GC032A register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_SOFTWARE_STANDBY 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_SC_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_SC_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_NULL 0xFFFF /* Array end token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC032A_ID 0x232a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct sensor_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct gc032a_framesize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 max_exp_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const struct sensor_register *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct gc032a_pll_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 ctrl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gc032a_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Output format Register Value (REG_FORMAT_CTRL00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct sensor_register *format_ctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pll_ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char * const gc032a_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GC032A_NUM_SUPPLIES ARRAY_SIZE(gc032a_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct gc032a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int xvclk_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct regulator_bulk_data supplies[GC032A_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_ctrl *link_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct gc032a_framesize *frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct sensor_register gc032a_vga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*System*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0xf3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0xf5, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0xf8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0xf9, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0xfa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0xfc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0x81, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x77, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x78, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x79, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*ANALOG & CISCTL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x03, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x04, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x06, 0xad},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0d, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0e, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x0f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x10, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x17, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x19, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x1a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x1f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x20, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x2e, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x2f, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x30, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x03, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x05, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x06, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x08, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x12, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*blk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x18, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x40, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x45, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x46, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x49, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x4b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x50, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x42, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*isp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x0a, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x45, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x40, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x41, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x42, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x43, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x44, 0x83},//Output_format //80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x46, 0x22},//sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x49, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x22, 0xf6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*Shading*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0xc1, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0xc2, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0xc3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0xc4, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xc5, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0xc6, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xc7, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0xc8, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0xc9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0xca, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0xdc, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xdd, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0xde, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0xdf, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*AWB*//*20170110*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x92, 0xe3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x93, 0xbe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x95, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x96, 0xe3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x97, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x98, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x9a, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x9b, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x9c, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x9d, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x9f, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0xa0, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xa1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0xa2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x86, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x89, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0xa4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0xa5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0xa6, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0xa7, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0xa9, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0xaa, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0xab, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0xac, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0xae, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0xaf, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xb0, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0xb1, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0xb3, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0xb4, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xb5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x8b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x8c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x8d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x8e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x94, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x99, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x9e, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0xa3, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x8a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xa8, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xad, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xb2, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xb7, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x8f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0xb8, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0xb9, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*CC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0xd0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xd1, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xd2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0xd3, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0xd4, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0xd5, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0xd6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0xd7, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0xd8, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0xd9, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0xda, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0xdb, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*Gamma*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0xba, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0xbb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0xbc, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0xbd, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0xbe, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0xbf, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xc0, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0xc1, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0xc2, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0xc3, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0xc4, 0x7a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0xc5, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0xc6, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0xc7, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0xc8, 0xb5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0xc9, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0xca, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0xcb, 0xd5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0xcc, 0xde},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0xcd, 0xea},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0xce, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0xcf, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*Auto Gamma*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x5a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x5b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x5c, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x5d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x5e, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5f, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x60, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x61, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x62, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x63, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x64, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x65, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x66, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x67, 0xb5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x68, 0xc3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x69, 0xcd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x6a, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x6b, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x6c, 0xe3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x6d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x6e, 0xf9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x6f, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*Gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x70, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*AEC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x4f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x0d, 0x00},//08 add 20170110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x12, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x13, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x44, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x1f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x20, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x26, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x40, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x41, 0x5b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x42, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x43, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x04, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x02, 0x79},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x03, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*measure window*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0xcc, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0xcd, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0xce, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0xcf, 0xec},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*DNDD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x81, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x82, 0x15},//de_noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x83, 0x1a},//de_noise dark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x84, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x86, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x87, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x88, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x89, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x8a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x8b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x8c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x8d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*Intpee*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x8f, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x90, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x91, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x92, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x93, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x94, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x95, 0x65},//sharpness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x97, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*ASDE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0xa1, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0xa2, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0xa4, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0xa5, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0xaa, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0xac, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*YCP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0xd1, 0x37},//3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0xd2, 0x37},//3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0xd3, 0x40},//38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0xd6, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0xd7, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0xdd, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0xde, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef GC032A_AUTO_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*Banding*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* 7fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x06, 0xad},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x25, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x26, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x27, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x28, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x29, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x2a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x2b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x2c, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x2d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x2e, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x2f, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x30, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x31, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x32, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x33, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x34, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*Banding*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* 30 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x06, 0xad},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x25, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x26, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x27, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x28, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x29, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x2a, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x2b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x2c, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x2d, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x2e, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x2f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x30, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x31, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x32, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x33, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x34, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct gc032a_framesize gc032a_framesizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .regs = gc032a_vga_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .max_exp_lines = 488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct gc032a_pixfmt gc032a_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static inline struct gc032a *to_gc032a(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return container_of(sd, struct gc032a, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int gc032a_write(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "gc032a write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int gc032a_read(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "gc032a read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int gc032a_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct sensor_register *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = gc032a_write(client, regs[i].addr, regs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void gc032a_get_default_format(struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) format->width = gc032a_framesizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) format->height = gc032a_framesizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) format->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) format->code = gc032a_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void gc032a_set_streaming(struct gc032a *gc032a, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct i2c_client *client = gc032a->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = gc032a_write(client, REG_SOFTWARE_STANDBY, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_err(&client->dev, "gc032a soft standby failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * V4L2 subdev video and pad level operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int gc032a_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (code->index >= ARRAY_SIZE(gc032a_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) code->code = gc032a_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int gc032a_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int i = ARRAY_SIZE(gc032a_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (fse->index >= ARRAY_SIZE(gc032a_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (fse->code == gc032a_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) fse->code = gc032a_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) fse->min_width = gc032a_framesizes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fse->max_width = fse->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) fse->max_height = gc032a_framesizes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fse->min_height = fse->max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int gc032a_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct gc032a *gc032a = to_gc032a(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_lock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) fmt->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mutex_unlock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_lock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fmt->format = gc032a->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_unlock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) gc032a->format.code, gc032a->format.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gc032a->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void __gc032a_try_frame_size(struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) const struct gc032a_framesize **size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) const struct gc032a_framesize *fsize = &gc032a_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) const struct gc032a_framesize *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int i = ARRAY_SIZE(gc032a_framesizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned int min_err = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned int err = abs(fsize->width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) + abs(fsize->height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (err < min_err && fsize->regs[0].addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) match = &gc032a_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mf->width = match->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mf->height = match->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *size = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int gc032a_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int index = ARRAY_SIZE(gc032a_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct v4l2_mbus_framefmt *mf = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) const struct gc032a_framesize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct gc032a *gc032a = to_gc032a(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __gc032a_try_frame_size(mf, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) while (--index >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (gc032a_formats[index].code == mf->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mf->code = gc032a_formats[index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_lock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) *mf = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (gc032a->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mutex_unlock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) gc032a->frame_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) gc032a->format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mutex_unlock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void gc032a_get_module_inf(struct gc032a *gc032a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) strlcpy(inf->base.sensor, DRIVER_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) strlcpy(inf->base.module, gc032a->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) strlcpy(inf->base.lens, gc032a->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static long gc032a_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct gc032a *gc032a = to_gc032a(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) gc032a_get_module_inf(gc032a, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) gc032a_set_streaming(gc032a, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) gc032a_set_streaming(gc032a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static long gc032a_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = gc032a_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = gc032a_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = gc032a_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int gc032a_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct gc032a *gc032a = to_gc032a(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_info(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mutex_lock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (gc032a->streaming == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Stop Streaming Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) gc032a_set_streaming(gc032a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) gc032a->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gc032a_set_streaming(gc032a, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) gc032a->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mutex_unlock(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int gc032a_set_test_pattern(struct gc032a *gc032a, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int gc032a_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct gc032a *gc032a =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) container_of(ctrl->handler, struct gc032a, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return gc032a_set_test_pattern(gc032a, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const struct v4l2_ctrl_ops gc032a_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .s_ctrl = gc032a_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const char * const gc032a_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "Vertical Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * V4L2 subdev internal operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int gc032a_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct v4l2_mbus_framefmt *format =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) gc032a_get_default_format(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int gc032a_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) config->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) V4L2_MBUS_VSYNC_ACTIVE_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) V4L2_MBUS_PCLK_SAMPLE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int gc032a_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct gc032a *gc032a = to_gc032a(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct i2c_client *client = gc032a->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!IS_ERR(gc032a->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) gpiod_set_value_cansleep(gc032a->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = gc032a_write_array(client, gc032a->frame_size->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(&client->dev, "init error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) gc032a->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!IS_ERR(gc032a->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) gpiod_set_value_cansleep(gc032a->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) gc032a->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int gc032a_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (fie->index >= ARRAY_SIZE(gc032a_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (fie->code != MEDIA_BUS_FMT_YUYV8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) fie->width = gc032a_framesizes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) fie->height = gc032a_framesizes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) fie->interval = gc032a_framesizes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const struct v4l2_subdev_core_ops gc032a_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .ioctl = gc032a_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .compat_ioctl32 = gc032a_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .s_power = gc032a_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const struct v4l2_subdev_video_ops gc032a_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .s_stream = gc032a_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .g_mbus_config = gc032a_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const struct v4l2_subdev_pad_ops gc032a_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .enum_mbus_code = gc032a_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .enum_frame_size = gc032a_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .enum_frame_interval = gc032a_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .get_fmt = gc032a_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .set_fmt = gc032a_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const struct v4l2_subdev_ops gc032a_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .core = &gc032a_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .video = &gc032a_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .pad = &gc032a_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const struct v4l2_subdev_internal_ops gc032a_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .open = gc032a_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int gc032a_detect(struct gc032a *gc032a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct i2c_client *client = gc032a->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u8 pid, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Check sensor revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = gc032a_read(client, REG_SC_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = gc032a_read(client, REG_SC_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned short id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (id != GC032A_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) "Sensor detection failed (%04X, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_info(&client->dev, "Found GC%04X sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!IS_ERR(gc032a->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) gpiod_set_value_cansleep(gc032a->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static int __gc032a_power_on(struct gc032a *gc032a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct device *dev = &gc032a->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!IS_ERR(gc032a->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = clk_set_rate(gc032a->xvclk, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_info(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (!IS_ERR(gc032a->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) gpiod_set_value_cansleep(gc032a->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (!IS_ERR(gc032a->supplies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = regulator_bulk_enable(GC032A_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) gc032a->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_info(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!IS_ERR(gc032a->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) gpiod_set_value_cansleep(gc032a->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!IS_ERR(gc032a->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = clk_prepare_enable(gc032a->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_info(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) usleep_range(7000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) gc032a->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void __gc032a_power_off(struct gc032a *gc032a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (!IS_ERR(gc032a->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) clk_disable_unprepare(gc032a->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (!IS_ERR(gc032a->supplies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) regulator_bulk_disable(GC032A_NUM_SUPPLIES, gc032a->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!IS_ERR(gc032a->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) gpiod_set_value_cansleep(gc032a->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) gc032a->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int gc032a_configure_regulators(struct gc032a *gc032a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) for (i = 0; i < GC032A_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) gc032a->supplies[i].supply = gc032a_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return devm_regulator_bulk_get(&gc032a->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GC032A_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) gc032a->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int gc032a_parse_of(struct gc032a *gc032a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct device *dev = &gc032a->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) gc032a->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (IS_ERR(gc032a->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_info(dev, "Failed to get pwdn-gpios, maybe no used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = gc032a_configure_regulators(gc032a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_info(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return __gc032a_power_on(gc032a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int gc032a_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct gc032a *gc032a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) gc032a = devm_kzalloc(&client->dev, sizeof(*gc032a), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!gc032a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) &gc032a->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) &gc032a->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) &gc032a->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) &gc032a->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) gc032a->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) gc032a->xvclk = devm_clk_get(&client->dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (IS_ERR(gc032a->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_err(&client->dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) gc032a_parse_of(gc032a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) gc032a->xvclk_frequency = clk_get_rate(gc032a->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (gc032a->xvclk_frequency < 6000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) gc032a->xvclk_frequency > 27000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) v4l2_ctrl_handler_init(&gc032a->ctrls, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) gc032a->link_frequency =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) v4l2_ctrl_new_std(&gc032a->ctrls, &gc032a_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) GC032A_PIXEL_RATE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) GC032A_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) v4l2_ctrl_new_std_menu_items(&gc032a->ctrls, &gc032a_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ARRAY_SIZE(gc032a_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 0, 0, gc032a_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) gc032a->sd.ctrl_handler = &gc032a->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (gc032a->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_err(&client->dev, "%s: control initialization error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) __func__, gc032a->ctrls.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return gc032a->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) sd = &gc032a->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) client->flags |= I2C_CLIENT_SCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) v4l2_i2c_subdev_init(sd, client, &gc032a_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sd->internal_ops = &gc032a_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) gc032a->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = media_entity_pads_init(&sd->entity, 1, &gc032a->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) v4l2_ctrl_handler_free(&gc032a->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) mutex_init(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) gc032a_get_default_format(&gc032a->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) gc032a->frame_size = &gc032a_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = gc032a_detect(gc032a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (strcmp(gc032a->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) gc032a->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) DRIVER_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) gc032a->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) v4l2_ctrl_handler_free(&gc032a->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mutex_destroy(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) __gc032a_power_off(gc032a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int gc032a_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct gc032a *gc032a = to_gc032a(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) v4l2_ctrl_handler_free(&gc032a->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) mutex_destroy(&gc032a->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) __gc032a_power_off(gc032a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const struct i2c_device_id gc032a_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) { "gc032a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) MODULE_DEVICE_TABLE(i2c, gc032a_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static const struct of_device_id gc032a_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) { .compatible = "galaxycore,gc032a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) MODULE_DEVICE_TABLE(of, gc032a_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct i2c_driver gc032a_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .of_match_table = of_match_ptr(gc032a_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .probe = gc032a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .remove = gc032a_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .id_table = gc032a_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return i2c_add_driver(&gc032a_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) i2c_del_driver(&gc032a_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) MODULE_AUTHOR("randy.wang <randy.wang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MODULE_DESCRIPTION("GC032A CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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