^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc0329 sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X01 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X02 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/media.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRIVER_NAME "gc0329"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GC0329_PIXEL_RATE (24 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * GC0329 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_SC_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GC0329_ID 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_NULL 0xFFFF /* Array end token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct sensor_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct gc0329_framesize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct sensor_register *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct gc0329_pll_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 ctrl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct gc0329_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Output format Register Value (REG_FORMAT_CTRL00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sensor_register *format_ctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pll_ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char * const gc0329_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GC0329_NUM_SUPPLIES ARRAY_SIZE(gc0329_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct gc0329 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int xvclk_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct regulator_bulk_data supplies[GC0329_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mutex lock; /* Protects streaming, format, interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct v4l2_ctrl *link_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct gc0329_framesize *frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct sensor_register gc0329_vga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {0xfe, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {0xfc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {0xfc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {0x73, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {0x74, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {0x75, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {0x76, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0xfc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0x0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0x17, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0x19, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0x1b, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0x1c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0x1e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0x1f, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x21, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x23, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x24, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* blk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x26, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x32, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x33, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x34, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x35, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x36, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x40, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x41, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x42, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x46, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x4b, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x4d, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x4f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x70, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* DNDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x80, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x82, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x87, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* ASDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x18, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x9c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0xa4, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0xa5, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0xa7, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0xdd, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x95, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0xbf, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0xc0, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0xc1, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0xc2, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0xc3, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0xc4, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0xc5, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0xc6, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0xc7, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0xc8, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0xc9, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0xca, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0xcb, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0xcc, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0xcd, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0xce, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0xcf, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* CC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0xb3, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0xb4, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0xb5, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0xb6, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0xb7, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0xb8, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* crop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x50, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x19, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x22, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x21, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* YCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xd1, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0xd2, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* AEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x10, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x11, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x12, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x13, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x17, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x21, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x22, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3c, 0x95},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3e, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* AWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x06, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x07, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x08, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x09, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x50, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x51, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x52, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x53, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x54, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x55, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x56, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x58, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x59, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x5a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x5b, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x5c, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x5d, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x5e, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x5f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x60, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x61, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x62, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x63, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x64, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x65, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x66, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x67, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x68, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x69, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x6a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x6b, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x6c, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x6d, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x6e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x70, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x71, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x72, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x73, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x80, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x81, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x82, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x83, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x84, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x85, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* CC-AWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xd0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xd2, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0xd3, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* ABS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x9c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x9d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* LSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xa0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xa1, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0xa2, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0xa3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0xa8, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0xa9, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0xaa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0xab, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0xac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0xad, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0xae, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0xaf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0xb0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0xb1, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0xb3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0xb4, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0xb5, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0xb6, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0xba, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0xbb, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xbc, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0xc0, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0xc1, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0xc2, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0xc6, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0xc7, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0xc8, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0xb7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0xb8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0xb9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0xbd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0xbe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0xbf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0xc3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0xc4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0xc5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0xc9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0xca, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0xcb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0xa4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0xa5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0xa6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0xa7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* asde */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0xa0, 0xaf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0xa2, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x44, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct sensor_register gc0329_vga_regs_14fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* flicker 14.2fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x05, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x06, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x08, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x29, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x2a, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x2b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x2c, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x2d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x2e, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x2f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x30, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x31, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x32, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x33, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct sensor_register gc0329_vga_regs_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* flicker 30fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x06, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x08, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x29, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x2a, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x2b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x2c, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x2d, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x2e, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x2f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x30, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x31, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x32, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x33, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct gc0329_framesize gc0329_framesizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .denominator = 140000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .regs = gc0329_vga_regs_14fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .regs = gc0329_vga_regs_30fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct gc0329_pixfmt gc0329_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline struct gc0329 *to_gc0329(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return container_of(sd, struct gc0329, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int gc0329_write(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "gc0329 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int gc0329_read(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "gc0329 read reg:0x%x failed!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int gc0329_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) const struct sensor_register *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = gc0329_write(client, regs[i].addr, regs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void gc0329_get_default_format(struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) format->width = gc0329_framesizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) format->height = gc0329_framesizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) format->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) format->code = gc0329_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void gc0329_set_streaming(struct gc0329 *gc0329, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct i2c_client *client = gc0329->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = gc0329_write(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret |= gc0329_write(client, 0xfc, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret |= gc0329_write(client, 0xf0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret |= gc0329_write(client, 0xf1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret |= gc0329_write(client, 0xfc, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret |= gc0329_write(client, 0xf0, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret |= gc0329_write(client, 0xf1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(&client->dev, "gc0329 soft standby failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * V4L2 subdev video and pad level operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int gc0329_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (code->index >= ARRAY_SIZE(gc0329_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) code->code = gc0329_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int gc0329_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int i = ARRAY_SIZE(gc0329_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (fse->index >= ARRAY_SIZE(gc0329_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (fse->code == gc0329_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fse->code = gc0329_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) fse->min_width = gc0329_framesizes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) fse->max_width = fse->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fse->max_height = gc0329_framesizes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fse->min_height = fse->max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int gc0329_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mutex_lock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) fmt->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_lock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fmt->format = gc0329->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) gc0329->format.code, gc0329->format.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) gc0329->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static void __gc0329_try_frame_size_fps(struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const struct gc0329_framesize **size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int fps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) const struct gc0329_framesize *fsize = &gc0329_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const struct gc0329_framesize *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int i = ARRAY_SIZE(gc0329_framesizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned int min_err = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned int err = abs(fsize->width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) + abs(fsize->height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (err < min_err && fsize->regs[0].addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) match = &gc0329_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fsize = &gc0329_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (i = 0; i < ARRAY_SIZE(gc0329_framesizes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (fsize->width == match->width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fsize->height == match->height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) fps >= DIV_ROUND_CLOSEST(fsize->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) fsize->max_fps.numerator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mf->width = match->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mf->height = match->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *size = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int gc0329_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int index = ARRAY_SIZE(gc0329_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct v4l2_mbus_framefmt *mf = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const struct gc0329_framesize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) __gc0329_try_frame_size_fps(mf, &size, gc0329->fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) while (--index >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (gc0329_formats[index].code == mf->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mf->code = gc0329_formats[index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_lock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *mf = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (gc0329->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gc0329->frame_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) gc0329->format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static void gc0329_get_module_inf(struct gc0329 *gc0329,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) strlcpy(inf->base.sensor, DRIVER_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) strlcpy(inf->base.module, gc0329->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) strlcpy(inf->base.lens, gc0329->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static long gc0329_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) gc0329_get_module_inf(gc0329, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) gc0329_set_streaming(gc0329, !!stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static long gc0329_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = gc0329_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = gc0329_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = gc0329_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int gc0329_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mutex_lock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (gc0329->streaming == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Stop Streaming Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) gc0329_set_streaming(gc0329, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) gc0329->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!IS_ERR(gc0329->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) gpiod_set_value_cansleep(gc0329->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!IS_ERR(gc0329->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) gpiod_set_value_cansleep(gc0329->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret = gc0329_write_array(client, gc0329_vga_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = gc0329_write_array(client, gc0329->frame_size->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) gc0329_set_streaming(gc0329, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) gc0329->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int gc0329_set_test_pattern(struct gc0329 *gc0329, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int gc0329_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct gc0329 *gc0329 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) container_of(ctrl->handler, struct gc0329, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return gc0329_set_test_pattern(gc0329, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct v4l2_ctrl_ops gc0329_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .s_ctrl = gc0329_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const char * const gc0329_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "Vertical Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * V4L2 subdev internal operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int gc0329_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct v4l2_mbus_framefmt *format =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) gc0329_get_default_format(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int gc0329_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) config->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) V4L2_MBUS_VSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) V4L2_MBUS_PCLK_SAMPLE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int gc0329_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mutex_lock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) fi->interval = gc0329->frame_size->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int gc0329_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) const struct gc0329_framesize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct v4l2_mbus_framefmt mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_dbg(&client->dev, "Setting %d/%d frame interval\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) fi->interval.numerator, fi->interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mutex_lock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) fi->interval.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mf = gc0329->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) __gc0329_try_frame_size_fps(&mf, &size, fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (gc0329->frame_size != size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = gc0329_write_array(client, size->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) gc0329->frame_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) gc0329->fps = fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mutex_unlock(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int gc0329_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (fie->index >= ARRAY_SIZE(gc0329_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (fie->code != MEDIA_BUS_FMT_YUYV8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) fie->width = gc0329_framesizes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) fie->height = gc0329_framesizes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) fie->interval = gc0329_framesizes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct v4l2_subdev_core_ops gc0329_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .ioctl = gc0329_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .compat_ioctl32 = gc0329_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const struct v4l2_subdev_video_ops gc0329_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .s_stream = gc0329_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .g_mbus_config = gc0329_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .g_frame_interval = gc0329_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .s_frame_interval = gc0329_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const struct v4l2_subdev_pad_ops gc0329_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .enum_mbus_code = gc0329_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .enum_frame_size = gc0329_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .enum_frame_interval = gc0329_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .get_fmt = gc0329_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .set_fmt = gc0329_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const struct v4l2_subdev_ops gc0329_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .core = &gc0329_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .video = &gc0329_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .pad = &gc0329_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const struct v4l2_subdev_internal_ops gc0329_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .open = gc0329_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int gc0329_detect(struct gc0329 *gc0329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct i2c_client *client = gc0329->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u8 pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Check sensor revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ret = gc0329_write(client, 0xfc, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret |= gc0329_read(client, REG_SC_CHIP_ID, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (pid != GC0329_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "Sensor detection failed (%X, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) pid, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "Found GC0329 id:%X sensor\n", pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!IS_ERR(gc0329->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) gpiod_set_value_cansleep(gc0329->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int __gc0329_power_on(struct gc0329 *gc0329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct device *dev = &gc0329->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!IS_ERR(gc0329->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = clk_set_rate(gc0329->xvclk, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dev_info(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!IS_ERR(gc0329->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) gpiod_set_value_cansleep(gc0329->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!IS_ERR(gc0329->supplies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = regulator_bulk_enable(GC0329_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) gc0329->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev_info(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!IS_ERR(gc0329->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) gpiod_set_value_cansleep(gc0329->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!IS_ERR(gc0329->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = clk_prepare_enable(gc0329->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_info(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) usleep_range(7000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static void __gc0329_power_off(struct gc0329 *gc0329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!IS_ERR(gc0329->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) clk_disable_unprepare(gc0329->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (!IS_ERR(gc0329->supplies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) regulator_bulk_disable(GC0329_NUM_SUPPLIES, gc0329->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (!IS_ERR(gc0329->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) gpiod_set_value_cansleep(gc0329->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int gc0329_configure_regulators(struct gc0329 *gc0329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) for (i = 0; i < GC0329_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) gc0329->supplies[i].supply = gc0329_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return devm_regulator_bulk_get(&gc0329->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GC0329_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) gc0329->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int gc0329_parse_of(struct gc0329 *gc0329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct device *dev = &gc0329->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) gc0329->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (IS_ERR(gc0329->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_info(dev, "Failed to get pwdn-gpios, maybe no used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ret = gc0329_configure_regulators(gc0329);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_info(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return __gc0329_power_on(gc0329);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int gc0329_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct gc0329 *gc0329;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) gc0329 = devm_kzalloc(&client->dev, sizeof(*gc0329), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (!gc0329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) &gc0329->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) &gc0329->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) &gc0329->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) &gc0329->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) gc0329->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) gc0329->xvclk = devm_clk_get(&client->dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (IS_ERR(gc0329->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(&client->dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) gc0329_parse_of(gc0329);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) gc0329->xvclk_frequency = clk_get_rate(gc0329->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (gc0329->xvclk_frequency < 6000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) gc0329->xvclk_frequency > 27000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) v4l2_ctrl_handler_init(&gc0329->ctrls, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) gc0329->link_frequency =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) v4l2_ctrl_new_std(&gc0329->ctrls, &gc0329_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GC0329_PIXEL_RATE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GC0329_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) v4l2_ctrl_new_std_menu_items(&gc0329->ctrls, &gc0329_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ARRAY_SIZE(gc0329_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) 0, 0, gc0329_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) gc0329->sd.ctrl_handler = &gc0329->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (gc0329->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dev_err(&client->dev, "%s: control initialization error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) __func__, gc0329->ctrls.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return gc0329->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) sd = &gc0329->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) client->flags |= I2C_CLIENT_SCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) v4l2_i2c_subdev_init(sd, client, &gc0329_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) sd->internal_ops = &gc0329_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) gc0329->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret = media_entity_pads_init(&sd->entity, 1, &gc0329->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) v4l2_ctrl_handler_free(&gc0329->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) mutex_init(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) gc0329_get_default_format(&gc0329->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) gc0329->frame_size = &gc0329_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) gc0329->format.width = gc0329_framesizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) gc0329->format.height = gc0329_framesizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) gc0329->fps = DIV_ROUND_CLOSEST(gc0329_framesizes[0].max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) gc0329_framesizes[0].max_fps.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = gc0329_detect(gc0329);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (strcmp(gc0329->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) gc0329->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) DRIVER_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) v4l2_ctrl_handler_free(&gc0329->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mutex_destroy(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) __gc0329_power_off(gc0329);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int gc0329_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct gc0329 *gc0329 = to_gc0329(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) v4l2_ctrl_handler_free(&gc0329->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mutex_destroy(&gc0329->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) __gc0329_power_off(gc0329);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const struct i2c_device_id gc0329_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) { "gc0329", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) MODULE_DEVICE_TABLE(i2c, gc0329_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct of_device_id gc0329_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) { .compatible = "galaxycore,gc0329", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) MODULE_DEVICE_TABLE(of, gc0329_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static struct i2c_driver gc0329_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .of_match_table = of_match_ptr(gc0329_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .probe = gc0329_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .remove = gc0329_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .id_table = gc0329_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return i2c_add_driver(&gc0329_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) i2c_del_driver(&gc0329_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) MODULE_DESCRIPTION("GC0329 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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