^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GC0312 CMOS Image Sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X01 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X02 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/media.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRIVER_NAME "gc0312"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GC0312_PIXEL_RATE (96 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * GC0312 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_SOFTWARE_STANDBY 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_SC_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_SC_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_NULL 0xFFFF /* Array end token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC0312_ID 0xb310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct sensor_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct gc0312_framesize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 max_exp_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct sensor_register *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct gc0312_pll_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 ctrl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct gc0312_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Output format Register Value (REG_FORMAT_CTRL00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sensor_register *format_ctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pll_ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gc0312_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GC0312_NUM_SUPPLIES ARRAY_SIZE(gc0312_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct gc0312 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int xvclk_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct regulator_bulk_data supplies[GC0312_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_ctrl *link_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct gc0312_framesize *frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct sensor_register gc0312_vga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {0xfe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {0xfe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {0xfc, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {0xfc, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0xf2, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*output_disable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0xf3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0xf7, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0xf8, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0xf9, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0xfa, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*CISCTL reg*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x00, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x01, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x02, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x03, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x04, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x0c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x0d, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x0e, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x0f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x10, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x16, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x17, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x18, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x19, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x1b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*1c travis 20140929 update for lag*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x1c, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x1e, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x1f, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*0x89 travis20140801*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x20, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x21, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*b0 travis 20140929 update for lag*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x22, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x23, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x24, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x34, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*BLK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x26, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x28, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x29, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x32, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x33, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x37, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x38, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x47, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x4e, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0xa8, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0xa9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*ISP reg*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x40, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x41, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x42, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x44, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x45, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*sync 02*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x46, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x4a, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x4b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x4c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x4d, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x4f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x50, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x54, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x55, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x56, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x57, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x58, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*GAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x70, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x5a, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x5b, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x5c, 0xed},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x77, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x78, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x79, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*DNDD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x82, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x83, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x89, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*EEINTP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x8f, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x90, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x91, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x92, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x93, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x94, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x95, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x96, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*ASDE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x9a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x9b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x9c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x9d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xa1, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0xa2, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0xa4, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0xa5, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0xaa, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0xac, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*GAMMA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0xbf, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0xc0, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0xc1, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0xc2, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0xc3, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0xc4, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0xc5, 0x7a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xc6, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0xc7, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0xc8, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0xc9, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xca, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0xcb, 0xdd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0xcc, 0xe5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0xcd, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0xce, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0xcf, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*YCP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0xd0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0xd1, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0xd2, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xd3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xd6, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xd7, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xd8, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xdd, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*AEC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x05, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x06, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x07, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x08, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x0a, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x0b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x12, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x13, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x18, 0x95},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x19, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x1f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x20, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3f, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x40, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x03, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x44, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*AWB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x1c, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x21, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x50, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x56, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x59, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x5b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x61, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x62, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x63, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x65, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x66, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x67, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x69, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x6a, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x6b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x6c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x6d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x6e, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x6f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x76, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x78, 0xaf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x79, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x7a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x7b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x7c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x90, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x91, 0xbe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x92, 0xe2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x93, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x95, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x96, 0xe2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x97, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x98, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x9a, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x9b, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x9c, 0xc3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x9d, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x9f, 0xc7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0xa0, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0xa1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0xa2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x86, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x89, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0xa4, 0xb9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0xa5, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0xa6, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0xa7, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0xa9, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0xaa, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0xab, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0xac, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0xae, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0xaf, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0xb0, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0xb1, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0xb3, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0xb4, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0xb5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x8b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x8c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x8d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x8e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x94, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x99, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x9e, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0xa3, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x8a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0xa8, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0xad, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0xb2, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0xb7, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x8f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0xb8, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0xb9, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*CC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*skin white*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0xd0, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0xd1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0xd2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0xd3, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0xd4, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0xd5, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0xd6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0xd7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0xd8, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0xd9, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0xda, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0xdb, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*LSC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0xc1, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0xc2, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0xc3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0xc4, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0xc5, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0xc6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0xc7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0xc8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0xc9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0xdc, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0xdd, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0xdf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0xde, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*Histogram*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x01, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x0b, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x0e, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x0f, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x10, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x12, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x15, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x16, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x17, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*Measure Window*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0xcc, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0xcd, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0xce, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0xcf, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*dark sun*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x45, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x46, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x47, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x48, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x4f, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*banding*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*HB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x06, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*VB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x08, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*anti-flicker step [11:8]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x25, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*anti-flicker step [7:0]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x26, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*exp level 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x27, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x28, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*exp level 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x29, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x2a, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*7.14fps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x2b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x2c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*exp level 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x2d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x2e, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*DVP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct gc0312_framesize gc0312_framesizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .regs = gc0312_vga_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .max_exp_lines = 488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct gc0312_pixfmt gc0312_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static inline struct gc0312 *to_gc0312(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return container_of(sd, struct gc0312, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int gc0312_write(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "gc0312 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int gc0312_read(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "gc0312 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int gc0312_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct sensor_register *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = gc0312_write(client, regs[i].addr, regs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void gc0312_get_default_format(struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) format->width = gc0312_framesizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) format->height = gc0312_framesizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) format->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) format->code = gc0312_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void gc0312_set_streaming(struct gc0312 *gc0312, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct i2c_client *client = gc0312->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = gc0312_write(client, REG_SOFTWARE_STANDBY, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&client->dev, "gc0312 soft standby failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * V4L2 subdev video and pad level operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int gc0312_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (code->index >= ARRAY_SIZE(gc0312_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) code->code = gc0312_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int gc0312_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int i = ARRAY_SIZE(gc0312_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (fse->index >= ARRAY_SIZE(gc0312_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (fse->code == gc0312_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) fse->code = gc0312_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fse->min_width = gc0312_framesizes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) fse->max_width = fse->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) fse->max_height = gc0312_framesizes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) fse->min_height = fse->max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int gc0312_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct gc0312 *gc0312 = to_gc0312(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mutex_lock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) fmt->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mutex_unlock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mutex_lock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fmt->format = gc0312->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mutex_unlock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gc0312->format.code, gc0312->format.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) gc0312->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static void __gc0312_try_frame_size(struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) const struct gc0312_framesize **size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) const struct gc0312_framesize *fsize = &gc0312_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) const struct gc0312_framesize *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int i = ARRAY_SIZE(gc0312_framesizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned int min_err = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned int err = abs(fsize->width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) + abs(fsize->height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (err < min_err && fsize->regs[0].addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) match = &gc0312_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mf->width = match->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mf->height = match->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) *size = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int gc0312_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int index = ARRAY_SIZE(gc0312_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct v4l2_mbus_framefmt *mf = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) const struct gc0312_framesize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct gc0312 *gc0312 = to_gc0312(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __gc0312_try_frame_size(mf, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) while (--index >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (gc0312_formats[index].code == mf->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mf->code = gc0312_formats[index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mutex_lock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) *mf = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (gc0312->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mutex_unlock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) gc0312->frame_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) gc0312->format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mutex_unlock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void gc0312_get_module_inf(struct gc0312 *gc0312,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) strlcpy(inf->base.sensor, DRIVER_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) strlcpy(inf->base.module, gc0312->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) strlcpy(inf->base.lens, gc0312->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static long gc0312_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct gc0312 *gc0312 = to_gc0312(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) gc0312_get_module_inf(gc0312, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) gc0312_set_streaming(gc0312, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) gc0312_set_streaming(gc0312, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static long gc0312_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = gc0312_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = gc0312_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = gc0312_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int gc0312_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct gc0312 *gc0312 = to_gc0312(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mutex_lock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (gc0312->streaming == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Stop Streaming Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) gc0312_set_streaming(gc0312, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) gc0312->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!IS_ERR(gc0312->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) gpiod_set_value_cansleep(gc0312->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!IS_ERR(gc0312->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) gpiod_set_value_cansleep(gc0312->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = gc0312_write_array(client, gc0312->frame_size->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) gc0312_set_streaming(gc0312, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) gc0312->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mutex_unlock(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int gc0312_set_test_pattern(struct gc0312 *gc0312, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int gc0312_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct gc0312 *gc0312 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) container_of(ctrl->handler, struct gc0312, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return gc0312_set_test_pattern(gc0312, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const struct v4l2_ctrl_ops gc0312_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .s_ctrl = gc0312_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const char * const gc0312_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "Vertical Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * V4L2 subdev internal operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int gc0312_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct v4l2_mbus_framefmt *format =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) gc0312_get_default_format(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int gc0312_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) config->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) V4L2_MBUS_VSYNC_ACTIVE_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) V4L2_MBUS_PCLK_SAMPLE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int gc0312_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (fie->index >= ARRAY_SIZE(gc0312_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (fie->code != MEDIA_BUS_FMT_YUYV8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) fie->width = gc0312_framesizes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) fie->height = gc0312_framesizes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) fie->interval = gc0312_framesizes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct v4l2_subdev_core_ops gc0312_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .ioctl = gc0312_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .compat_ioctl32 = gc0312_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct v4l2_subdev_video_ops gc0312_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .s_stream = gc0312_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .g_mbus_config = gc0312_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct v4l2_subdev_pad_ops gc0312_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .enum_mbus_code = gc0312_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .enum_frame_size = gc0312_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .enum_frame_interval = gc0312_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .get_fmt = gc0312_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .set_fmt = gc0312_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const struct v4l2_subdev_ops gc0312_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .core = &gc0312_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .video = &gc0312_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .pad = &gc0312_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const struct v4l2_subdev_internal_ops gc0312_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .open = gc0312_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int gc0312_detect(struct gc0312 *gc0312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct i2c_client *client = gc0312->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u8 pid, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* Check sensor revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = gc0312_read(client, REG_SC_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = gc0312_read(client, REG_SC_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned short id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (id != GC0312_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "Sensor detection failed (%04X, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_info(&client->dev, "Found GC%04X sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!IS_ERR(gc0312->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) gpiod_set_value_cansleep(gc0312->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int __gc0312_power_on(struct gc0312 *gc0312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct device *dev = &gc0312->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!IS_ERR(gc0312->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = clk_set_rate(gc0312->xvclk, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_info(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (!IS_ERR(gc0312->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) gpiod_set_value_cansleep(gc0312->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!IS_ERR(gc0312->supplies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = regulator_bulk_enable(GC0312_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) gc0312->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_info(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!IS_ERR(gc0312->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) gpiod_set_value_cansleep(gc0312->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (!IS_ERR(gc0312->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = clk_prepare_enable(gc0312->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_info(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) usleep_range(7000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static void __gc0312_power_off(struct gc0312 *gc0312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!IS_ERR(gc0312->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) clk_disable_unprepare(gc0312->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!IS_ERR(gc0312->supplies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) regulator_bulk_disable(GC0312_NUM_SUPPLIES, gc0312->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!IS_ERR(gc0312->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) gpiod_set_value_cansleep(gc0312->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int gc0312_configure_regulators(struct gc0312 *gc0312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) for (i = 0; i < GC0312_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) gc0312->supplies[i].supply = gc0312_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return devm_regulator_bulk_get(&gc0312->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GC0312_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) gc0312->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int gc0312_parse_of(struct gc0312 *gc0312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct device *dev = &gc0312->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) gc0312->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (IS_ERR(gc0312->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dev_info(dev, "Failed to get pwdn-gpios, maybe no used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = gc0312_configure_regulators(gc0312);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_info(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return __gc0312_power_on(gc0312);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int gc0312_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct gc0312 *gc0312;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) gc0312 = devm_kzalloc(&client->dev, sizeof(*gc0312), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!gc0312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) &gc0312->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) &gc0312->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) &gc0312->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) &gc0312->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) gc0312->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) gc0312->xvclk = devm_clk_get(&client->dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (IS_ERR(gc0312->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dev_err(&client->dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) gc0312_parse_of(gc0312);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) gc0312->xvclk_frequency = clk_get_rate(gc0312->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (gc0312->xvclk_frequency < 6000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) gc0312->xvclk_frequency > 27000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) v4l2_ctrl_handler_init(&gc0312->ctrls, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) gc0312->link_frequency =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) v4l2_ctrl_new_std(&gc0312->ctrls, &gc0312_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GC0312_PIXEL_RATE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GC0312_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) v4l2_ctrl_new_std_menu_items(&gc0312->ctrls, &gc0312_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ARRAY_SIZE(gc0312_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) 0, 0, gc0312_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) gc0312->sd.ctrl_handler = &gc0312->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (gc0312->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_err(&client->dev, "%s: control initialization error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) __func__, gc0312->ctrls.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return gc0312->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) sd = &gc0312->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) client->flags |= I2C_CLIENT_SCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) v4l2_i2c_subdev_init(sd, client, &gc0312_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) sd->internal_ops = &gc0312_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) gc0312->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = media_entity_pads_init(&sd->entity, 1, &gc0312->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) v4l2_ctrl_handler_free(&gc0312->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mutex_init(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) gc0312_get_default_format(&gc0312->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) gc0312->frame_size = &gc0312_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = gc0312_detect(gc0312);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (strcmp(gc0312->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) gc0312->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) DRIVER_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) v4l2_ctrl_handler_free(&gc0312->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mutex_destroy(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) __gc0312_power_off(gc0312);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int gc0312_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct gc0312 *gc0312 = to_gc0312(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) v4l2_ctrl_handler_free(&gc0312->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mutex_destroy(&gc0312->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) __gc0312_power_off(gc0312);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static const struct i2c_device_id gc0312_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { "gc0312", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) MODULE_DEVICE_TABLE(i2c, gc0312_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static const struct of_device_id gc0312_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) { .compatible = "galaxycore,gc0312", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) MODULE_DEVICE_TABLE(of, gc0312_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static struct i2c_driver gc0312_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .of_match_table = of_match_ptr(gc0312_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .probe = gc0312_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .remove = gc0312_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .id_table = gc0312_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return i2c_add_driver(&gc0312_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) i2c_del_driver(&gc0312_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) MODULE_DESCRIPTION("GC0312 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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