^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc02m2 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 init version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1.add hflip/vflip function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2.modify set_gain_reg function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) //#define DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GC02M2_MIPI_LINK_FREQ 336000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* pixel rate = link frequency * 1 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC02M2_PIXEL_RATE (GC02M2_MIPI_LINK_FREQ * 2LL * 1LL / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GC02M2_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHIP_ID 0x02f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC02M2_REG_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GC02M2_REG_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC02M2_PAGE_SELECT 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC02M2_MODE_SELECT 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GC02M2_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC02M2_MODE_STREAMING 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC02M2_REG_EXPOSURE_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC02M2_REG_EXPOSURE_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GC02M2_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC02M2_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC02M2_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC02M2_ANALOG_GAIN_REG 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC02M2_PREGAIN_H_REG 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC02M2_PREGAIN_L_REG 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC02M2_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC02M2_GAIN_MAX 0x286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC02M2_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC02M2_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC02M2_REG_VTS_H 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC02M2_REG_VTS_L 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GC02M2_MIRROR_FLIP_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC200AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC200AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x02 : VAL & 0xfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GC02M2_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC02M2_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GC02M2_NAME "gc02m2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char * const gc02m2_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GC02M2_NUM_SUPPLIES ARRAY_SIZE(gc02m2_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define to_gc02m2(sd) container_of(sd, struct gc02m2, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gc02m2_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gc02m2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct regulator_bulk_data supplies[GC02M2_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct gc02m2_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct regval gc02m2_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*system*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0xfc, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0xf4, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0xf5, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0xf6, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0xf8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0xf9, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0xfa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0xfd, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0xfc, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x01, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0xfc, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0xfc, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0xfc, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*CISCTL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x87, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0xee, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x8c, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x03, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x04, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x41, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x42, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x05, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x06, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x08, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x9d, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x0a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x0d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x0e, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x19, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x24, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x56, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x5b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x5e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*analog Register width*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x21, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x44, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0xcc, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*analog mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x1a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x1f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x27, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x2b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x53, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0xe6, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*analog voltage*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x39, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x43, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x46, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x7c, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0xd0, 0xbe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0xd1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0xd2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0xd3, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0xde, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*analog current*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0xcd, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0xce, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*CISCTL RESET*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0xfc, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0xfe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0xfc, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0xfe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0xfe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0xe0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x53, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x87, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x89, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*Gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0xb0, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xb1, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0xfe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xd8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0xc0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0xc0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0xc0, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0xc0, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0xc0, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xc0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xc0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xc0, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0xc0, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0xc0, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0xc0, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0xc0, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0xc0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xc0, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0xc0, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0xc0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0xc0, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0xc0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0xc0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0xc0, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0xc0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0xc0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0xc0, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0xc0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0xc0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0xc0, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0xc0, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xc0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0xc0, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0xc0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0xc0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0xc0, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0xc0, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0xc0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0xc0, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0xc0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0xc0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0xc0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0xc0, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0xc0, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0xc0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0xc0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0xc0, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0xc0, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0xc0, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0xc0, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x9f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*BLK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x26, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x40, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x46, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x49, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x4a, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0xfe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x14, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x15, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x16, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*anti_blooming*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x41, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x4c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x4d, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x44, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x48, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*Window 1600X1200*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x90, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x92, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x94, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x95, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x96, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x97, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x98, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*mipi*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x01, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x03, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x04, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x15, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x21, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x22, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x23, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x25, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x26, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x29, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x2a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x2b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*out*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x8c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct gc02m2_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .width = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .height = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .exp_def = 0x0475,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .hts_def = 0x0448 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .vts_def = 0x04f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .reg_list = gc02m2_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GC02M2_MIPI_LINK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int gc02m2_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "gc02m2 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int gc02m2_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = gc02m2_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int gc02m2_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "gc02m2 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int gc02m2_get_reso_dist(const struct gc02m2_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct gc02m2_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) gc02m2_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dist = gc02m2_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static u32 GC02M2_AGC_Param[17][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 64 , 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 96 , 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 127 , 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 157 , 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 198 , 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 227 , 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { 259 , 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 287 , 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 318 , 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 356 , 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 392 , 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 420 , 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 451 , 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { 480 , 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { 513 , 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { 646 , 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { 0xffff , 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int gc02m2_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) const struct gc02m2_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) mode = gc02m2_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) gc02m2->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __v4l2_ctrl_modify_range(gc02m2->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __v4l2_ctrl_modify_range(gc02m2->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GC02M2_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int gc02m2_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct gc02m2_mode *mode = gc02m2->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int gc02m2_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) code->code = gc02m2->cur_mode->bus_fmt;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int gc02m2_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int gc02m2_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) const struct gc02m2_mode *mode = gc02m2->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void gc02m2_get_module_inf(struct gc02m2 *gc02m2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) strlcpy(inf->base.sensor, GC02M2_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) strlcpy(inf->base.module, gc02m2->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) strlcpy(inf->base.lens, gc02m2->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static long gc02m2_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int i, w, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) gc02m2_get_module_inf(gc02m2, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GC02M2_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GC02M2_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) hdr_cfg->hdr_mode = gc02m2->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) w = gc02m2->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) h = gc02m2->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) gc02m2->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_err(&gc02m2->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) w = gc02m2->cur_mode->hts_def - gc02m2->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) h = gc02m2->cur_mode->vts_def - gc02m2->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __v4l2_ctrl_modify_range(gc02m2->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __v4l2_ctrl_modify_range(gc02m2->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GC02M2_VTS_MAX - gc02m2->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static long gc02m2_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = gc02m2_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = gc02m2_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = gc02m2_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = gc02m2_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static inline u32 gc02m2_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return DIV_ROUND_UP(cycles, GC02M2_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int __gc02m2_power_on(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct device *dev = &gc02m2->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!IS_ERR_OR_NULL(gc02m2->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = pinctrl_select_state(gc02m2->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) gc02m2->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = clk_set_rate(gc02m2->xvclk, GC02M2_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (clk_get_rate(gc02m2->xvclk) != GC02M2_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = clk_prepare_enable(gc02m2->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = regulator_bulk_enable(GC02M2_NUM_SUPPLIES, gc02m2->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!IS_ERR(gc02m2->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) gpiod_set_value_cansleep(gc02m2->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!IS_ERR(gc02m2->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) gpiod_set_value_cansleep(gc02m2->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!IS_ERR(gc02m2->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) gpiod_set_value_cansleep(gc02m2->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) delay_us = gc02m2_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) gc02m2->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) clk_disable_unprepare(gc02m2->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static void __gc02m2_power_off(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct device *dev = &gc02m2->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!IS_ERR(gc02m2->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) gpiod_set_value_cansleep(gc02m2->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) clk_disable_unprepare(gc02m2->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!IS_ERR(gc02m2->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) gpiod_set_value_cansleep(gc02m2->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!IS_ERR_OR_NULL(gc02m2->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = pinctrl_select_state(gc02m2->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) gc02m2->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) regulator_bulk_disable(GC02M2_NUM_SUPPLIES, gc02m2->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) gc02m2->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int __gc02m2_start_stream(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = v4l2_ctrl_handler_setup(&gc02m2->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GC02M2_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int __gc02m2_stop_stream(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GC02M2_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int gc02m2_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct i2c_client *client = gc02m2->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (on == gc02m2->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = __gc02m2_start_stream(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) __gc02m2_stop_stream(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) gc02m2->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int gc02m2_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct i2c_client *client = gc02m2->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (gc02m2->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = gc02m2_write_array(gc02m2->client, gc02m2->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) gc02m2->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) gc02m2->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int gc02m2_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return __gc02m2_power_on(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int gc02m2_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __gc02m2_power_off(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int gc02m2_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) const struct gc02m2_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mutex_lock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mutex_unlock(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int gc02m2_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) const struct gc02m2_mode *mode = gc02m2->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) val = 1 << (GC02M2_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int gc02m2_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const struct dev_pm_ops gc02m2_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) SET_RUNTIME_PM_OPS(gc02m2_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) gc02m2_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const struct v4l2_subdev_internal_ops gc02m2_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .open = gc02m2_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const struct v4l2_subdev_core_ops gc02m2_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .s_power = gc02m2_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .ioctl = gc02m2_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .compat_ioctl32 = gc02m2_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const struct v4l2_subdev_video_ops gc02m2_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .s_stream = gc02m2_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .g_frame_interval = gc02m2_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const struct v4l2_subdev_pad_ops gc02m2_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .enum_mbus_code = gc02m2_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .enum_frame_size = gc02m2_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .enum_frame_interval = gc02m2_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .get_fmt = gc02m2_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .set_fmt = gc02m2_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .get_mbus_config = gc02m2_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const struct v4l2_subdev_ops gc02m2_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .core = &gc02m2_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .video = &gc02m2_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .pad = &gc02m2_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define DIGITAL_GAIN_BASE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int gc02m2_set_gain_reg(struct gc02m2 *gc02m2, u32 total_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct device *dev = &gc02m2->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int ret = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u32 dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_dbg(dev, "total_gain = 0x%04x!\n", total_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (total_gain < 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) total_gain = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) for (i = 15; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (total_gain >= GC02M2_AGC_Param[i][0] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) total_gain < GC02M2_AGC_Param[i + 1][0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret |= gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GC02M2_ANALOG_GAIN_REG, GC02M2_AGC_Param[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dgain = total_gain * DIGITAL_GAIN_BASE / GC02M2_AGC_Param[i][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev_dbg(dev, "AGC_Param[%d][0] = %d dgain = 0x%04x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) i, GC02M2_AGC_Param[i][0], dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret |= gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GC02M2_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dgain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret |= gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GC02M2_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dgain & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int gc02m2_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct gc02m2 *gc02m2 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct gc02m2, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct i2c_client *client = gc02m2->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) max = gc02m2->cur_mode->height + ctrl->val - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) __v4l2_ctrl_modify_range(gc02m2->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) gc02m2->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) gc02m2->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) gc02m2->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret |= gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GC02M2_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) (ctrl->val >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret |= gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GC02M2_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = gc02m2_set_gain_reg(gc02m2, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) vts = ctrl->val + gc02m2->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) (vts >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret |= gc02m2_write_reg(gc02m2->client, GC02M2_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ret = gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret |= gc02m2_read_reg(gc02m2->client, GC02M2_MIRROR_FLIP_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret |= gc02m2_write_reg(client, GC02M2_MIRROR_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) SC200AI_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret = gc02m2_write_reg(gc02m2->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GC02M2_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret |= gc02m2_read_reg(gc02m2->client, GC02M2_MIRROR_FLIP_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret |= gc02m2_write_reg(client, GC02M2_MIRROR_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) SC200AI_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static const struct v4l2_ctrl_ops gc02m2_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .s_ctrl = gc02m2_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int gc02m2_check_sensor_id(struct gc02m2 *gc02m2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct device *dev = &gc02m2->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u8 pid, ver = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) unsigned short id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = gc02m2_read_reg(client, GC02M2_REG_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_err(dev, "Read chip ID H register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = gc02m2_read_reg(client, GC02M2_REG_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_err(dev, "Read chip ID L register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static int gc02m2_configure_regulators(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) for (i = 0; i < GC02M2_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) gc02m2->supplies[i].supply = gc02m2_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return devm_regulator_bulk_get(&gc02m2->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GC02M2_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) gc02m2->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int gc02m2_parse_of(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct device *dev = &gc02m2->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) gc02m2->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (1 == gc02m2->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) gc02m2->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) gc02m2->pixel_rate = GC02M2_MIPI_LINK_FREQ * 2U * gc02m2->lane_num / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) gc02m2->lane_num, gc02m2->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dev_err(dev, "unsupported lane_num(%d)\n", gc02m2->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int gc02m2_initialize_controls(struct gc02m2 *gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) const struct gc02m2_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct device *dev = &gc02m2->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_info(dev, "Enter %s(%d) !\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) handler = &gc02m2->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) mode = gc02m2->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) handler->lock = &gc02m2->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 0, GC02M2_PIXEL_RATE, 1, GC02M2_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) gc02m2->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (gc02m2->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) gc02m2->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) gc02m2->vblank = v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) GC02M2_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) exposure_max = mode->vts_def - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) gc02m2->exposure = v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) V4L2_CID_EXPOSURE, GC02M2_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) exposure_max, GC02M2_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) gc02m2->anal_gain = v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) V4L2_CID_ANALOGUE_GAIN, GC02M2_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) GC02M2_GAIN_MAX, GC02M2_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GC02M2_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) v4l2_ctrl_new_std(handler, &gc02m2_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(&gc02m2->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) gc02m2->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int gc02m2_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct gc02m2 *gc02m2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) gc02m2 = devm_kzalloc(dev, sizeof(*gc02m2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!gc02m2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) &gc02m2->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) &gc02m2->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) &gc02m2->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &gc02m2->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) gc02m2->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) gc02m2->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) gc02m2->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (IS_ERR(gc02m2->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) gc02m2->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (IS_ERR(gc02m2->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) gc02m2->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (IS_ERR(gc02m2->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = gc02m2_parse_of(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) gc02m2->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!IS_ERR(gc02m2->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) gc02m2->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pinctrl_lookup_state(gc02m2->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (IS_ERR(gc02m2->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) gc02m2->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) pinctrl_lookup_state(gc02m2->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (IS_ERR(gc02m2->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret = gc02m2_configure_regulators(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mutex_init(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) sd = &gc02m2->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) v4l2_i2c_subdev_init(sd, client, &gc02m2_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = gc02m2_initialize_controls(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = __gc02m2_power_on(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret = gc02m2_check_sensor_id(gc02m2, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) sd->internal_ops = &gc02m2_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) gc02m2->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ret = media_entity_pads_init(&sd->entity, 1, &gc02m2->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (strcmp(gc02m2->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) gc02m2->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) GC02M2_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) __gc02m2_power_off(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) v4l2_ctrl_handler_free(&gc02m2->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mutex_destroy(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static int gc02m2_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct gc02m2 *gc02m2 = to_gc02m2(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) v4l2_ctrl_handler_free(&gc02m2->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) mutex_destroy(&gc02m2->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) __gc02m2_power_off(gc02m2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static const struct of_device_id gc02m2_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) { .compatible = "galaxycore,gc02m2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) MODULE_DEVICE_TABLE(of, gc02m2_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const struct i2c_device_id gc02m2_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) { "galaxycore,gc02m2", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static struct i2c_driver gc02m2_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .name = GC02M2_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .pm = &gc02m2_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .of_match_table = of_match_ptr(gc02m2_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .probe = &gc02m2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .remove = &gc02m2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .id_table = gc02m2_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return i2c_add_driver(&gc02m2_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) i2c_del_driver(&gc02m2_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) MODULE_DESCRIPTION("GalaxyCore gc02m2 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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