Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (C) 2018 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DW9807_MAX_FOCUS_POS	1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * This sets the minimum granularity for the focus positions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * A value of 1 gives maximum accuracy for a desired focus position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DW9807_FOCUS_STEPS	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * This acts as the minimum granularity of lens movement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Keep this value power of 2, so the control steps can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * uniformly adjusted for gradual lens movement, with desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * number of control steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DW9807_CTRL_STEPS	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DW9807_CTRL_DELAY_US	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DW9807_CTL_ADDR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * DW9807 separates two registers to control the VCM position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * One for MSB value, another is LSB value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DW9807_MSB_ADDR		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DW9807_LSB_ADDR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DW9807_STATUS_ADDR	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DW9807_MODE_ADDR	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DW9807_RESONANCE_ADDR	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX_RETRY		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct dw9807_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct v4l2_ctrl_handler ctrls_vcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u16 current_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static inline struct dw9807_device *sd_to_dw9807_vcm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 					struct v4l2_subdev *subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return container_of(subdev, struct dw9807_device, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int dw9807_i2c_check(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	const char status_addr = DW9807_STATUS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	char status_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ret = i2c_master_send(client, &status_addr, sizeof(status_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		dev_err(&client->dev, "I2C write STATUS address fail ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ret = i2c_master_recv(client, &status_result, sizeof(status_result));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		dev_err(&client->dev, "I2C read STATUS value fail ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return status_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int dw9807_set_dac(struct i2c_client *client, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	const char tx_data[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		DW9807_MSB_ADDR, ((data >> 8) & 0x03), (data & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * According to the datasheet, need to check the bus status before we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * write VCM position. This ensure that we really write the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * into the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ret = readx_poll_timeout(dw9807_i2c_check, client, val, val <= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			DW9807_CTRL_DELAY_US, MAX_RETRY * DW9807_CTRL_DELAY_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (ret || val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				"Cannot do the write operation because VCM is busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return ret ? -EBUSY : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Write VCM position to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ret = i2c_master_send(client, tx_data, sizeof(tx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			"I2C write MSB fail ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int dw9807_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct dw9807_device *dev_vcm = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		struct dw9807_device, ctrls_vcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		struct i2c_client *client = v4l2_get_subdevdata(&dev_vcm->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		dev_vcm->current_val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return dw9807_set_dac(client, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct v4l2_ctrl_ops dw9807_vcm_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.s_ctrl = dw9807_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int dw9807_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	rval = pm_runtime_get_sync(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (rval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		pm_runtime_put_noidle(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int dw9807_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	pm_runtime_put(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct v4l2_subdev_internal_ops dw9807_int_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.open = dw9807_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.close = dw9807_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct v4l2_subdev_ops dw9807_ops = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void dw9807_subdev_cleanup(struct dw9807_device *dw9807_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	v4l2_async_unregister_subdev(&dw9807_dev->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	v4l2_ctrl_handler_free(&dw9807_dev->ctrls_vcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	media_entity_cleanup(&dw9807_dev->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int dw9807_init_controls(struct dw9807_device *dev_vcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct v4l2_ctrl_handler *hdl = &dev_vcm->ctrls_vcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	const struct v4l2_ctrl_ops *ops = &dw9807_vcm_ctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct i2c_client *client = v4l2_get_subdevdata(&dev_vcm->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	v4l2_ctrl_handler_init(hdl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			  0, DW9807_MAX_FOCUS_POS, DW9807_FOCUS_STEPS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	dev_vcm->sd.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		dev_err(&client->dev, "%s fail error: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			__func__, hdl->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int dw9807_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct dw9807_device *dw9807_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	dw9807_dev = devm_kzalloc(&client->dev, sizeof(*dw9807_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (dw9807_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	v4l2_i2c_subdev_init(&dw9807_dev->sd, client, &dw9807_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	dw9807_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	dw9807_dev->sd.internal_ops = &dw9807_int_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	rval = dw9807_init_controls(dw9807_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	rval = media_entity_pads_init(&dw9807_dev->sd.entity, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	dw9807_dev->sd.entity.function = MEDIA_ENT_F_LENS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	rval = v4l2_async_register_subdev(&dw9807_dev->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (rval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	pm_runtime_idle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) err_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	v4l2_ctrl_handler_free(&dw9807_dev->ctrls_vcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	media_entity_cleanup(&dw9807_dev->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int dw9807_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct dw9807_device *dw9807_dev = sd_to_dw9807_vcm(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	dw9807_subdev_cleanup(dw9807_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * This function sets the vcm position, so it consumes least current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * The lens position is gradually moved in units of DW9807_CTRL_STEPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * to make the movements smoothly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int __maybe_unused dw9807_vcm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct dw9807_device *dw9807_dev = sd_to_dw9807_vcm(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	const char tx_data[2] = { DW9807_CTL_ADDR, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	for (val = dw9807_dev->current_val & ~(DW9807_CTRL_STEPS - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	     val >= 0; val -= DW9807_CTRL_STEPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		ret = dw9807_set_dac(client, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			dev_err_once(dev, "%s I2C failure: %d", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		usleep_range(DW9807_CTRL_DELAY_US, DW9807_CTRL_DELAY_US + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* Power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = i2c_master_send(client, tx_data, sizeof(tx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		dev_err(&client->dev, "I2C write CTL fail ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * This function sets the vcm position to the value set by the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * through v4l2_ctrl_ops s_ctrl handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * The lens position is gradually moved in units of DW9807_CTRL_STEPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * to make the movements smoothly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int  __maybe_unused dw9807_vcm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct dw9807_device *dw9807_dev = sd_to_dw9807_vcm(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	const char tx_data[2] = { DW9807_CTL_ADDR, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = i2c_master_send(client, tx_data, sizeof(tx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(&client->dev, "I2C write CTL fail ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	for (val = dw9807_dev->current_val % DW9807_CTRL_STEPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	     val < dw9807_dev->current_val + DW9807_CTRL_STEPS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	     val += DW9807_CTRL_STEPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		ret = dw9807_set_dac(client, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			dev_err_ratelimited(dev, "%s I2C failure: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 						__func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		usleep_range(DW9807_CTRL_DELAY_US, DW9807_CTRL_DELAY_US + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct of_device_id dw9807_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ .compatible = "dongwoon,dw9807-vcm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_DEVICE_TABLE(of, dw9807_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct dev_pm_ops dw9807_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	SET_SYSTEM_SLEEP_PM_OPS(dw9807_vcm_suspend, dw9807_vcm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	SET_RUNTIME_PM_OPS(dw9807_vcm_suspend, dw9807_vcm_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct i2c_driver dw9807_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.name = "dw9807",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.pm = &dw9807_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.of_match_table = dw9807_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.probe_new = dw9807_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.remove = dw9807_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) module_i2c_driver(dw9807_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MODULE_AUTHOR("Chiang, Alan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_DESCRIPTION("DW9807 VCM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_LICENSE("GPL v2");