^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DW9768_NAME "dw9768"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DW9768_MAX_FOCUS_POS (1024 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This sets the minimum granularity for the focus positions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * A value of 1 gives maximum accuracy for a desired focus position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DW9768_FOCUS_STEPS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Ring control and Power control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Bit[1] RING_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0: Direct mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 1: AAC mode (ringing control mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Bit[0] PD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0: Normal operation mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 1: Power down mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * DW9768 requires waiting time of Topr after PD reset takes place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DW9768_RING_PD_CONTROL_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DW9768_PD_MODE_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DW9768_PD_MODE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DW9768_AAC_MODE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * DW9768 separates two registers to control the VCM position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * One for MSB value, another is LSB value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DAC_MSB: D[9:8] (ADD: 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * DAC_LSB: D[7:0] (ADD: 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * D[9:0] DAC data input: positive output current = D[9:0] / 1023 * 100[mA]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DW9768_MSB_ADDR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DW9768_LSB_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DW9768_STATUS_ADDR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * AAC mode control & prescale register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Bit[7:5] Namely AC[2:0], decide the VCM mode and operation time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 001 AAC2 0.48 x Tvib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 010 AAC3 0.70 x Tvib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 011 AAC4 0.75 x Tvib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 101 AAC8 1.13 x Tvib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 000 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 001 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 010 1/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 011 1/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 100 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 101 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DW9768_AAC_PRESC_REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DW9768_AAC_MODE_SEL_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DW9768_CLOCK_PRE_SCALE_SEL_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * VCM period of vibration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Dividing Rate is the internal clock dividing rate that is defined at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * PRESCALE register (ADD: 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DW9768_AAC_TIME_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * DW9768 requires waiting time (delay time) of t_OPR after power-up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * or in the case of PD reset taking place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DW9768_T_OPR_US 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DW9768_TVIB_MS_BASE10 (64 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DW9768_AAC_MODE_DEFAULT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DW9768_AAC_TIME_DEFAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DW9768_CLOCK_PRE_SCALE_DEFAULT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * This acts as the minimum granularity of lens movement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Keep this value power of 2, so the control steps can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * uniformly adjusted for gradual lens movement, with desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * number of control steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DW9768_MOVE_STEPS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const dw9768_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "vin", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "vdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* dw9768 device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct dw9768 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct regulator_bulk_data supplies[ARRAY_SIZE(dw9768_supply_names)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct v4l2_ctrl *focus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 aac_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 aac_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 clock_presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 move_delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline struct dw9768 *sd_to_dw9768(struct v4l2_subdev *subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return container_of(subdev, struct dw9768, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct regval_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct dw9768_aac_mode_ot_multi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 aac_mode_enum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ot_multi_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct dw9768_clk_presc_dividing_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 clk_presc_enum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 dividing_rate_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct dw9768_aac_mode_ot_multi aac_mode_ot_multi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {1, 48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {2, 70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {3, 75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {5, 113},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct dw9768_clk_presc_dividing_rate presc_dividing_rate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0, 200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {1, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {2, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {3, 25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {4, 800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {5, 400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static u32 dw9768_find_ot_multi(u32 aac_mode_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 cur_ot_multi_base100 = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 0; i < ARRAY_SIZE(aac_mode_ot_multi); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (aac_mode_ot_multi[i].aac_mode_enum == aac_mode_param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cur_ot_multi_base100 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) aac_mode_ot_multi[i].ot_multi_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return cur_ot_multi_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u32 dw9768_find_dividing_rate(u32 presc_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 cur_clk_dividing_rate_base100 = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; i < ARRAY_SIZE(presc_dividing_rate); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (presc_dividing_rate[i].clk_presc_enum == presc_param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cur_clk_dividing_rate_base100 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) presc_dividing_rate[i].dividing_rate_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return cur_clk_dividing_rate_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * DW9768_AAC_PRESC_REG & DW9768_AAC_TIME_REG determine VCM operation time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * For current VCM mode: AAC3, Operation Time would be 0.70 x Tvib.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Below is calculation of the operation delay for each step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline u32 dw9768_cal_move_delay(u32 aac_mode_param, u32 presc_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 aac_timing_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 Tvib_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 ot_multi_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 clk_dividing_rate_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ot_multi_base100 = dw9768_find_ot_multi(aac_mode_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clk_dividing_rate_base100 = dw9768_find_dividing_rate(presc_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) Tvib_us = (DW9768_TVIB_MS_BASE10 + aac_timing_param) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk_dividing_rate_base100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return Tvib_us * ot_multi_base100 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int dw9768_mod_reg(struct dw9768 *dw9768, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val = ((unsigned char)ret & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int dw9768_set_dac(struct dw9768 *dw9768, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Write VCM position to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return i2c_smbus_write_word_swapped(client, DW9768_MSB_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int dw9768_init(struct dw9768 *dw9768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Reset DW9768_RING_PD_CONTROL_REG to default status 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DW9768_PD_MODE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * DW9769 requires waiting delay time of t_OPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * after PD reset takes place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Set DW9768_RING_PD_CONTROL_REG to DW9768_AAC_MODE_EN(0x01) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DW9768_AAC_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Set AAC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DW9768_AAC_MODE_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dw9768->aac_mode << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Set clock presc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (dw9768->clock_presc != DW9768_CLOCK_PRE_SCALE_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DW9768_CLOCK_PRE_SCALE_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dw9768->clock_presc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Set AAC Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (dw9768->aac_timing != DW9768_AAC_TIME_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = i2c_smbus_write_byte_data(client, DW9768_AAC_TIME_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dw9768->aac_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (val = dw9768->focus->val % DW9768_MOVE_STEPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val <= dw9768->focus->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val += DW9768_MOVE_STEPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = dw9768_set_dac(dw9768, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(&client->dev, "I2C failure: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) usleep_range(dw9768->move_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dw9768->move_delay_us + 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int dw9768_release(struct dw9768 *dw9768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val = round_down(dw9768->focus->val, DW9768_MOVE_STEPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) for ( ; val >= 0; val -= DW9768_MOVE_STEPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = dw9768_set_dac(dw9768, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(&client->dev, "I2C write fail: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) usleep_range(dw9768->move_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dw9768->move_delay_us + 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DW9768_PD_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * DW9769 requires waiting delay time of t_OPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * after PD reset takes place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int dw9768_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct dw9768 *dw9768 = sd_to_dw9768(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dw9768_release(dw9768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dw9768->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int dw9768_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct dw9768 *dw9768 = sd_to_dw9768(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = regulator_bulk_enable(ARRAY_SIZE(dw9768_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dw9768->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(dev, "failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * The datasheet refers to t_OPR that needs to be waited before sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * I2C commands after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = dw9768_init(dw9768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dw9768->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int dw9768_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct dw9768 *dw9768 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct dw9768, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return dw9768_set_dac(dw9768, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct v4l2_ctrl_ops dw9768_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .s_ctrl = dw9768_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int dw9768_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = pm_runtime_get_sync(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pm_runtime_put_noidle(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int dw9768_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pm_runtime_put(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct v4l2_subdev_internal_ops dw9768_int_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .open = dw9768_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .close = dw9768_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct v4l2_subdev_ops dw9768_ops = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int dw9768_init_controls(struct dw9768 *dw9768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct v4l2_ctrl_handler *hdl = &dw9768->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const struct v4l2_ctrl_ops *ops = &dw9768_ctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) v4l2_ctrl_handler_init(hdl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dw9768->focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DW9768_MAX_FOCUS_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DW9768_FOCUS_STEPS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (hdl->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dw9768->sd.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int dw9768_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct dw9768 *dw9768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dw9768 = devm_kzalloc(dev, sizeof(*dw9768), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!dw9768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Initialize subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) v4l2_i2c_subdev_init(&dw9768->sd, client, &dw9768_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dw9768->aac_mode = DW9768_AAC_MODE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dw9768->aac_timing = DW9768_AAC_TIME_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dw9768->clock_presc = DW9768_CLOCK_PRE_SCALE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Optional indication of AAC mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &dw9768->aac_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Optional indication of clock pre-scale select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,clock-presc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &dw9768->clock_presc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Optional indication of AAC Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-timing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &dw9768->aac_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dw9768->move_delay_us = dw9768_cal_move_delay(dw9768->aac_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dw9768->clock_presc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dw9768->aac_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0; i < ARRAY_SIZE(dw9768_supply_names); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dw9768->supplies[i].supply = dw9768_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dw9768_supply_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dw9768->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(dev, "failed to get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Initialize controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = dw9768_init_controls(dw9768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Initialize subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dw9768->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dw9768->sd.internal_ops = &dw9768_int_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = media_entity_pads_init(&dw9768->sd.entity, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dw9768->sd.entity.function = MEDIA_ENT_F_LENS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!pm_runtime_enabled(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = dw9768_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_err(dev, "failed to power on: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = v4l2_async_register_subdev(&dw9768->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "failed to register V4L2 subdev: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pm_runtime_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dw9768_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) media_entity_cleanup(&dw9768->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) v4l2_ctrl_handler_free(&dw9768->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int dw9768_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct dw9768 *dw9768 = sd_to_dw9768(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) v4l2_async_unregister_subdev(&dw9768->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) v4l2_ctrl_handler_free(&dw9768->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) media_entity_cleanup(&dw9768->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dw9768_runtime_suspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct of_device_id dw9768_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { .compatible = "dongwoon,dw9768" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { .compatible = "giantec,gt9769" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_DEVICE_TABLE(of, dw9768_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct dev_pm_ops dw9768_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SET_RUNTIME_PM_OPS(dw9768_runtime_suspend, dw9768_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct i2c_driver dw9768_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = DW9768_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .pm = &dw9768_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .of_match_table = dw9768_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .probe_new = dw9768_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .remove = dw9768_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) module_i2c_driver(dw9768_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_DESCRIPTION("DW9768 VCM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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