^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* cx25840 audio functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <media/drv-intf/cx25840.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "cx25840-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Note: The PLL and SRC parameters are based on a reference frequency that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * would ideally be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * However, it's not the exact reference frequency that matters, only that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * firmware and modules that comprise the driver for a particular board all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * use the same value (close to the ideal value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Comments below will note which reference frequency is assumed for various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * parameters. They will usually be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ref_freq = 28.636360 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ref_freq = 28.636363 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct cx25840_state *state = to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (state->aud_input != CX25840_AUDIO_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) cx25840_write4(client, 0x108, 0x1006040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * VID_PLL Fraction (register 0x10c) = 0x2be2fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 28636360 * 0xf.15f17f0/4 = 108 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 432 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * AUX_PLL Fraction = 0x1bb39ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 196.6 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * FIXME < 200 MHz is out of specified valid range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * FIXME 28636363 ref_freq doesn't match VID PLL ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cx25840_write4(client, 0x110, 0x01bb39ee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * SA_MCLK_SEL = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cx25840_write(client, 0x127, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cx25840_write4(client, 0x900, 0x0801f77f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cx25840_write4(client, 0x904, 0x0801f77f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cx25840_write4(client, 0x90c, 0x0801f77f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cx25840_write4(client, 0x108, 0x1009040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * VID_PLL Fraction (register 0x10c) = 0x2be2fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 28636360 * 0xf.15f17f0/4 = 108 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 432 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * AUX_PLL Fraction = 0x0ec6bd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * 28636363 * 0x9.7635eb0/0x10 = 44100 * 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 271 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * FIXME 28636363 ref_freq doesn't match VID PLL ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cx25840_write4(client, 0x110, 0x00ec6bd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * SA_MCLK_SEL = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cx25840_write(client, 0x127, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cx25840_write4(client, 0x900, 0x08016d59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cx25840_write4(client, 0x904, 0x08016d59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cx25840_write4(client, 0x90c, 0x08016d59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cx25840_write4(client, 0x108, 0x100a040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * VID_PLL Fraction (register 0x10c) = 0x2be2fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * 28636360 * 0xf.15f17f0/4 = 108 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 432 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * AUX_PLL Fraction = 0x098d6e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * 28636363 * 0xa.4c6b728/0x10 = 48000 * 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 295 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * FIXME 28636363 ref_freq doesn't match VID PLL ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cx25840_write4(client, 0x110, 0x0098d6e5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * SA_MCLK_SEL = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cx25840_write(client, 0x127, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cx25840_write4(client, 0x900, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cx25840_write4(client, 0x904, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cx25840_write4(client, 0x90c, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * AUX_PLL Integer = 0x08, AUX PLL Post Divider = 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cx25840_write4(client, 0x108, 0x1e08040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * VID_PLL Fraction (register 0x10c) = 0x2be2fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * 28636360 * 0xf.15f17f0/4 = 108 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 432 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * AUX_PLL Fraction = 0x12a0869
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * 28636363 * 0x8.9504348/0x1e = 32000 * 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * 246 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * FIXME 28636363 ref_freq doesn't match VID PLL ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cx25840_write4(client, 0x110, 0x012a0869);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * SA_MCLK_SEL = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * SA_MCLK_DIV = 0x14 = 256/384 * AUX_PLL post dvivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cx25840_write(client, 0x127, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* 0x1.0000 = 32000/32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cx25840_write4(client, 0x8f8, 0x08010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* 0x2.0000 = 2 * (32000/32000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cx25840_write4(client, 0x900, 0x08020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cx25840_write4(client, 0x904, 0x08020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) cx25840_write4(client, 0x90c, 0x08020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cx25840_write4(client, 0x108, 0x1809040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * VID_PLL Fraction (register 0x10c) = 0x2be2fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 28636360 * 0xf.15f17f0/4 = 108 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 432 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * AUX_PLL Fraction = 0x0ec6bd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 28636363 * 0x9.7635eb0/0x18 = 44100 * 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 271 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * FIXME 28636363 ref_freq doesn't match VID PLL ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cx25840_write4(client, 0x110, 0x00ec6bd6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * SA_MCLK_SEL = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cx25840_write(client, 0x127, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 0x1.60cd = 44100/32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) cx25840_write4(client, 0x8f8, 0x080160cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 0x1.7385 = 2 * (32000/44100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cx25840_write4(client, 0x900, 0x08017385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cx25840_write4(client, 0x904, 0x08017385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cx25840_write4(client, 0x90c, 0x08017385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cx25840_write4(client, 0x108, 0x180a040f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * VID_PLL Fraction (register 0x10c) = 0x2be2fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * 28636360 * 0xf.15f17f0/4 = 108 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * 432 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * AUX_PLL Fraction = 0x098d6e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * 28636363 * 0xa.4c6b728/0x18 = 48000 * 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * 295 MHz pre-postdivide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * FIXME 28636363 ref_freq doesn't match VID PLL ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) cx25840_write4(client, 0x110, 0x0098d6e5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * SA_MCLK_SEL = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cx25840_write(client, 0x127, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* 0x1.8000 = 48000/32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cx25840_write4(client, 0x8f8, 0x08018000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* 0x1.5555 = 2 * (32000/48000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cx25840_write4(client, 0x900, 0x08015555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cx25840_write4(client, 0x904, 0x08015555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cx25840_write4(client, 0x90c, 0x08015555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) state->audclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static inline int cx25836_set_audclk_freq(struct i2c_client *client, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return cx25840_set_audclk_freq(client, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int cx23885_set_audclk_freq(struct i2c_client *client, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct cx25840_state *state = to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (state->aud_input != CX25840_AUDIO_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* We don't have register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * so avoid destroying registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* FIXME return -EINVAL; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* We don't have register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * so avoid destroying registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* FIXME return -EINVAL; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) cx25840_write4(client, 0x8f8, 0x0801867c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) cx25840_write4(client, 0x900, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cx25840_write4(client, 0x904, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cx25840_write4(client, 0x90c, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) state->audclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int cx231xx_set_audclk_freq(struct i2c_client *client, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct cx25840_state *state = to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (state->aud_input != CX25840_AUDIO_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cx25840_write4(client, 0x900, 0x0801f77f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cx25840_write4(client, 0x904, 0x0801f77f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cx25840_write4(client, 0x90c, 0x0801f77f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cx25840_write4(client, 0x900, 0x08016d59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cx25840_write4(client, 0x904, 0x08016d59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cx25840_write4(client, 0x90c, 0x08016d59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cx25840_write4(client, 0x900, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cx25840_write4(client, 0x904, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cx25840_write4(client, 0x90c, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* FIXME These cases make different assumptions about audclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* 0x1.0000 = 32000/32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cx25840_write4(client, 0x8f8, 0x08010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* 0x2.0000 = 2 * (32000/32000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cx25840_write4(client, 0x900, 0x08020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cx25840_write4(client, 0x904, 0x08020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cx25840_write4(client, 0x90c, 0x08020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* 0x1.60cd = 44100/32000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cx25840_write4(client, 0x8f8, 0x080160cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* 0x1.7385 = 2 * (32000/44100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cx25840_write4(client, 0x900, 0x08017385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cx25840_write4(client, 0x904, 0x08017385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cx25840_write4(client, 0x90c, 0x08017385);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* src1_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cx25840_write4(client, 0x8f8, 0x0801867c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* src3/4/6_ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cx25840_write4(client, 0x900, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) cx25840_write4(client, 0x904, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cx25840_write4(client, 0x90c, 0x08014faa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) state->audclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int set_audclk_freq(struct i2c_client *client, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct cx25840_state *state = to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (freq != 32000 && freq != 44100 && freq != 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (is_cx231xx(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return cx231xx_set_audclk_freq(client, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (is_cx2388x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return cx23885_set_audclk_freq(client, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return cx25836_set_audclk_freq(client, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return cx25840_set_audclk_freq(client, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) void cx25840_audio_set_path(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct cx25840_state *state = to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!is_cx2583x(state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* assert soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cx25840_and_or(client, 0x810, ~0x1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* stop microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) cx25840_and_or(client, 0x803, ~0x10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Mute everything to prevent the PFFT! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cx25840_write(client, 0x8d3, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (state->aud_input == CX25840_AUDIO_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Set Path1 to Serial Audio Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cx25840_write4(client, 0x8d0, 0x01011012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* The microcontroller should not be started for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * non-tuner inputs: autodetection is specific for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * TV audio. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Set Path1 to Analog Demod Main Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cx25840_write4(client, 0x8d0, 0x1f063870);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) set_audclk_freq(client, state->audclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!is_cx2583x(state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (state->aud_input != CX25840_AUDIO_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* When the microcontroller detects the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * audio format, it will unmute the lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cx25840_and_or(client, 0x803, ~0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* deassert soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cx25840_and_or(client, 0x810, ~0x1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Ensure the controller is running when we exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (is_cx2388x(state) || is_cx231xx(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cx25840_and_or(client, 0x803, ~0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void set_volume(struct i2c_client *client, int volume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Convert the volume to msp3400 values (0-127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) vol = volume >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* now scale it up to cx25840 values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * -114dB to -96dB maps to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * this should be 19, but in my testing that was 4dB too loud */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (vol <= 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) vol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) vol -= 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* PATH1_VOLUME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cx25840_write(client, 0x8d4, 228 - (vol * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void set_balance(struct i2c_client *client, int balance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int bal = balance >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (bal > 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* PATH1_BAL_LEFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cx25840_and_or(client, 0x8d5, 0x7f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* PATH1_BAL_LEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cx25840_and_or(client, 0x8d5, ~0x7f, bal & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* PATH1_BAL_LEFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cx25840_and_or(client, 0x8d5, 0x7f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* PATH1_BAL_LEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cx25840_and_or(client, 0x8d5, ~0x7f, 0x80 - bal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int cx25840_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct cx25840_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cx25840_and_or(client, 0x810, ~0x1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (state->aud_input != CX25840_AUDIO_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cx25840_and_or(client, 0x803, ~0x10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cx25840_write(client, 0x8d3, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) retval = set_audclk_freq(client, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (state->aud_input != CX25840_AUDIO_SERIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cx25840_and_or(client, 0x803, ~0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!is_cx2583x(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) cx25840_and_or(client, 0x810, ~0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int cx25840_audio_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct cx25840_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case V4L2_CID_AUDIO_VOLUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (state->mute->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) set_volume(client, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) set_volume(client, state->volume->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case V4L2_CID_AUDIO_BASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* PATH1_EQ_BASS_VOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cx25840_and_or(client, 0x8d9, ~0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 48 - (ctrl->val * 48 / 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case V4L2_CID_AUDIO_TREBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* PATH1_EQ_TREBLE_VOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cx25840_and_or(client, 0x8db, ~0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 48 - (ctrl->val * 48 / 0xffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case V4L2_CID_AUDIO_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) set_balance(client, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) const struct v4l2_ctrl_ops cx25840_audio_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .s_ctrl = cx25840_audio_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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