^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cs53l32a (Adaptec AVC-2010 and AVC-2410) i2c ivtv driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 Martin Vaughan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Audio source switching for Adaptec AVC-2410 added by Trev Jackson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MODULE_DESCRIPTION("i2c device driver for cs53l32a Audio ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_AUTHOR("Martin Vaughan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static bool debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) module_param(debug, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(debug, "Debugging messages, 0=Off (default), 1=On");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct cs53l32a_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline struct cs53l32a_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return container_of(sd, struct cs53l32a_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return &container_of(ctrl->handler, struct cs53l32a_state, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int cs53l32a_write(struct v4l2_subdev *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int cs53l32a_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int cs53l32a_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* There are 2 physical inputs, but the second input can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) placed in two modes, the first mode bypasses the PGA (gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) the second goes through the PGA. Hence there are three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) possible inputs to choose from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (input > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) v4l2_err(sd, "Invalid input %d.\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cs53l32a_write(sd, 0x01, 0x01 + (input << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int cs53l32a_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case V4L2_CID_AUDIO_MUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) cs53l32a_write(sd, 0x03, ctrl->val ? 0xf0 : 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case V4L2_CID_AUDIO_VOLUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cs53l32a_write(sd, 0x04, (u8)ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cs53l32a_write(sd, 0x05, (u8)ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int cs53l32a_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct cs53l32a_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 v = cs53l32a_read(sd, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) v4l2_info(sd, "Input: %d\n", (v >> 4) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct v4l2_ctrl_ops cs53l32a_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .s_ctrl = cs53l32a_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct v4l2_subdev_core_ops cs53l32a_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .log_status = cs53l32a_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct v4l2_subdev_audio_ops cs53l32a_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .s_routing = cs53l32a_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct v4l2_subdev_ops cs53l32a_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .core = &cs53l32a_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .audio = &cs53l32a_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* i2c implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Generic i2c probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * concerning the addresses: i2c wants 7 bit (without the r/w bit), so '>>1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int cs53l32a_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct cs53l32a_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) strscpy(client->name, "cs53l32a", sizeof(client->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) v4l2_i2c_subdev_init(sd, client, &cs53l32a_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 1; i <= 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 v = cs53l32a_read(sd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) v4l2_dbg(1, debug, sd, "Read Reg %d %02x\n", i, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) v4l2_ctrl_handler_init(&state->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) v4l2_ctrl_new_std(&state->hdl, &cs53l32a_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) V4L2_CID_AUDIO_VOLUME, -96, 12, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) v4l2_ctrl_new_std(&state->hdl, &cs53l32a_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sd->ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (state->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Set cs53l32a internal register for Adaptec 2010/2410 setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cs53l32a_write(sd, 0x01, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cs53l32a_write(sd, 0x02, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cs53l32a_write(sd, 0x03, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cs53l32a_write(sd, 0x04, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cs53l32a_write(sd, 0x05, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cs53l32a_write(sd, 0x06, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cs53l32a_write(sd, 0x07, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Display results, should be 0x21,0x29,0x30,0x00,0x00,0x00,0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 1; i <= 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 v = cs53l32a_read(sd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) v4l2_dbg(1, debug, sd, "Read Reg %d %02x\n", i, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int cs53l32a_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct cs53l32a_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct i2c_device_id cs53l32a_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { "cs53l32a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_DEVICE_TABLE(i2c, cs53l32a_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct i2c_driver cs53l32a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "cs53l32a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .probe = cs53l32a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .remove = cs53l32a_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .id_table = cs53l32a_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) module_i2c_driver(cs53l32a_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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