^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bt819 - BT819A VideoStream Decoder (Rockwell Part)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 Mike Bernson <mike@mlb.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Modifications for LML33/DC10plus unified driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Changes by Ronald Bultje <rbultje@ronald.bitfreak.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This code was modify/ported from the saa7111 driver written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * by Dave Perks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/i2c/bt819.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_AUTHOR("Mike Bernson & Dave Perks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct bt819 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned char reg[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline struct bt819 *to_bt819(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return container_of(sd, struct bt819, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return &container_of(ctrl->handler, struct bt819, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int hdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int vdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int hscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int vscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* for values, see the bt819 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct timing timing_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {864 - 24, 20, 625 - 2, 1, 0x0504, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {858 - 24, 20, 525 - 2, 1, 0x00f8, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline int bt819_write(struct bt819 *decoder, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct i2c_client *client = v4l2_get_subdevdata(&decoder->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) decoder->reg[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline int bt819_setbit(struct bt819 *decoder, u8 reg, u8 bit, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return bt819_write(decoder, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (decoder->reg[reg] & ~(1 << bit)) | (value ? (1 << bit) : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int bt819_write_block(struct bt819 *decoder, const u8 *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct i2c_client *client = v4l2_get_subdevdata(&decoder->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* the bt819 has an autoincrement function, use it if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * the adapter understands raw I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* do raw I2C, not smbus compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 block_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) block_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) block_data[block_len++] = reg = data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) block_data[block_len++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) decoder->reg[reg++] = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } while (len >= 2 && data[0] == reg && block_len < 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = i2c_master_send(client, block_data, block_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* do some slow I2C emulation kind of thing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = bt819_write(decoder, reg, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline int bt819_read(struct bt819 *decoder, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct i2c_client *client = v4l2_get_subdevdata(&decoder->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int bt819_init(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static unsigned char init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*0x1f, 0x00,*/ /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x01, 0x59, /* 0x01 input format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x02, 0x00, /* 0x02 temporal decimation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x03, 0x12, /* 0x03 Cropping msb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x04, 0x16, /* 0x04 Vertical Delay, lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x05, 0xe0, /* 0x05 Vertical Active lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x06, 0x80, /* 0x06 Horizontal Delay lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x07, 0xd0, /* 0x07 Horizontal Active lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x08, 0x00, /* 0x08 Horizontal Scaling msb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x09, 0xf8, /* 0x09 Horizontal Scaling lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x0a, 0x00, /* 0x0a Brightness control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x0b, 0x30, /* 0x0b Miscellaneous control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x0c, 0xd8, /* 0x0c Luma Gain lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x0d, 0xfe, /* 0x0d Chroma Gain (U) lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x0e, 0xb4, /* 0x0e Chroma Gain (V) msb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x0f, 0x00, /* 0x0f Hue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x12, 0x04, /* 0x12 Output Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x13, 0x20, /* 0x13 Vertical Scaling msb 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) chroma comb OFF, line drop scaling, interlace scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BUG? Why does turning the chroma comb on screw up color?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) Bug in the bt819 stepping on my board?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x14, 0x00, /* 0x14 Vertical Scaling lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x16, 0x07, /* 0x16 Video Timing Polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ACTIVE=active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FIELD: high=odd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) vreset=active high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hreset=active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x18, 0x68, /* 0x18 AGC Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x19, 0x5d, /* 0x19 Burst Gate Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x1a, 0x80, /* 0x1a ADC Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) init[0x03 * 2 - 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (((timing->vdelay >> 8) & 0x03) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (((timing->vactive >> 8) & 0x03) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (((timing->hdelay >> 8) & 0x03) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ((timing->hactive >> 8) & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) init[0x04 * 2 - 1] = timing->vdelay & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) init[0x05 * 2 - 1] = timing->vactive & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) init[0x06 * 2 - 1] = timing->hdelay & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) init[0x07 * 2 - 1] = timing->hactive & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) init[0x08 * 2 - 1] = timing->hscale >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) init[0x09 * 2 - 1] = timing->hscale & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* 0x15 in array is address 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) init[0x15 * 2 - 1] = (decoder->norm & V4L2_STD_625_50) ? 115 : 93; /* Chroma burst delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bt819_write(decoder, 0x1f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return bt819_write_block(decoder, init, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int bt819_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int status = bt819_read(decoder, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int res = V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if ((status & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if ((status & 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) std &= V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) std &= V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (pstd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *pstd = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (pstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *pstatus = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) v4l2_dbg(1, debug, sd, "get status %x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int bt819_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return bt819_status(sd, NULL, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int bt819_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return bt819_status(sd, status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int bt819_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct timing *timing = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) v4l2_dbg(1, debug, sd, "set norm %llx\n", (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (sd->v4l2_dev == NULL || sd->v4l2_dev->notify == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) v4l2_err(sd, "no notify found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (std & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) v4l2_subdev_notify(sd, BT819_FIFO_RESET_LOW, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bt819_setbit(decoder, 0x01, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bt819_setbit(decoder, 0x01, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bt819_setbit(decoder, 0x01, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bt819_write(decoder, 0x18, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bt819_write(decoder, 0x19, 0x5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* bt819_setbit(decoder, 0x1a, 5, 1); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) timing = &timing_data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } else if (std & V4L2_STD_PAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) v4l2_subdev_notify(sd, BT819_FIFO_RESET_LOW, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bt819_setbit(decoder, 0x01, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bt819_setbit(decoder, 0x01, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bt819_setbit(decoder, 0x01, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bt819_write(decoder, 0x18, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bt819_write(decoder, 0x19, 0x72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* bt819_setbit(decoder, 0x1a, 5, 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) timing = &timing_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) v4l2_dbg(1, debug, sd, "unsupported norm %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bt819_write(decoder, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (((timing->vdelay >> 8) & 0x03) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (((timing->vactive >> 8) & 0x03) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (((timing->hdelay >> 8) & 0x03) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ((timing->hactive >> 8) & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) bt819_write(decoder, 0x04, timing->vdelay & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bt819_write(decoder, 0x05, timing->vactive & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bt819_write(decoder, 0x06, timing->hdelay & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bt819_write(decoder, 0x07, timing->hactive & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bt819_write(decoder, 0x08, (timing->hscale >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bt819_write(decoder, 0x09, timing->hscale & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) decoder->norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) v4l2_subdev_notify(sd, BT819_FIFO_RESET_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int bt819_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) v4l2_dbg(1, debug, sd, "set input %x\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (input > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (sd->v4l2_dev == NULL || sd->v4l2_dev->notify == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) v4l2_err(sd, "no notify found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (decoder->input != input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) v4l2_subdev_notify(sd, BT819_FIFO_RESET_LOW, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) decoder->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* select mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (decoder->input == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bt819_setbit(decoder, 0x0b, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bt819_setbit(decoder, 0x1a, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bt819_setbit(decoder, 0x0b, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bt819_setbit(decoder, 0x1a, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) v4l2_subdev_notify(sd, BT819_FIFO_RESET_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int bt819_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) v4l2_dbg(1, debug, sd, "enable output %x\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (decoder->enable != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) decoder->enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bt819_setbit(decoder, 0x16, 7, !enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int bt819_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bt819_write(decoder, 0x0a, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bt819_write(decoder, 0x0c, ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bt819_setbit(decoder, 0x0b, 2, ((ctrl->val >> 8) & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bt819_write(decoder, 0x0d, (ctrl->val >> 7) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bt819_setbit(decoder, 0x0b, 1, ((ctrl->val >> 15) & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Ratio between U gain and V gain must stay the same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) the ratio between the default U and V gain values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) temp = (ctrl->val * 180) / 254;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bt819_write(decoder, 0x0e, (temp >> 7) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bt819_setbit(decoder, 0x0b, 0, (temp >> 15) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bt819_write(decoder, 0x0f, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct v4l2_ctrl_ops bt819_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .s_ctrl = bt819_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct v4l2_subdev_video_ops bt819_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .s_std = bt819_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .s_routing = bt819_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .s_stream = bt819_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .querystd = bt819_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .g_input_status = bt819_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct v4l2_subdev_ops bt819_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .video = &bt819_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int bt819_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int i, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct bt819 *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (decoder == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sd = &decoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) v4l2_i2c_subdev_init(sd, client, &bt819_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ver = bt819_read(decoder, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (ver & 0xf0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 0x70:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) name = "bt819a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) name = "bt817a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) name = "bt815a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "unknown chip version 0x%02x\n", ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) v4l_info(client, "%s found @ 0x%x (%s)\n", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) decoder->norm = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) decoder->input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) decoder->enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) i = bt819_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) v4l2_dbg(1, debug, sd, "init status %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) v4l2_ctrl_handler_init(&decoder->hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) v4l2_ctrl_new_std(&decoder->hdl, &bt819_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) v4l2_ctrl_new_std(&decoder->hdl, &bt819_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) V4L2_CID_CONTRAST, 0, 511, 1, 0xd8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) v4l2_ctrl_new_std(&decoder->hdl, &bt819_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) V4L2_CID_SATURATION, 0, 511, 1, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) v4l2_ctrl_new_std(&decoder->hdl, &bt819_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) V4L2_CID_HUE, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sd->ctrl_handler = &decoder->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (decoder->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int err = decoder->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) v4l2_ctrl_handler_free(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) v4l2_ctrl_handler_setup(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int bt819_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct bt819 *decoder = to_bt819(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) v4l2_ctrl_handler_free(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct i2c_device_id bt819_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { "bt819a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { "bt817a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { "bt815a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_DEVICE_TABLE(i2c, bt819_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct i2c_driver bt819_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "bt819",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .probe = bt819_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .remove = bt819_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .id_table = bt819_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) module_i2c_driver(bt819_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags