^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BF3925 CMOS Image Sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X01 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X02 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/media.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRIVER_NAME "bf3925"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BF3925_PIXEL_RATE (120 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * BF3925 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_SOFTWARE_STANDBY 0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_SC_CHIP_ID_H 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_SC_CHIP_ID_L 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_NULL 0xFFFF /* Array end token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BF3925_ID 0x3925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct sensor_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct bf3925_framesize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 max_exp_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct sensor_register *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct bf3925_pll_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 ctrl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct bf3925_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Output format Register Value (REG_FORMAT_CTRL00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct sensor_register *format_ctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct pll_ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const bf3925_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BF3925_NUM_SUPPLIES ARRAY_SIZE(bf3925_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct bf3925 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int xvclk_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct gpio_desc *pwdn2_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct regulator_bulk_data supplies[BF3925_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_ctrl *link_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const struct bf3925_framesize *frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct sensor_register bf3925_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0x50, 0x00}, //bit[4]: digital subsample Data format selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0x51, 0x02}, //YUV Sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0xe0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0xe2, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0xe3, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0xe4, 0x83}, //Drive capability //0x81 ljx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0xe7, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) //clock, dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0xe9, 0x2a}, //08 PLL setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x02, 0x90}, //Dummy Pixel Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x03, 0x00}, ///02 //yang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x04, 0x00}, //Dummy line Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0xe5, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) //init black
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x3d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x30, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x31, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x32, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x33, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) //resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x05, 0xa2}, ///a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x09, 0x90}, ///00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x0a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x0b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x0d, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x5d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x5a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x5b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x5c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x53, 0x30}, ///60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x54, 0x20}, ///40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x55, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x56, 0x20}, ///40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x57, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x58, 0x58}, ///b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x50, 0x00}, //bit[4]: digital subsample Data format selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) //initial AWB and AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0xb2, 0x81}, //Manual AWB & AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0xb0, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0xb1, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0xb2, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x0e, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x0f, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x10, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x00, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) //black control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3c, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) //black sun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0xe1, 0xf8}, //28 bit[7:4]: Pixel bias current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x00, 0x47}, //bit[6]: black sun control bit[5:4]: mirror/flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x18, 0x0c}, //PRST indoor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x19, 0x1a}, //PRST outdoor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) //lens shading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x52, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x53, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x54, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x55, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x56, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x57, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x58, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x59, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x5a, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x5b, 0x44}, ///46 lens shading gain of R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x5c, 0x3C}, ///43 lens shading gain of G1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x5d, 0x40}, //lens shading gain of B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x5e, 0x3C}, /// 43lens shading gain of G0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*gamma default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x60, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x61, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x62, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x63, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x64, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x65, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x66, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x67, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x68, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x69, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x6a, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x6b, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x6c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x6d, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x6e, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x6f, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x70, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x71, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x72, 0x24},///10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x73, 0x24},///10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) //gamma hi-lit,nice over-ex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x60, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x61, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x62, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x63, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x64, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x65, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x66, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x67, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x68, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x69, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x6a, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x6b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x6c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x6d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x6e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) //gamma nice color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x60, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x61, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x62, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x63, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x64, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x65, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x66, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x67, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x68, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x69, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x6a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x6b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x6c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x6d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x6e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ///gamma low denoise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x60, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x61, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x62, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x63, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x64, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x65, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x66, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x67, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x68, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x69, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x6a, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x6b, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x6c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x6d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x6e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) //clearer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) //denoise and edge enhancement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x80, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x81, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x83, 0x37}, //0x83[7:4]: de_noise threshhole; 0x83[3:0]: de_noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x84, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x85, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x86, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x88, 0xa2}, //bit[7:6] 0 is low noise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x89, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x8a, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x8b, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x91, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x92, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x93, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) //denoise and edge enhancement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x80, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x81, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x83, 0x27}, //0x83[7:4]: de_noise threshhole; 0x83[3:0]: de_noise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x84, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x85, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x86, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x87, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x88, 0xa2}, //bit[7:6] 0 is low noise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x89, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x8b, 0x11}, //12 Bright/Dark edge enhancement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x91, 0x48}, //45 0x91:40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) //AWB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0xa2, 0x06}, //the low limit of blue gain for indoor scene
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0xa3, 0x28}, //the upper limit of blue gain for indoor scene
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0xa4, 0x0a}, //the low limit of red gain for indoor scene
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0xa5, 0x2c}, //the upper limit of red gain for indoor scene
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0xa7, 0x1b}, //Base B gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0xa8, 0x14}, //Base R gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0xa9, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0xaa, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0xab, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0xac, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0xae, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0xb2, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0xb3, 0x66}, // green gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0xb4, 0x03}, //the offset of F light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0xb5, 0x00}, //the offset of non-F light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0xb6, 0xd9}, //bit[7]: outdoor control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0xb8, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0xbb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0xbc, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0xbd, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0xbe, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0xbf, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) // color default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0xc0, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0xc1, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0xc2, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0xc3, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0xc4, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0xc5, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) //color Gorgeous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0xc0, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0xc1, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0xc2, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0xc3, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0xc4, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0xc5, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) //color light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0xc0, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0xc1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0xc2, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0xc3, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0xc4, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0xc5, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) // A color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0xc6, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0xc7, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0xc8, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0xc9, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0xca, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0xcb, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) //Outdoor color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0xd0, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0xd1, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0xd2, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0xd3, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0xd4, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0xd5, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0xcd, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0xd6, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) //AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x00, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x01, 0x8a}, // AE window and weight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x04, 0x48}, //4f AE Target//40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x05, 0x48}, //4f Y target value1//48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x07, 0x92}, //Bit[3:2]: the bigger, Y_AVER_MODIFY is smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x09, 0x8a}, //92 Bit[5:0]: INT_MAX//8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x0a, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x0b, 0x82}, //Bit[5:0]: INT_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0c, 0xb4}, //78 50hz banding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x0d, 0x96}, //64 60hz banding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x15, 0x02}, //AEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x16, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x17, 0xb5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x18, 0x50}, ///30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x1b, 0x30}, ///33 minimum global gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x1c, 0x58}, ///66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x1d, 0x38}, ///55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x1e, 0x58}, ///80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x1f, 0x60}, /// c0 maximum gain//a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) // saturation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x30, 0xff}, ///e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x31, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x32, 0x60}, ///f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x34, 0xd8}, ///da Cb Saturation Coefficient low 8 bit for NF light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x35, 0xc8}, ///ca Cr Saturation Coefficient low 8 bit for NF light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x36, 0xff}, //Cb Saturation Coefficient low 8 bit for F light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x37, 0xd0}, //Cr Saturation Coefficient low 8 bit for F light
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) //skin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) // auto contrast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3e, 0x02}, //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3e, 0x82}, //do not change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x38, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) //yang add start switch to 1600*1200 UXGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) //1600*1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) //window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) //yang add end switch to 1600*1200 UXGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Senor full resolution setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct sensor_register bf3925_full_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) //1600*1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) //window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x05, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x0a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x0b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x0d, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x0e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x5d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x5a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x5b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x5c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x53, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x54, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x55, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x56, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x57, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x58, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) //clock, dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x09, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0xe9, 0x2a}, //08 PLL setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x02, 0x00}, //Dummy Pixel Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x03, 0x00}, ///02 //yang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x04, 0x00}, //Dummy line Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Preview resolution setting*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct sensor_register bf3925_svga_regs_15fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) //800*600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) //window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x05, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x0a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x0b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x0d, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x0e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x52, 0x01}, //Bit[1]: VSYNC option Bit[0]: HSYNC option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x5d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x5a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x5b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x5c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x53, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x54, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x55, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x56, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x57, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x58, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) //clock, dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x09, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0xe9, 0x2a}, //08 PLL setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x02, 0x00}, //Dummy Pixel Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x03, 0x00}, ///02 //yang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x04, 0x00}, //Dummy line Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Preview resolution setting*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct sensor_register bf3925_svga_regs_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) //800*600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x09, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x0a, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x0b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x0c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x0d, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x0e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x52, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x5d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x5a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x5b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x5c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x09, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x53, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x54, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x55, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x56, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x57, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x58, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0xe9, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) //clock, dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0xff, 0x01}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x09, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* 08 PLL setting 0x09: 1 times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * 0x1b: multiply 5/4 0x2b: 3/2 multiply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * 0x08:double 0x1a: 5/2 multiply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * 0x2a: triple 0x2a ljx 2017-6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0xe9, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0xff, 0x00}, //Bit[0]: select reg page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x02, 0xea}, //Dummy Pixel Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x03, 0x00}, ///02 //yang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x04, 0x00}, //Dummy line Insert LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct bf3925_framesize bf3925_framesizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { /* SVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .width = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .height = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .regs = bf3925_svga_regs_15fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }, { /* SVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .width = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .height = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .regs = bf3925_svga_regs_30fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }, { /* FULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .width = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .height = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .regs = bf3925_full_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct bf3925_pixfmt bf3925_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static inline struct bf3925 *to_bf3925(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return container_of(sd, struct bf3925, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int bf3925_write(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "bf3925 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int bf3925_read(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "bf3925 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int bf3925_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) const struct sensor_register *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = bf3925_write(client, regs[i].addr, regs[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void bf3925_get_default_format(struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) format->width = bf3925_framesizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) format->height = bf3925_framesizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) format->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) format->code = bf3925_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void bf3925_set_streaming(struct bf3925 *bf3925, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct i2c_client *client = bf3925->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = bf3925_write(client, REG_SOFTWARE_STANDBY, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(&client->dev, "bf3925 soft standby failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * V4L2 subdev video and pad level operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int bf3925_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (code->index >= ARRAY_SIZE(bf3925_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) code->code = bf3925_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int bf3925_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int i = ARRAY_SIZE(bf3925_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (fse->index >= ARRAY_SIZE(bf3925_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (fse->code == bf3925_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) fse->code = bf3925_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) fse->min_width = bf3925_framesizes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fse->max_width = fse->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) fse->max_height = bf3925_framesizes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fse->min_height = fse->max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int bf3925_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mutex_lock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fmt->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_lock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fmt->format = bf3925->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) bf3925->format.code, bf3925->format.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) bf3925->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void __bf3925_try_frame_size_fps(struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) const struct bf3925_framesize **size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned int fps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) const struct bf3925_framesize *fsize = &bf3925_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) const struct bf3925_framesize *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) unsigned int i = ARRAY_SIZE(bf3925_framesizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned int min_err = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned int err = abs(fsize->width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) + abs(fsize->height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (err < min_err && fsize->regs[0].addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) match = &bf3925_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fsize = &bf3925_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) for (i = 0; i < ARRAY_SIZE(bf3925_framesizes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (fsize->width == match->width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) fsize->height == match->height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) fps >= DIV_ROUND_CLOSEST(fsize->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) fsize->max_fps.numerator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mf->width = match->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mf->height = match->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *size = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int bf3925_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int index = ARRAY_SIZE(bf3925_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct v4l2_mbus_framefmt *mf = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) const struct bf3925_framesize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev_dbg(&client->dev, "%s enter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __bf3925_try_frame_size_fps(mf, &size, bf3925->fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) while (--index >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (bf3925_formats[index].code == mf->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mf->code = bf3925_formats[index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mutex_lock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) *mf = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (bf3925->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) bf3925->frame_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) bf3925->format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int bf3925_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_info(&client->dev, "%s: on: %d, %dx%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) bf3925->frame_size->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) bf3925->frame_size->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mutex_lock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (bf3925->streaming == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Stop Streaming Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) bf3925_set_streaming(bf3925, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) bf3925->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = bf3925_write_array(client, bf3925->frame_size->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) bf3925_set_streaming(bf3925, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) bf3925->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int bf3925_set_test_pattern(struct bf3925 *bf3925, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int bf3925_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct bf3925 *bf3925 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) container_of(ctrl->handler, struct bf3925, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return bf3925_set_test_pattern(bf3925, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const struct v4l2_ctrl_ops bf3925_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .s_ctrl = bf3925_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const char * const bf3925_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "Vertical Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * V4L2 subdev internal operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int bf3925_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct v4l2_mbus_framefmt *format =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) bf3925_get_default_format(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int bf3925_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) config->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) V4L2_MBUS_VSYNC_ACTIVE_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) V4L2_MBUS_PCLK_SAMPLE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int bf3925_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mutex_lock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) fi->interval = bf3925->frame_size->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int bf3925_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) const struct bf3925_framesize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct v4l2_mbus_framefmt mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_dbg(&client->dev, "Setting %d/%d frame interval\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) fi->interval.numerator, fi->interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mutex_lock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (bf3925->format.width == 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fi->interval.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) mf = bf3925->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) __bf3925_try_frame_size_fps(&mf, &size, fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (bf3925->frame_size != size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_info(&client->dev, "%s match wxh@FPS is %dx%d@%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) __func__, size->width, size->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) DIV_ROUND_CLOSEST(size->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) size->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret = bf3925_write_array(client, size->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bf3925->frame_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bf3925->fps = fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) mutex_unlock(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static void bf3925_get_module_inf(struct bf3925 *bf3925,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) strlcpy(inf->base.sensor, DRIVER_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) strlcpy(inf->base.module, bf3925->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) strlcpy(inf->base.lens, bf3925->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static long bf3925_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) bf3925_get_module_inf(bf3925, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bf3925_set_streaming(bf3925, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) bf3925_set_streaming(bf3925, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static long bf3925_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = bf3925_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = bf3925_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = bf3925_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int bf3925_init(struct v4l2_subdev *sd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct i2c_client *client = bf3925->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_info(&client->dev, "%s(%d)\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = bf3925_write(client, 0xf2, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = bf3925_write_array(client, bf3925_init_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int bf3925_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct i2c_client *client = bf3925->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct device *dev = &bf3925->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!IS_ERR(bf3925->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) gpiod_set_value_cansleep(bf3925->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ret = bf3925_init(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev_err(dev, "init error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (!IS_ERR(bf3925->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int bf3925_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (fie->index >= ARRAY_SIZE(bf3925_framesizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) fie->width = bf3925_framesizes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) fie->height = bf3925_framesizes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) fie->interval = bf3925_framesizes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const struct v4l2_subdev_core_ops bf3925_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .ioctl = bf3925_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .compat_ioctl32 = bf3925_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .s_power = bf3925_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct v4l2_subdev_video_ops bf3925_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .s_stream = bf3925_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .g_mbus_config = bf3925_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .g_frame_interval = bf3925_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .s_frame_interval = bf3925_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static const struct v4l2_subdev_pad_ops bf3925_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .enum_mbus_code = bf3925_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .enum_frame_size = bf3925_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .enum_frame_interval = bf3925_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .get_fmt = bf3925_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .set_fmt = bf3925_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const struct v4l2_subdev_ops bf3925_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .core = &bf3925_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .video = &bf3925_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .pad = &bf3925_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static const struct v4l2_subdev_internal_ops bf3925_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .open = bf3925_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static int bf3925_detect(struct bf3925 *bf3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct i2c_client *client = bf3925->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u8 pid, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* Check sensor revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = bf3925_read(client, REG_SC_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = bf3925_read(client, REG_SC_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned short id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (id != BF3925_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) "Sensor detection failed (%04X, %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dev_info(&client->dev, "Found BF%04X sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!IS_ERR(bf3925->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static int __bf3925_power_on(struct bf3925 *bf3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct device *dev = &bf3925->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_info(dev, "power on!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!IS_ERR(bf3925->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = clk_set_rate(bf3925->xvclk, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_info(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (!IS_ERR(bf3925->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = clk_prepare_enable(bf3925->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_info(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) usleep_range(7000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!IS_ERR(bf3925->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (!IS_ERR(bf3925->supplies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = regulator_bulk_enable(BF3925_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) bf3925->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_info(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) usleep_range(20000, 50000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (!IS_ERR(bf3925->pwdn2_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) gpiod_set_value_cansleep(bf3925->pwdn2_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!IS_ERR(bf3925->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) gpiod_set_value_cansleep(bf3925->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static void __bf3925_power_off(struct bf3925 *bf3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!IS_ERR(bf3925->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) clk_disable_unprepare(bf3925->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (!IS_ERR(bf3925->supplies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) regulator_bulk_disable(BF3925_NUM_SUPPLIES, bf3925->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (!IS_ERR(bf3925->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) gpiod_set_value_cansleep(bf3925->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int bf3925_configure_regulators(struct bf3925 *bf3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) for (i = 0; i < BF3925_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) bf3925->supplies[i].supply = bf3925_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return devm_regulator_bulk_get(&bf3925->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) BF3925_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) bf3925->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int bf3925_parse_of(struct bf3925 *bf3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct device *dev = &bf3925->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) unsigned int pwdn = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) enum of_gpio_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) bf3925->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (IS_ERR(bf3925->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_info(dev, "Failed to get pwdn-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pwdn = of_get_named_gpio_flags(node, "pwdn-gpios", 0, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) pwdn_gpio = gpio_to_desc(pwdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (IS_ERR(pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dev_info(dev, "Failed to get pwdn-gpios again\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) bf3925->pwdn_gpio = pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) bf3925->pwdn2_gpio = devm_gpiod_get(dev, "pwdn2", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (IS_ERR(bf3925->pwdn2_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_info(dev, "Failed to get pwdn2-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pwdn = of_get_named_gpio_flags(node, "pwdn2-gpios", 0, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pwdn_gpio = gpio_to_desc(pwdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (IS_ERR(pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dev_info(dev, "Failed to get pwdn2-gpios again\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) bf3925->pwdn2_gpio = pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = bf3925_configure_regulators(bf3925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_info(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return __bf3925_power_on(bf3925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static int bf3925_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct bf3925 *bf3925;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) char facing[2] = "b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) bf3925 = devm_kzalloc(&client->dev, sizeof(*bf3925), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (!bf3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &bf3925->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) &bf3925->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) &bf3925->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) &bf3925->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(&client->dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) bf3925->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) bf3925->xvclk = devm_clk_get(&client->dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (IS_ERR(bf3925->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) dev_err(&client->dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) bf3925_parse_of(bf3925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bf3925->xvclk_frequency = clk_get_rate(bf3925->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (bf3925->xvclk_frequency < 6000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) bf3925->xvclk_frequency > 27000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) v4l2_ctrl_handler_init(&bf3925->ctrls, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) bf3925->link_frequency =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) v4l2_ctrl_new_std(&bf3925->ctrls, &bf3925_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) BF3925_PIXEL_RATE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) BF3925_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) v4l2_ctrl_new_std_menu_items(&bf3925->ctrls, &bf3925_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ARRAY_SIZE(bf3925_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) 0, 0, bf3925_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) bf3925->sd.ctrl_handler = &bf3925->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (bf3925->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_err(&client->dev, "%s: control initialization error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) __func__, bf3925->ctrls.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return bf3925->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) sd = &bf3925->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) client->flags |= I2C_CLIENT_SCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) v4l2_i2c_subdev_init(sd, client, &bf3925_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) sd->internal_ops = &bf3925_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) bf3925->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = media_entity_pads_init(&sd->entity, 1, &bf3925->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) v4l2_ctrl_handler_free(&bf3925->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) mutex_init(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) bf3925_get_default_format(&bf3925->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) bf3925->frame_size = &bf3925_framesizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) bf3925->format.width = bf3925_framesizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) bf3925->format.height = bf3925_framesizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) bf3925->fps = DIV_ROUND_CLOSEST(bf3925_framesizes[0].max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) bf3925_framesizes[0].max_fps.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = bf3925_detect(bf3925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (strcmp(bf3925->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) bf3925->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) DRIVER_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = v4l2_async_register_subdev_sensor_common(&bf3925->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) v4l2_ctrl_handler_free(&bf3925->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) mutex_destroy(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) __bf3925_power_off(bf3925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static int bf3925_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct bf3925 *bf3925 = to_bf3925(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) v4l2_ctrl_handler_free(&bf3925->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) mutex_destroy(&bf3925->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) __bf3925_power_off(bf3925);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static const struct i2c_device_id bf3925_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) { "bf3925", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) MODULE_DEVICE_TABLE(i2c, bf3925_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static const struct of_device_id bf3925_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) { .compatible = "byd,bf3925", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) MODULE_DEVICE_TABLE(of, bf3925_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static struct i2c_driver bf3925_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .of_match_table = of_match_ptr(bf3925_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .probe = bf3925_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .remove = bf3925_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .id_table = bf3925_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return i2c_add_driver(&bf3925_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) i2c_del_driver(&bf3925_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) MODULE_DESCRIPTION("BF3925 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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