^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ar0230 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X01 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X02 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* 74.25Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AR0230_PIXEL_RATE (74250000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AR0230_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CHIP_ID 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AR0230_REG_CHIP_ID 0x31fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AR0230_REG_CTRL_MODE 0x301A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AR0230_MODE_SW_STANDBY 0x10D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AR0230_MODE_STREAMING 0x10DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AR0230_REG_EXPOSURE 0x3012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AR0230_EXPOSURE_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AR0230_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AR0230_VTS_MAX 0x044A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AR0230_REG_ANALOG_GAIN 0x3060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ANALOG_GAIN_MIN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ANALOG_GAIN_MAX 0xFB7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ANALOG_GAIN_DEFAULT 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AR0230_REG_VTS 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AR0230_REG_ORIENTATION 0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AR0230_ORIENTATION_H bit(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AR0230_ORIENTATION_V bit(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AR0230_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AR0230_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AR0230_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USE_HDR_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* h_offs 35 v_offs 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PIX_FORMAT MEDIA_BUS_FMT_SGRBG12_1X12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AR0230_NAME "ar0230"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct cam_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct cam_regulator ar0230_regulator[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {"avdd", 2800000}, /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {"dovdd", 1800000}, /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {"dvdd", 1800000}, /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AR0230_NUM_SUPPLIES ARRAY_SIZE(ar0230_regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ar0230_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct ar0230 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regulator_bulk_data supplies[AR0230_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct ar0230_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define to_ar0230(sd) container_of(sd, struct ar0230, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Pclk 74.25Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * linelength 0x469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * framelength 0x44a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * grabwindow_width 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * grabwindow_height 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * dvp bt601 12bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct regval ar0230_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifdef USE_HDR_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x301A, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {REG_DELAY, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x301A, 0x10D8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {REG_DELAY, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x3088, 0x8000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x3086, 0x729B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x3086, 0x4A31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x3086, 0x4342},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x3086, 0x8E03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x3086, 0x2A14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x3086, 0x4578},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x3086, 0x7B3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x3086, 0xFF3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x3086, 0xFF3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x3086, 0xEA2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3086, 0x043D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3086, 0x102A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3086, 0x052A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3086, 0x1535},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3086, 0x2A05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3086, 0x3D10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3086, 0x2A04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3086, 0x2A14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3086, 0x3DFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3086, 0x3DFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3086, 0x3DEA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3086, 0x2A04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3086, 0x622A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3086, 0x288E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3086, 0x0036},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3086, 0x2A08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3086, 0x3D64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3086, 0x7A3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3086, 0x0444},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3086, 0x2C4B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3086, 0x8F00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3086, 0x430C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3086, 0x2D63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3086, 0x8E03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3086, 0x2AFC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3086, 0x5C1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3086, 0x5754},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3086, 0x495F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3086, 0x5305},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3086, 0x5307},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3086, 0x4D2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3086, 0xF810},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3086, 0x164C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3086, 0x0855},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3086, 0x562B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3086, 0xB82B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3086, 0x984E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3086, 0x1129},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3086, 0x0429},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3086, 0x8429},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3086, 0x9460},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3086, 0x5C19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3086, 0x5C1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3086, 0x4548},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3086, 0x4508},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3086, 0x4588},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3086, 0x29B6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3086, 0x8E01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3086, 0x2AF8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3086, 0x3E02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3086, 0x3F09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3086, 0x5C1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3086, 0x29B2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3086, 0x3F0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3086, 0x3E02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3086, 0x3E13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3086, 0x5C13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3086, 0x3F11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3086, 0x3E0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3086, 0x5F2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3086, 0x902A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3086, 0xF22B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3086, 0x803E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3086, 0x043F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3086, 0x0660},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3086, 0x29A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3086, 0x29A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3086, 0x5F4D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3086, 0x192A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3086, 0xFA29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3086, 0x8345},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3086, 0xA83E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3086, 0x072A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3086, 0xFB3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3086, 0x2945},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3086, 0x8821},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3086, 0x3E08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3086, 0x5D29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3086, 0x9288},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3086, 0x102B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3086, 0x048B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3086, 0x1685},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3086, 0x8D48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3086, 0x4D4E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3086, 0x2B80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3086, 0x4C0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3086, 0x603F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3086, 0x282A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3086, 0xF23F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3086, 0x0F29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3086, 0x8229},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3086, 0x8329},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3086, 0x435C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3086, 0x155F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3086, 0x4D19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3086, 0x8E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3086, 0x2A98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3086, 0x3F06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3086, 0x1244},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3086, 0x4A04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3086, 0x0543},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3086, 0x1658},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3086, 0x5A43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3086, 0x1606},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3086, 0x0743},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3086, 0x168E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3086, 0x032A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3086, 0x9C45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3086, 0x787B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3086, 0x3F07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3086, 0x2A9D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3086, 0x3E2E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3086, 0x253E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3086, 0x068E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3086, 0x012A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3086, 0x988E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3086, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3086, 0x444B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3086, 0x0343},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3086, 0x2D46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3086, 0xA343},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3086, 0x165D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3086, 0x0D29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3086, 0x4488},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3086, 0x102B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3086, 0x0453},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3086, 0x0D8B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3086, 0x1685},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3086, 0x448E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3086, 0x032A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3086, 0xFC5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3086, 0x1D8D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3086, 0x6057},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3086, 0x5449},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3086, 0x5F53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3086, 0x0553},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3086, 0x074D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3086, 0x2BF8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3086, 0x1016},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3086, 0x4C08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3086, 0x5556},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3086, 0x2BB8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3086, 0x2B98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3086, 0x4E11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3086, 0x2904},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3086, 0x2984},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3086, 0x2994},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3086, 0x605C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3086, 0x195C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3086, 0x1B45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3086, 0x4845},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3086, 0x0845},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3086, 0x8829},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3086, 0xB68E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3086, 0x012A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3086, 0xF83E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3086, 0x022A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3086, 0xFA3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3086, 0x095C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3086, 0x1B29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3086, 0xB23F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3086, 0x0C3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3086, 0x023E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3086, 0x135C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3086, 0x133F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3086, 0x113E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3086, 0x0B5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3086, 0x2B90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3086, 0x2AF2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3086, 0x2B80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3086, 0x3E04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3086, 0x3F06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3086, 0x6029},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3086, 0xA229},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3086, 0xA35F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3086, 0x4D1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3086, 0x2983},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3086, 0x45A8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3086, 0x3E07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3086, 0x2AFB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3086, 0x3E29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3086, 0x4588},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3086, 0x243E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3086, 0x082A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3086, 0xFA5D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3086, 0x2992},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3086, 0x8810},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3086, 0x2B04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3086, 0x8B16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3086, 0x868D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3086, 0x484D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3086, 0x4E2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3086, 0x804C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3086, 0x0B60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3086, 0x3F28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3086, 0x2AF2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3086, 0x3F0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3086, 0x2982},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3086, 0x2983},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3086, 0x2943},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3086, 0x5C15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3086, 0x5F4D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3086, 0x1C2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3086, 0xFA45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3086, 0x588E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3086, 0x002A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3086, 0x983F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3086, 0x064A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3086, 0x739D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3086, 0x0A43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3086, 0x160B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3086, 0x8E03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3086, 0x2A9C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3086, 0x4578},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3086, 0x3F07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3086, 0x2A9D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3086, 0x3E12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3086, 0x3F04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3086, 0x8E01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3086, 0x2A98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3086, 0x8E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3086, 0x9176},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x3086, 0x9C77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3086, 0x9C46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3086, 0x4416},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3086, 0x1690},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3086, 0x7A12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3086, 0x444B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3086, 0x4A00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3086, 0x6343},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3086, 0x1608},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3086, 0x5043},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3086, 0x1665},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3086, 0x6643},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3086, 0x168E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3086, 0x032A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3086, 0x9C45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3086, 0x783F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3086, 0x072A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3086, 0x9D5D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3086, 0x0C29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3086, 0x4488},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3086, 0x102B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3086, 0x0453},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3086, 0x0D8B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3086, 0x1686},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3086, 0x3E1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3086, 0x283E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3086, 0x068E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3086, 0x012A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3086, 0x988E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3086, 0x008D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3086, 0x6012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3086, 0x444B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3086, 0x2C2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3086, 0x2C2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x2436, 0x000E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x320C, 0x0180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x320E, 0x0300},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3210, 0x0500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3204, 0x0B6D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x30FE, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3ED8, 0x7B99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3EDC, 0x9BA8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3EDA, 0x9B9B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3092, 0x006F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3EEC, 0x1C04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x30BA, 0x779C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3EF6, 0xA70F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3044, 0x0410},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3ED0, 0xFF44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3ED4, 0x031F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x30FE, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3EE2, 0x8866},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3EE4, 0x6623},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3EE6, 0x2263},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x30E0, 0x4283},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x30F0, 0x1283},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x30B0, 0x0118},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x31AC, 0x100C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3040, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x31AE, 0x0301},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3082, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x31E0, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x2420, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x2440, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x2442, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x301E, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x2450, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x320A, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x31D0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x2400, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x2410, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x2412, 0x002D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x2444, 0xF400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x2446, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x2438, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x243A, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x243C, 0xFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x243E, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3206, 0x0B08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3208, 0x1E13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3202, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3200, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3190, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x318A, 0x0E74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x318C, 0xC000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3192, 0x0400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3198, 0x183C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3060, 0x000B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3096, 0x0480},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3098, 0x0480},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3206, 0x0B08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3208, 0x1E13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3202, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3200, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3100, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x30BA, 0x779C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x318E, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3064, 0x1982},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3064, 0x1802},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x302A, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x302C, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x302E, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3030, 0x00C6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3036, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3038, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x31AE, 0x0301},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x30BA, 0x769C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3002, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3004, 0x000c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3006, 0x043b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3008, 0x078b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x300A, 0x044A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x300C, 0x0469},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3012, 0x0148},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3180, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3062, 0x2333},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x30B0, 0x0118},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x30A2, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x30A6, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3082, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3040, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x318E, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x301A, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {REG_DELAY, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x301A, 0x10D8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {REG_DELAY, 20000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3088, 0x8242},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3086, 0x729B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3086, 0x4A31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3086, 0x4342},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x3086, 0x8E03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3086, 0x2A14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3086, 0x4578},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3086, 0x7B3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3086, 0xFF3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3086, 0xFF3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3086, 0xEA2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3086, 0x043D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3086, 0x102A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3086, 0x052A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3086, 0x1535},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3086, 0x2A05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3086, 0x3D10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3086, 0x2A04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3086, 0x2A14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3086, 0x3DFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3086, 0x3DFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3086, 0x3DEA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x3086, 0x2A04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3086, 0x622A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3086, 0x288E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x3086, 0x0036},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x3086, 0x2A08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x3086, 0x3D64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x3086, 0x7A3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3086, 0x0444},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x3086, 0x2C4B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x3086, 0x8F03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x3086, 0x430D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x3086, 0x2D46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x3086, 0x5F16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x3086, 0x530D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x3086, 0x1660},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3086, 0x3E4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x3086, 0x2904},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x3086, 0x2984},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x3086, 0x8E03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x3086, 0x2AFC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x3086, 0x5C1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x3086, 0x5754},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x3086, 0x495F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x3086, 0x5305},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x3086, 0x5307},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x3086, 0x4D2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x3086, 0xF810},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x3086, 0x164C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x3086, 0x0955},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3086, 0x562B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3086, 0xB82B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3086, 0x984E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3086, 0x1129},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3086, 0x9460},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3086, 0x5C19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3086, 0x5C1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3086, 0x4548},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3086, 0x4508},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3086, 0x4588},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x3086, 0x29B6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x3086, 0x8E01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x3086, 0x2AF8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x3086, 0x1702},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3086, 0x1709},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3086, 0x5C1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3086, 0x29B2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x3086, 0x170C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x3086, 0x1703},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x3086, 0x1715},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x3086, 0x5C13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x3086, 0x1711},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x3086, 0x170F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x3086, 0x5F2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x3086, 0x902A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x3086, 0xF22B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x3086, 0x8017},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x3086, 0x0617},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x3086, 0x0660},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x3086, 0x29A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x3086, 0x29A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x3086, 0x5F4D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x3086, 0x1C2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x3086, 0xFA29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x3086, 0x8345},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3086, 0xA817},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x3086, 0x072A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x3086, 0xFB17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x3086, 0x2945},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x3086, 0x8824},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x3086, 0x1708},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x3086, 0x5D29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x3086, 0x9288},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x3086, 0x102B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x3086, 0x048B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x3086, 0x1686},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x3086, 0x8D48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x3086, 0x4D4E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x3086, 0x2B80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x3086, 0x4C0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x3086, 0x6017},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x3086, 0x302A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x3086, 0xF217},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x3086, 0x1017},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3086, 0x8F29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3086, 0x8229},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x3086, 0x8329},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x3086, 0x435C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3086, 0x155F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x3086, 0x4D1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x3086, 0x2AFA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x3086, 0x8E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x3086, 0x2A98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x3086, 0x170A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3086, 0x4A0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x3086, 0x0B43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x3086, 0x168E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x3086, 0x032A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x3086, 0x9C45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x3086, 0x7817},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x3086, 0x072A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x3086, 0x9D17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x3086, 0x305D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x3086, 0x2944},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3086, 0x8810},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x3086, 0x2B04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3086, 0x530D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x3086, 0x4558},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x3086, 0x1708},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x3086, 0x8E01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x3086, 0x2A98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x3086, 0x8E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x3086, 0x769C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x3086, 0x779C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x3086, 0x4644},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3086, 0x1616},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3086, 0x907A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x3086, 0x1244},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x3086, 0x4B18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x3086, 0x4A04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x3086, 0x0643},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x3086, 0x1605},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x3086, 0x0743},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x3086, 0x1658},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x3086, 0x4316},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x3086, 0x5A43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x3086, 0x1645},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x3086, 0x588E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x3086, 0x032A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x3086, 0x9C45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x3086, 0x787B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x3086, 0x1707},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x3086, 0x2A9D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x3086, 0x530D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x3086, 0x8B16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x3086, 0x8617},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x3086, 0x2345},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x3086, 0x5825},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x3086, 0x1710},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x3086, 0x8E01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x3086, 0x2A98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x3086, 0x8E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x3086, 0x1710},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x3086, 0x8D60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x3086, 0x1244},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x3086, 0x4B2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x3086, 0x2C2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x2436, 0x000E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x320C, 0x0180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x320E, 0x0300},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x3210, 0x0500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x3204, 0x0B6D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x30FE, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x3ED8, 0x7B99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x3EDC, 0x9BA8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x3EDA, 0x9B9B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x3092, 0x006F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x3EEC, 0x1C04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x30BA, 0x779C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x3EF6, 0xA70F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x3044, 0x0410},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x3ED0, 0xFF44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x3ED4, 0x031F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x30FE, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x3EE2, 0x8866},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x3EE4, 0x6623},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x3EE6, 0x2263},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x30E0, 0x4283},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x30F0, 0x1283},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x30B0, 0x0118},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x31AC, 0x0C0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x3040, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x31AE, 0x0301},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x3082, 0x0009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x30BA, 0x769C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x31E0, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x318C, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x3060, 0x000B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x3096, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x3098, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x3206, 0x0B08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x3208, 0x1E13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x3202, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x3200, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x3100, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x3200, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x31D0, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x2400, 0x0003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x301E, 0x00A8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x2450, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x320A, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x3064, 0x1982},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x3064, 0x1802},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x302A, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x302C, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x302E, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x3030, 0x00C6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x3036, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x3038, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x31AE, 0x0301},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x30BA, 0x769C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x3002, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x3004, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x3006, 0x043B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x3008, 0x078B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x300A, 0x0448},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x300C, 0x0469},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x3012, 0x03DA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x3180, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x3062, 0x2333},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x30B0, 0x0118},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x30A2, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x30A6, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x3082, 0x0009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x3040, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x318E, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x301A, 0x10D8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const struct ar0230_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .hts_def = 0x0469 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .vts_def = 0x044a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .reg_list = ar0230_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const char * const ar0230_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int ar0230_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) //printk("czf reg = 0x%04x, value = 0x%04x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int ar0230_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (unlikely(regs[i].addr == REG_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) usleep_range(regs[i].val, regs[i].val * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = ar0230_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) AR0230_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int ar0230_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int ar0230_get_reso_dist(const struct ar0230_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const struct ar0230_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ar0230_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dist = ar0230_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int ar0230_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) const struct ar0230_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mode = ar0230_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ar0230->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __v4l2_ctrl_modify_range(ar0230->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) __v4l2_ctrl_modify_range(ar0230->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) AR0230_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int ar0230_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) const struct ar0230_mode *mode = ar0230->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int ar0230_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) code->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int ar0230_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (fse->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int ar0230_enable_test_pattern(struct ar0230 *ar0230, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void ar0230_get_module_inf(struct ar0230 *ar0230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) strlcpy(inf->base.sensor, AR0230_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) strlcpy(inf->base.module, ar0230->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) strlcpy(inf->base.lens, ar0230->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static long ar0230_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ar0230_get_module_inf(ar0230, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = ar0230_write_reg(ar0230->client, AR0230_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) AR0230_REG_VALUE_16BIT, AR0230_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = ar0230_write_reg(ar0230->client, AR0230_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) AR0230_REG_VALUE_16BIT, AR0230_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static long ar0230_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = ar0230_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = ar0230_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int __ar0230_start_stream(struct ar0230 *ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = ar0230_write_array(ar0230->client, ar0230->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = v4l2_ctrl_handler_setup(&ar0230->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return ar0230_write_reg(ar0230->client, AR0230_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) AR0230_REG_VALUE_16BIT, AR0230_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static int __ar0230_stop_stream(struct ar0230 *ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return ar0230_write_reg(ar0230->client, AR0230_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) AR0230_REG_VALUE_16BIT, AR0230_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int ar0230_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct i2c_client *client = ar0230->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (on == ar0230->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = __ar0230_start_stream(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) __ar0230_stop_stream(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ar0230->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int ar0230_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) const struct ar0230_mode *mode = ar0230->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int ar0230_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct i2c_client *client = ar0230->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ar0230->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ar0230->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ar0230->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static inline u32 ar0230_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return DIV_ROUND_UP(cycles, AR0230_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int __ar0230_power_on(struct ar0230 *ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) u32 i, delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct device *dev = &ar0230->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = clk_set_rate(ar0230->xvclk, AR0230_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_err(dev, "Failed to set xvclk rate (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) AR0230_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (clk_get_rate(ar0230->xvclk) != AR0230_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_warn(dev, "xvclk mismatched, modes are based on %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) AR0230_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = clk_prepare_enable(ar0230->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!IS_ERR(ar0230->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) gpiod_set_value_cansleep(ar0230->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) for (i = 0; i < AR0230_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) regulator_set_voltage(ar0230->supplies[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ar0230_regulator[i].val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ar0230_regulator[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret = regulator_bulk_enable(AR0230_NUM_SUPPLIES, ar0230->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!IS_ERR(ar0230->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) gpiod_set_value_cansleep(ar0230->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (!IS_ERR(ar0230->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) gpiod_set_value_cansleep(ar0230->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) delay_us = ar0230_cal_delay(92000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) clk_disable_unprepare(ar0230->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static void __ar0230_power_off(struct ar0230 *ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!IS_ERR(ar0230->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) gpiod_set_value_cansleep(ar0230->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) clk_disable_unprepare(ar0230->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (!IS_ERR(ar0230->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) gpiod_set_value_cansleep(ar0230->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) regulator_bulk_disable(AR0230_NUM_SUPPLIES, ar0230->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int ar0230_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return __ar0230_power_on(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static int ar0230_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) __ar0230_power_off(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int ar0230_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) const struct ar0230_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) mutex_lock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) try_fmt->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mutex_unlock(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int ar0230_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) config->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) V4L2_MBUS_VSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) V4L2_MBUS_PCLK_SAMPLE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int ar0230_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (fie->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static const struct dev_pm_ops ar0230_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SET_RUNTIME_PM_OPS(ar0230_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ar0230_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static const struct v4l2_subdev_internal_ops ar0230_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .open = ar0230_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static const struct v4l2_subdev_core_ops ar0230_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .s_power = ar0230_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .ioctl = ar0230_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .compat_ioctl32 = ar0230_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const struct v4l2_subdev_video_ops ar0230_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .s_stream = ar0230_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .g_frame_interval = ar0230_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const struct v4l2_subdev_pad_ops ar0230_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .enum_mbus_code = ar0230_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .enum_frame_size = ar0230_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .enum_frame_interval = ar0230_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .get_fmt = ar0230_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .set_fmt = ar0230_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .get_mbus_config = ar0230_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const struct v4l2_subdev_ops ar0230_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .core = &ar0230_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .video = &ar0230_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .pad = &ar0230_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static int ar0230_set_gain(struct ar0230 *ar0230, int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 again = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (gain < 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) gain = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (gain < 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) again = (u32)(32 - (32 * 128 / gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = ar0230_write_reg(ar0230->client, 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) AR0230_REG_VALUE_16BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret |= ar0230_write_reg(ar0230->client, AR0230_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) AR0230_REG_VALUE_16BIT, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) } else if (gain >= 256 && gain < 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) again = (u32)(32 - (64 * 128 / gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) again |= 0x0010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = ar0230_write_reg(ar0230->client, 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) AR0230_REG_VALUE_16BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret |= ar0230_write_reg(ar0230->client, AR0230_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) AR0230_REG_VALUE_16BIT, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } else if (gain >= 345 && gain < 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) again = (u32)(32 - (32 * 345 / gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret = ar0230_write_reg(ar0230->client, 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) AR0230_REG_VALUE_16BIT, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ret |= ar0230_write_reg(ar0230->client, AR0230_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) AR0230_REG_VALUE_16BIT, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) } else if (gain >= 691 && gain < 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) again = (u32)(32 - (64 * 345 / gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) again |= 0x0010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = ar0230_write_reg(ar0230->client, 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) AR0230_REG_VALUE_16BIT, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret |= ar0230_write_reg(ar0230->client, AR0230_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) AR0230_REG_VALUE_16BIT, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) } else if (gain >= 1382 && gain < 2764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) again = (u32)(32 - (128 * 345 / gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) again |= 0x0020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ret = ar0230_write_reg(ar0230->client, 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) AR0230_REG_VALUE_16BIT, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret |= ar0230_write_reg(ar0230->client, AR0230_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) AR0230_REG_VALUE_16BIT, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) } else if (gain >= 2764 && gain < 4023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) again = (u32)(32 - (256 * 345 / gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) again |= 0x0030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ret = ar0230_write_reg(ar0230->client, 0x3100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) AR0230_REG_VALUE_16BIT, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ret |= ar0230_write_reg(ar0230->client, AR0230_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) AR0230_REG_VALUE_16BIT, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int ar0230_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct ar0230 *ar0230 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct ar0230, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct i2c_client *client = ar0230->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = ar0230_write_reg(ar0230->client, AR0230_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) AR0230_REG_VALUE_16BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ret = ar0230_set_gain(ar0230, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = ar0230_write_reg(ar0230->client, AR0230_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) AR0230_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ctrl->val + ar0230->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ret = ar0230_enable_test_pattern(ar0230, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static const struct v4l2_ctrl_ops ar0230_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .s_ctrl = ar0230_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static int ar0230_initialize_controls(struct ar0230 *ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) const struct ar0230_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) handler = &ar0230->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mode = ar0230->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) handler->lock = &ar0230->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) 0, AR0230_PIXEL_RATE, 1, AR0230_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ar0230->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (ar0230->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ar0230->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ar0230->vblank = v4l2_ctrl_new_std(handler, &ar0230_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) AR0230_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) exposure_max = mode->vts_def - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ar0230->exposure = v4l2_ctrl_new_std(handler, &ar0230_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) V4L2_CID_EXPOSURE, AR0230_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) exposure_max, AR0230_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ar0230->anal_gain = v4l2_ctrl_new_std(handler, &ar0230_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ar0230->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) &ar0230_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ARRAY_SIZE(ar0230_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) 0, 0, ar0230_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_err(&ar0230->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ar0230->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static int ar0230_check_sensor_id(struct ar0230 *ar0230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct device *dev = &ar0230->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ret = ar0230_read_reg(client, AR0230_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) AR0230_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) dev_err(dev, "Unexpected sensor id(%x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_info(dev, "Detected AR0230 sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static int ar0230_configure_regulators(struct ar0230 *ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) for (i = 0; i < AR0230_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ar0230->supplies[i].supply =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ar0230_regulator[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return devm_regulator_bulk_get(&ar0230->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) AR0230_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ar0230->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static int ar0230_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct ar0230 *ar0230;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ar0230 = devm_kzalloc(dev, sizeof(*ar0230), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (!ar0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) &ar0230->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) &ar0230->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) &ar0230->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) &ar0230->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ar0230->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ar0230->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ar0230->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (IS_ERR(ar0230->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ar0230->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (IS_ERR(ar0230->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ar0230->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (IS_ERR(ar0230->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ret = ar0230_configure_regulators(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) mutex_init(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) sd = &ar0230->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) v4l2_i2c_subdev_init(sd, client, &ar0230_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ret = ar0230_initialize_controls(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ret = __ar0230_power_on(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = ar0230_check_sensor_id(ar0230, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) sd->internal_ops = &ar0230_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ar0230->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ret = media_entity_pads_init(&sd->entity, 1, &ar0230->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (strcmp(ar0230->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ar0230->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) AR0230_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) __ar0230_power_off(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) v4l2_ctrl_handler_free(&ar0230->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) mutex_destroy(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static int ar0230_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct ar0230 *ar0230 = to_ar0230(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) v4l2_ctrl_handler_free(&ar0230->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) mutex_destroy(&ar0230->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) __ar0230_power_off(ar0230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static const struct of_device_id ar0230_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) { .compatible = "aptina,ar0230" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) MODULE_DEVICE_TABLE(of, ar0230_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static const struct i2c_device_id ar0230_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) { "aptina,ar0230", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static struct i2c_driver ar0230_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .name = AR0230_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .pm = &ar0230_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .of_match_table = of_match_ptr(ar0230_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .probe = &ar0230_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .remove = &ar0230_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .id_table = ar0230_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return i2c_add_driver(&ar0230_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) i2c_del_driver(&ar0230_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) MODULE_DESCRIPTION("Aptina ar0230 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags