^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Aptina Sensor PLL Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/lcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "aptina-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) int aptina_pll_calculate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) const struct aptina_pll_limits *limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct aptina_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int mf_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int mf_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int p1_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int p1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dev_dbg(dev, "PLL: ext clock %u pix clock %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pll->ext_clock, pll->pix_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (pll->ext_clock < limits->ext_clock_min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pll->ext_clock > limits->ext_clock_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) dev_err(dev, "pll: invalid external clock frequency.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dev_err(dev, "pll: invalid pixel clock frequency.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Compute the multiplier M and combined N*P1 divisor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) div = gcd(pll->pix_clock, pll->ext_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pll->m = pll->pix_clock / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) div = pll->ext_clock / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* We now have the smallest M and N*P1 values that will result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * desired pixel clock frequency, but they might be out of the valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * range. Compute the factor by which we should multiply them given the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * following constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * - minimum/maximum multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * - minimum/maximum multiplier output clock frequency assuming the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * minimum/maximum N value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * - minimum/maximum combined N*P1 divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mf_min = DIV_ROUND_UP(limits->m_min, pll->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mf_min = max(mf_min, limits->out_clock_min /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (pll->ext_clock / limits->n_min * pll->m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mf_min = max(mf_min, limits->n_min * limits->p1_min / div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mf_max = limits->m_max / pll->m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mf_max = min(mf_max, limits->out_clock_max /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (pll->ext_clock / limits->n_max * pll->m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_dbg(dev, "pll: mf min %u max %u\n", mf_min, mf_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (mf_min > mf_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(dev, "pll: no valid combined N*P1 divisor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * We're looking for the highest acceptable P1 value for which a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * multiplier factor MF exists that fulfills the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 1. p1 is in the [p1_min, p1_max] range given by the limits and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 2. mf is in the [mf_min, mf_max] range computed above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * 3. div * mf is a multiple of p1, in order to compute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * n = div * mf / p1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * m = pll->m * mf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 4. the internal clock frequency, given by ext_clock / n, is in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * [int_clock_min, int_clock_max] range given by the limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 5. the output clock frequency, given by ext_clock / n * m, is in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * [out_clock_min, out_clock_max] range given by the limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * The first naive approach is to iterate over all p1 values acceptable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * according to (1) and all mf values acceptable according to (2), and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * stop at the first combination that fulfills (3), (4) and (5). This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * has a O(n^2) complexity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Instead of iterating over all mf values in the [mf_min, mf_max] range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * we can compute the mf increment between two acceptable values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * according to (3) with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * mf_inc = p1 / gcd(div, p1) (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * and round the minimum up to the nearest multiple of mf_inc. This will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * restrict the number of mf values to be checked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Furthermore, conditions (4) and (5) only restrict the range of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * acceptable p1 and mf values by modifying the minimum and maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * limits. (5) can be expressed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * ext_clock / (div * mf / p1) * m * mf >= out_clock_min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * ext_clock / (div * mf / p1) * m * mf <= out_clock_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * p1 >= out_clock_min * div / (ext_clock * m) (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * p1 <= out_clock_max * div / (ext_clock * m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Similarly, (4) can be expressed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * mf >= ext_clock * p1 / (int_clock_max * div) (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * mf <= ext_clock * p1 / (int_clock_min * div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * We can thus iterate over the restricted p1 range defined by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * combination of (1) and (7), and then compute the restricted mf range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * defined by the combination of (2), (6) and (8). If the resulting mf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * range is not empty, any value in the mf range is acceptable. We thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * select the mf lwoer bound and the corresponding p1 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (limits->p1_min == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(dev, "pll: P1 minimum value must be >0.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pll->ext_clock * pll->m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) p1_max = min(limits->p1_max, limits->out_clock_max * div /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (pll->ext_clock * pll->m));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (p1 = p1_max & ~1; p1 >= p1_min; p1 -= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int mf_inc = p1 / gcd(div, p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int mf_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int mf_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) limits->int_clock_max * div)), mf_inc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mf_high = min(mf_max, pll->ext_clock * p1 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (limits->int_clock_min * div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (mf_low > mf_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pll->n = div * mf_low / p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pll->m *= mf_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pll->p1 = p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(dev, "pll: no valid N and P1 divisors found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EXPORT_SYMBOL_GPL(aptina_pll_calculate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MODULE_DESCRIPTION("Aptina PLL Helpers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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