^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7842 - Analog Devices ADV7842 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * REF_01 - Analog devices, ADV7842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Register Settings Recommendations, Rev. 1.9, April 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * REF_02 - Analog devices, Software User Guide, UG-206,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ADV7842 I2C Register Maps, Rev. 0, November 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * REF_03 - Analog devices, Hardware User Guide, UG-214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Decoder and Digitizer , Rev. 0, January 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/cec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/i2c/adv7842.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(debug, "debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* ADV7842 system clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADV7842_fsc (28636360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADV7842_RGB_OUT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADV7842_OP_CH_SEL_GBR (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADV7842_OP_CH_SEL_GRB (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADV7842_OP_CH_SEL_BGR (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADV7842_OP_CH_SEL_RGB (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADV7842_OP_CH_SEL_BRG (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADV7842_OP_CH_SEL_RBG (5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADV7842_OP_SWAP_CB_CR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADV7842_MAX_ADDRS (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Arrays with configuration parameters for the ADV7842
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct adv7842_format_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 op_ch_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bool rgb_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool swap_cb_cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 op_format_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct adv7842_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct adv7842_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum adv7842_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum adv7842_vid_std_select vid_std_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const struct adv7842_format_info *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 edid[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } hdmi_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 edid[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } vga_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_fract aspect_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 rgb_quantization_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool is_cea_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct delayed_work delayed_work_enable_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool restart_stdi_once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool hdmi_port_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* i2c clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct i2c_client *i2c_sdp_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct i2c_client *i2c_sdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct i2c_client *i2c_cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_client *i2c_vdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct i2c_client *i2c_afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct i2c_client *i2c_hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct i2c_client *i2c_repeater;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_client *i2c_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_client *i2c_infoframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct i2c_client *i2c_cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct i2c_client *i2c_avlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *detect_tx_5v_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *analog_sampling_phase_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *free_run_color_ctrl_manual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *free_run_color_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *rgb_quantization_range_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct cec_adapter *cec_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 cec_addr[ADV7842_MAX_ADDRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 cec_valid_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool cec_enabled_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Unsupported timings. This device cannot support 720p30. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) V4L2_DV_BT_CEA_1280X720P30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct adv7842_video_standards {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 vid_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 v_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* sorted by number of lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* TODO add 1920x1080P60_RB (CVT timing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* sorted by number of lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* TODO add 1600X1200P60_RB (not a DMT timing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* sorted by number of lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* sorted by number of lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct v4l2_event adv7842_ev_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return container_of(sd, struct adv7842_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline unsigned hblanking(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return V4L2_DV_BT_BLANKING_WIDTH(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline unsigned htotal(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return V4L2_DV_BT_FRAME_WIDTH(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline unsigned vblanking(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return V4L2_DV_BT_BLANKING_HEIGHT(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline unsigned vtotal(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return V4L2_DV_BT_FRAME_HEIGHT(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 command, bool check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) union i2c_smbus_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) I2C_SMBUS_READ, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) I2C_SMBUS_BYTE_DATA, &data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return data.byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) v4l_err(client, "error reading %02x, %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) client->addr, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret = adv_smbus_read_byte_data_check(client, command, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) v4l_err(client, "read ok after %d retries\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) v4l_err(client, "read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static s32 adv_smbus_write_byte_data(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 command, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) union i2c_smbus_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) data.byte = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) err = i2c_smbus_xfer(client->adapter, client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) I2C_SMBUS_WRITE, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) I2C_SMBUS_BYTE_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) v4l_err(client, "error writing %02x, %02x, %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) client->addr, command, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void adv_smbus_write_byte_no_check(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 command, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) union i2c_smbus_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) data.byte = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) i2c_smbus_xfer(client->adapter, client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) I2C_SMBUS_WRITE, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) I2C_SMBUS_BYTE_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 command, unsigned length, const u8 *values)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) union i2c_smbus_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (length > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) length = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) data.block[0] = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) memcpy(data.block + 1, values, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) I2C_SMBUS_WRITE, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) I2C_SMBUS_I2C_BLOCK_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static inline int io_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return adv_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return adv_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline int io_write_clr_set(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return adv_smbus_read_byte_data(state->i2c_avlink, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return adv_smbus_read_byte_data(state->i2c_cec, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return adv_smbus_read_byte_data(state->i2c_sdp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return adv_smbus_read_byte_data(state->i2c_afe, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return adv_smbus_read_byte_data(state->i2c_repeater, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return adv_smbus_read_byte_data(state->i2c_edid, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return adv_smbus_read_byte_data(state->i2c_cp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return adv_smbus_read_byte_data(state->i2c_vdp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void main_reset(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) adv_smbus_write_byte_no_check(client, 0xff, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Format helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct adv7842_format_info adv7842_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct adv7842_format_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) adv7842_format_info(struct adv7842_state *state, u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (adv7842_formats[i].code == code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return &adv7842_formats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static inline bool is_analog_input(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ((state->mode == ADV7842_MODE_RGB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (state->mode == ADV7842_MODE_COMP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static inline bool is_digital_input(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return state->mode == ADV7842_MODE_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static inline const struct v4l2_dv_timings_cap *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return is_digital_input(sd) ? &adv7842_timings_cap_digital :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &adv7842_timings_cap_analog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u8 reg = io_read(sd, 0x6f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (reg & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val |= 1; /* port A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (reg & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val |= 2; /* port B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct adv7842_state *state = container_of(dwork,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct adv7842_state, delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int present = state->hdmi_edid.present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u8 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) __func__, present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (present & (0x04 << ADV7842_EDID_PORT_A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mask |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (present & (0x04 << ADV7842_EDID_PORT_B))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mask |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) io_write_and_or(sd, 0x20, 0xcf, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int edid_write_vga_segment(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) const u8 *val = state->vga_edid.edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* HPA disable on port A and B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) io_write_and_or(sd, 0x20, 0xcf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Disable I2C access to internal EDID ram from VGA DDC port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* edid segment pointer '1' for VGA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rep_write_and_or(sd, 0x77, 0xef, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) I2C_SMBUS_BLOCK_MAX, val + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Calculates the checksums and enables I2C access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * to internal EDID ram from VGA DDC port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (rep_read(sd, 0x79) & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (i == 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) v4l_err(client, "error enabling edid on VGA port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* enable hotplug after 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) const u8 *edid = state->hdmi_edid.edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int spa_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u16 pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* HPA disable on port A and B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) io_write_and_or(sd, 0x20, 0xcf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Disable I2C access to internal EDID ram from HDMI DDC ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) rep_write_and_or(sd, 0x77, 0xf3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!state->hdmi_edid.present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) cec_phys_addr_invalidate(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pa = v4l2_get_edid_phys_addr(edid, 256, &spa_loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) err = v4l2_phys_addr_validate(pa, &pa, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * Return an error if no location of the source physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * was found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (spa_loc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* edid segment pointer '0' for HDMI ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rep_write_and_or(sd, 0x77, 0xef, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) I2C_SMBUS_BLOCK_MAX, edid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (port == ADV7842_EDID_PORT_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) rep_write(sd, 0x72, edid[spa_loc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rep_write(sd, 0x73, edid[spa_loc + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) rep_write(sd, 0x74, edid[spa_loc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) rep_write(sd, 0x75, edid[spa_loc + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) rep_write(sd, 0x76, spa_loc & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Calculates the checksums and enables I2C access to internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * EDID ram from HDMI DDC ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (i == 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) v4l_err(client, "error enabling edid on port %c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cec_s_phys_addr(state->cec_adap, pa, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* enable hotplug after 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void adv7842_inv_register(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) v4l2_info(sd, "0x000-0x0ff: IO Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) v4l2_info(sd, "0xa00-0xaff: CP Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int adv7842_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) switch (reg->reg >> 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) reg->val = io_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) reg->val = avlink_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) reg->val = cec_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) reg->val = infoframe_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) reg->val = sdp_io_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) reg->val = sdp_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) reg->val = afe_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) reg->val = rep_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) reg->val = edid_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) reg->val = hdmi_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case 0xa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) reg->val = cp_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case 0xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) reg->val = vdp_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) adv7842_inv_register(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int adv7842_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u8 val = reg->val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) switch (reg->reg >> 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) io_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) avlink_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cec_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) infoframe_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) sdp_io_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) sdp_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) afe_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rep_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) edid_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) hdmi_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case 0xa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) cp_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case 0xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) vdp_write(sd, reg->reg & 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) adv7842_inv_register(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u16 cable_det = adv7842_read_cable_det(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u8 prim_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) const struct adv7842_video_standards *predef_vid_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) const struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) is_digital_input(sd) ? 250000 : 1000000, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* video std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) io_write(sd, 0x00, predef_vid_timings[i].vid_std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* v_freq and prim mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int configure_predefined_video_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) v4l2_dbg(1, debug, sd, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* reset to default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) io_write(sd, 0x16, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) io_write(sd, 0x17, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* disable embedded syncs for auto graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cp_write_and_or(sd, 0x81, 0xef, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) cp_write(sd, 0x26, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) cp_write(sd, 0x27, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) cp_write(sd, 0x28, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) cp_write(sd, 0x29, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) cp_write(sd, 0x8f, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) cp_write(sd, 0x90, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) cp_write(sd, 0xa5, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) cp_write(sd, 0xa6, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) cp_write(sd, 0xa7, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) cp_write(sd, 0xab, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) cp_write(sd, 0xac, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) switch (state->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case ADV7842_MODE_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case ADV7842_MODE_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err = find_and_set_predefined_video_timings(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) 0x01, adv7842_prim_mode_comp, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) err = find_and_set_predefined_video_timings(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) 0x02, adv7842_prim_mode_gr, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case ADV7842_MODE_HDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) err = find_and_set_predefined_video_timings(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) 0x05, adv7842_prim_mode_hdmi_comp, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) err = find_and_set_predefined_video_timings(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) 0x06, adv7842_prim_mode_hdmi_gr, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __func__, state->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) err = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static void configure_custom_video_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) const struct v4l2_bt_timings *bt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u32 width = htotal(bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u32 height = vtotal(bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u16 cp_start_eav = width - bt->hfrontporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u16 cp_start_vbi = height - bt->vfrontporch + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) const u8 pll[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) 0xc0 | ((width >> 8) & 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) width & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) v4l2_dbg(2, debug, sd, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) switch (state->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case ADV7842_MODE_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case ADV7842_MODE_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* auto graphics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) io_write(sd, 0x00, 0x07); /* video std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) io_write(sd, 0x01, 0x02); /* prim mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* enable embedded syncs for auto graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) cp_write_and_or(sd, 0x81, 0xef, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* IO-map reg. 0x16 and 0x17 should be written in sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* active video - horizontal timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) cp_write(sd, 0x27, (cp_start_sav & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) cp_write(sd, 0x29, (cp_start_eav & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* active video - vertical timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ((cp_end_vbi >> 8) & 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) cp_write(sd, 0xa7, cp_end_vbi & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case ADV7842_MODE_HDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* set default prim_mode/vid_std for HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) according to [REF_03, c. 4.2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) io_write(sd, 0x00, 0x02); /* video std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) io_write(sd, 0x01, 0x06); /* prim mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) __func__, state->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) cp_write(sd, 0x90, ch1_fr_ll & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) cp_write(sd, 0xab, (height >> 4) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) cp_write(sd, 0xac, (height & 0x0f) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) u8 offset_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (auto_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) offset_a = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) offset_b = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) offset_c = 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) __func__, auto_offset ? "Auto" : "Manual",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) offset_a, offset_b, offset_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) offset_buf[3] = offset_c & 0x0ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Registers must be written in this order with no i2c access in between */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u8 gain_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u8 gain_man = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u8 agc_mode_man = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (auto_gain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) gain_man = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) agc_mode_man = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) gain_a = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) gain_b = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) gain_c = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) __func__, auto_gain ? "Auto" : "Manual",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) gain_a, gain_b, gain_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) gain_buf[3] = ((gain_c & 0x0ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* Registers must be written in this order with no i2c access in between */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void set_rgb_quantization_range(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) bool rgb_output = io_read(sd, 0x02) & 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u8 y = HDMI_COLORSPACE_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (hdmi_signal && (io_read(sd, 0x60) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) y = infoframe_read(sd, 0x01) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) __func__, state->rgb_quantization_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) rgb_output, hdmi_signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) switch (state->rgb_quantization_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case V4L2_DV_RGB_RANGE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (state->mode == ADV7842_MODE_RGB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* Receiving analog RGB signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * Set RGB full range (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) io_write_and_or(sd, 0x02, 0x0f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (state->mode == ADV7842_MODE_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Receiving analog YPbPr signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * Set automode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) io_write_and_or(sd, 0x02, 0x0f, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (hdmi_signal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Receiving HDMI signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * Set automode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) io_write_and_or(sd, 0x02, 0x0f, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* Receiving DVI-D signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * ADV7842 selects RGB limited range regardless of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * input format (CE/IT) in automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* RGB limited range (16-235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) io_write_and_or(sd, 0x02, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* RGB full range (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) io_write_and_or(sd, 0x02, 0x0f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (is_digital_input(sd) && rgb_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case V4L2_DV_RGB_RANGE_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (state->mode == ADV7842_MODE_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* YCrCb limited range (16-235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) io_write_and_or(sd, 0x02, 0x0f, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (y != HDMI_COLORSPACE_RGB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* RGB limited range (16-235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) io_write_and_or(sd, 0x02, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case V4L2_DV_RGB_RANGE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (state->mode == ADV7842_MODE_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* YCrCb full range (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) io_write_and_or(sd, 0x02, 0x0f, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (y != HDMI_COLORSPACE_RGB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* RGB full range (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) io_write_and_or(sd, 0x02, 0x0f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (is_analog_input(sd) || hdmi_signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Adjust gain/offset for DVI-D signals only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (rgb_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* TODO SDP ctrls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) contrast/brightness/hue/free run is acting a bit strange,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) not sure if sdp csc is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* standard ctrls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) cp_write(sd, 0x3c, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) sdp_write(sd, 0x14, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* ignore lsb sdp 0x17[3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) cp_write(sd, 0x3a, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) sdp_write(sd, 0x13, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* ignore lsb sdp 0x17[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) cp_write(sd, 0x3b, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) sdp_write(sd, 0x15, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* ignore lsb sdp 0x17[5:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) cp_write(sd, 0x3d, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) sdp_write(sd, 0x16, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* ignore lsb sdp 0x17[7:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* custom ctrls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) afe_write(sd, 0xc8, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u8 R = (ctrl->val & 0xff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) u8 G = (ctrl->val & 0x00ff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) u8 B = (ctrl->val & 0x0000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* RGB -> YUV, numerical approximation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int Y = 66 * R + 129 * G + 25 * B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) int U = -38 * R - 74 * G + 112 * B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int V = 112 * R - 94 * G - 18 * B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Scale down to 8 bits with rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) Y = (Y + 128) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) U = (U + 128) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) V = (V + 128) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* make U,V positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) Y += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) U += 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) V += 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* CP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) cp_write(sd, 0xc1, R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) cp_write(sd, 0xc0, G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) cp_write(sd, 0xc2, B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* SDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sdp_write(sd, 0xde, Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case V4L2_CID_DV_RX_RGB_RANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) state->rgb_quantization_range = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) set_rgb_quantization_range(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static inline bool no_power(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return io_read(sd, 0x0c) & 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static inline bool no_cp_signal(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static inline bool is_hdmi(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return hdmi_read(sd, 0x05) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (io_read(sd, 0x0c) & 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) *status |= V4L2_IN_ST_NO_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (state->mode == ADV7842_MODE_SDP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* status from SDP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (!(sdp_read(sd, 0x5A) & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) *status |= V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* status from CP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) !(cp_read(sd, 0xb1) & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* TODO channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) *status |= V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *status |= V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct stdi_readback {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u16 bl, lcf, lcvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u8 hs_pol, vs_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) bool interlaced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static int stdi2dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct stdi_readback *stdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) u32 pix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) adv7842_get_dv_timings_cap(sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) adv7842_check_dv_timings, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (vtotal(bt) != stdi->lcf + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (bt->vsync != stdi->lcvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pix_clk = hfreq * htotal(bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if ((pix_clk < bt->pixelclock + 1000000) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) (pix_clk > bt->pixelclock - 1000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) *timings = v4l2_dv_timings_presets[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) false, timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) false, state->aspect_ratio, timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) v4l2_dbg(2, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) __func__, stdi->lcvs, stdi->lcf, stdi->bl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) stdi->hs_pol, stdi->vs_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) adv7842_g_input_status(sd, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (status & V4L2_IN_ST_NO_SIGNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) stdi->lcvs = cp_read(sd, 0xb3) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) stdi->hs_pol = 'x';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) stdi->vs_pol = 'x';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) v4l2_dbg(2, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) __func__, stdi->lcf, stdi->bl, stdi->lcvs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) stdi->hs_pol, stdi->vs_pol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) stdi->interlaced ? "interlaced" : "progressive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return v4l2_enum_dv_timings_cap(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) *cap = *adv7842_get_dv_timings_cap(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if the format is listed in adv7842_timings[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) is_digital_input(sd) ? 250000 : 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) adv7842_check_dv_timings, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct v4l2_bt_timings *bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct stdi_readback stdi = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) memset(timings, 0, sizeof(struct v4l2_dv_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* SDP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (state->mode == ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* read STDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (read_stdi(sd, &stdi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) state->restart_stdi_once = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) bt->interlaced = stdi.interlaced ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (is_digital_input(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) timings->type = V4L2_DV_BT_656_1120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (is_hdmi(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* adjust for deep color mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) bt->pixelclock = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) hdmi_read(sd, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) hdmi_read(sd, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) hdmi_read(sd, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) hdmi_read(sd, 0x2b)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) hdmi_read(sd, 0x2f)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) hdmi_read(sd, 0x33)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (bt->interlaced == V4L2_DV_INTERLACED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) hdmi_read(sd, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) hdmi_read(sd, 0x2d)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) hdmi_read(sd, 0x31)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) hdmi_read(sd, 0x35)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) bt->il_vfrontporch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) bt->il_vsync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) bt->il_vbackporch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) adv7842_fill_optional_dv_timings_fields(sd, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) freq < bt->pixelclock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) u32 delta_freq = abs(freq - reduced_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* find format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * Since LCVS values are inaccurate [REF_03, p. 339-340],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (!stdi2dv_timings(sd, &stdi, timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) stdi.lcvs += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (!stdi2dv_timings(sd, &stdi, timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) stdi.lcvs -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (stdi2dv_timings(sd, &stdi, timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * The STDI block may measure wrong values, especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * for lcvs and lcf. If the driver can not find any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * valid timing, the STDI block is restarted to measure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * the video timings again. The function will return an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * error, but the restart of STDI will generate a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * STDI interrupt and the format detection process will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * restart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (state->restart_stdi_once) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* TODO restart STDI for Sync Channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* enter one-shot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) cp_write_and_or(sd, 0x86, 0xf9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* trigger STDI restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) cp_write_and_or(sd, 0x86, 0xf9, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* reset to continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) cp_write_and_or(sd, 0x86, 0xf9, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) state->restart_stdi_once = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) state->restart_stdi_once = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) timings, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct v4l2_bt_timings *bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (state->mode == ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) adv7842_check_dv_timings, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) adv7842_fill_optional_dv_timings_fields(sd, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) state->timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* Use prim_mode and vid_std when available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) err = configure_predefined_video_timings(sd, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* custom settings when the video format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) does not have prim_mode/vid_std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) configure_custom_video_timings(sd, bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) set_rgb_quantization_range(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) timings, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (state->mode == ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) *timings = state->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static void enable_input(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) set_rgb_quantization_range(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) switch (state->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) case ADV7842_MODE_SDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) case ADV7842_MODE_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) case ADV7842_MODE_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) case ADV7842_MODE_HDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) __func__, state->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static void disable_input(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static void sdp_csc_coeff(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) const struct adv7842_sdp_csc_coeff *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* csc auto/manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (!c->manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /* csc scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* A coeff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) sdp_io_write(sd, 0xe1, c->A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) sdp_io_write(sd, 0xe3, c->A2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) sdp_io_write(sd, 0xe5, c->A3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* A scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) sdp_io_write(sd, 0xe7, c->A4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* B coeff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) sdp_io_write(sd, 0xe9, c->B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) sdp_io_write(sd, 0xeb, c->B2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) sdp_io_write(sd, 0xed, c->B3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* B scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) sdp_io_write(sd, 0xef, c->B4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* C coeff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) sdp_io_write(sd, 0xf1, c->C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) sdp_io_write(sd, 0xf3, c->C2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) sdp_io_write(sd, 0xf5, c->C3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /* C scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) sdp_io_write(sd, 0xf7, c->C4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static void select_input(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) enum adv7842_vid_std_select vid_std_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) switch (state->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) case ADV7842_MODE_SDP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) io_write(sd, 0x01, 0); /* prim mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* enable embedded syncs for auto graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) cp_write_and_or(sd, 0x81, 0xef, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) afe_write(sd, 0x00, 0x00); /* power up ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) afe_write(sd, 0xc8, 0x00); /* phase control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /* script says register 0xde, which don't exist in manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /* Manual analog input muxing mode, CVBS (6.4)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) afe_write_and_or(sd, 0x02, 0x7f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) afe_write(sd, 0x12, 0x63); /* ADI recommend write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* SDP recommended settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* deinterlacer enabled and 3D comb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) case ADV7842_MODE_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) case ADV7842_MODE_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* Automatic analog input muxing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) afe_write_and_or(sd, 0x02, 0x7f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* set mode and select free run resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) io_write(sd, 0x00, vid_std_select); /* video std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) io_write(sd, 0x01, 0x02); /* prim mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) for auto graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) afe_write(sd, 0x00, 0x00); /* power up ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) afe_write(sd, 0xc8, 0x00); /* phase control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (state->mode == ADV7842_MODE_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* force to YCrCb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) io_write_and_or(sd, 0x02, 0x0f, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* force to RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) io_write_and_or(sd, 0x02, 0x0f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* set ADI recommended settings for digitizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* "ADV7842 Register Settings Recommendations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * (rev. 1.8, November 2010)" p. 9. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* set to default gain for RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) cp_write(sd, 0x73, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) cp_write(sd, 0x74, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) cp_write(sd, 0x75, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) cp_write(sd, 0x76, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) case ADV7842_MODE_HDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* Automatic analog input muxing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) afe_write_and_or(sd, 0x02, 0x7f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* set mode and select free run resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (state->hdmi_port_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) hdmi_write(sd, 0x00, 0x02); /* select port A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) hdmi_write(sd, 0x00, 0x03); /* select port B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) io_write(sd, 0x00, vid_std_select); /* video std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) io_write(sd, 0x01, 5); /* prim mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) for auto graphics mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* set ADI recommended settings for HDMI: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* "ADV7842 Register Settings Recommendations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * (rev. 1.8, November 2010)" p. 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) hdmi_write(sd, 0xc0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) Improve robustness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) hdmi_write(sd, 0x85, 0x1f); /* equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) hdmi_write(sd, 0x89, 0x04); /* equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) hdmi_write(sd, 0x93, 0x04); /* equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) hdmi_write(sd, 0x94, 0x1e); /* equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) hdmi_write(sd, 0x9d, 0x02); /* equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) afe_write(sd, 0x00, 0xff); /* power down ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) afe_write(sd, 0xc8, 0x40); /* phase control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* set to default gain for HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) cp_write(sd, 0x73, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) cp_write(sd, 0x74, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) cp_write(sd, 0x75, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) cp_write(sd, 0x76, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* reset ADI recommended settings for digitizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* "ADV7842 Register Settings Recommendations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * (rev. 2.5, June 2010)" p. 17. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) /* CP coast control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) cp_write(sd, 0xc3, 0x33); /* Component mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* color space conversion, autodetect color space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) io_write_and_or(sd, 0x02, 0x0f, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) __func__, state->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static int adv7842_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) case ADV7842_SELECT_HDMI_PORT_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) state->mode = ADV7842_MODE_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) state->hdmi_port_a = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) case ADV7842_SELECT_HDMI_PORT_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) state->mode = ADV7842_MODE_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) state->hdmi_port_a = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) case ADV7842_SELECT_VGA_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) state->mode = ADV7842_MODE_COMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) case ADV7842_SELECT_VGA_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) state->mode = ADV7842_MODE_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) case ADV7842_SELECT_SDP_CVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) state->mode = ADV7842_MODE_SDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) case ADV7842_SELECT_SDP_YC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) state->mode = ADV7842_MODE_SDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) disable_input(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) select_input(sd, state->vid_std_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) enable_input(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (code->index >= ARRAY_SIZE(adv7842_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) code->code = adv7842_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static void adv7842_fill_format(struct adv7842_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) memset(format, 0, sizeof(*format));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) format->width = state->timings.bt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) format->height = state->timings.bt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) format->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) format->colorspace = (state->timings.bt.height <= 576) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * Compute the op_ch_sel value required to obtain on the bus the component order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * corresponding to the selected format taking into account bus reordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * applied by the board at the output of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * The following table gives the op_ch_value from the format component order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * adv7842_bus_order value in row).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * ----------+-------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * RGB (NOP) | GBR GRB BGR RGB BRG RBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * GRB (1-2) | BGR RGB GBR GRB RBG BRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * RBG (2-3) | GRB GBR BRG RBG BGR RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * BGR (1-3) | RBG BRG RGB BGR GRB GBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * BRG (ROR) | BRG RBG GRB GBR RGB BGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * GBR (ROL) | RGB BGR RBG BRG GBR GRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define _SEL(a, b, c, d, e, f) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define _BUS(x) [ADV7842_BUS_ORDER_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static const unsigned int op_ch_sel[6][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static void adv7842_setup_format(struct adv7842_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) io_write_clr_set(sd, 0x02, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) state->format->rgb_out ? ADV7842_RGB_OUT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) io_write(sd, 0x03, state->format->op_format_sel |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) state->pdata.op_format_mode_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) io_write_clr_set(sd, 0x05, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) set_rgb_quantization_range(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) static int adv7842_get_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (format->pad != ADV7842_PAD_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (state->mode == ADV7842_MODE_SDP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /* SPD block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (!(sdp_read(sd, 0x5a) & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) format->format.width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* valid signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (state->norm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) format->format.height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) format->format.height = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) adv7842_fill_format(state, &format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct v4l2_mbus_framefmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) format->format.code = fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) format->format.code = state->format->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static int adv7842_set_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) const struct adv7842_format_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (format->pad != ADV7842_PAD_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (state->mode == ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return adv7842_get_format(sd, cfg, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) info = adv7842_format_info(state, format->format.code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) adv7842_fill_format(state, &format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) format->format.code = info->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct v4l2_mbus_framefmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) fmt->code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) state->format = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) adv7842_setup_format(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* Enable SSPD, STDI and CP locked/unlocked interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) io_write(sd, 0x46, 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* ESDP_50HZ_DET interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) io_write(sd, 0x5a, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) io_write(sd, 0x73, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) io_write(sd, 0x78, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* Enable SDP Standard Detection Change and SDP Video Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) io_write(sd, 0xa0, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* Enable HDMI_MODE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) io_write(sd, 0x69, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) io_write(sd, 0x46, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) io_write(sd, 0x5a, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) io_write(sd, 0x73, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) io_write(sd, 0x78, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) io_write(sd, 0xa0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) io_write(sd, 0x69, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if ((cec_read(sd, 0x11) & 0x01) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (tx_raw_status & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) 1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (tx_raw_status & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) u8 nack_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) u8 low_drive_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * We set this status bit since this hardware performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * retransmissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) status = CEC_TX_STATUS_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) nack_cnt = cec_read(sd, 0x14) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (nack_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) status |= CEC_TX_STATUS_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) low_drive_cnt = cec_read(sd, 0x14) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (low_drive_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) status |= CEC_TX_STATUS_LOW_DRIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) cec_transmit_done(state->cec_adap, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) 0, nack_cnt, low_drive_cnt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (tx_raw_status & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) u8 cec_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /* cec controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) cec_irq = io_read(sd, 0x93) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (!cec_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) adv7842_cec_tx_raw_status(sd, cec_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (cec_irq & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) struct cec_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) msg.len = cec_read(sd, 0x25) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (msg.len > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) msg.len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (msg.len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) for (i = 0; i < msg.len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) msg.msg[i] = cec_read(sd, i + 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) cec_write(sd, 0x26, 0x01); /* re-enable rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) cec_received_msg(state->cec_adap, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) io_write(sd, 0x94, cec_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) struct adv7842_state *state = cec_get_drvdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (!state->cec_enabled_adap && enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) cec_write(sd, 0x2c, 0x01); /* cec soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* enabled irqs: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /* tx: ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /* tx: arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* tx: retry timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /* rx: ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) cec_write(sd, 0x26, 0x01); /* enable rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) } else if (state->cec_enabled_adap && !enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) /* disable cec interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) io_write_clr_set(sd, 0x96, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) /* disable address mask 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) cec_write_clr_set(sd, 0x27, 0x70, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* power down cec section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) state->cec_valid_addrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) state->cec_enabled_adap = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct adv7842_state *state = cec_get_drvdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) unsigned int i, free_idx = ADV7842_MAX_ADDRS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (!state->cec_enabled_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (addr == CEC_LOG_ADDR_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) cec_write_clr_set(sd, 0x27, 0x70, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) state->cec_valid_addrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) bool is_valid = state->cec_valid_addrs & (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) free_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if (is_valid && state->cec_addr[i] == addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (i == ADV7842_MAX_ADDRS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) i = free_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (i == ADV7842_MAX_ADDRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) state->cec_addr[i] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) state->cec_valid_addrs |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /* enable address mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) cec_write_clr_set(sd, 0x27, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* set address for mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) cec_write_clr_set(sd, 0x28, 0x0f, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* enable address mask 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) cec_write_clr_set(sd, 0x27, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) /* set address for mask 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* enable address mask 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) cec_write_clr_set(sd, 0x27, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* set address for mask 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) cec_write_clr_set(sd, 0x29, 0x0f, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) u32 signal_free_time, struct cec_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct adv7842_state *state = cec_get_drvdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) u8 len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * The number of retries is the number of attempts - 1, but retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) * at least once. It's not clear if a value of 0 is allowed, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) * let's do at least one retry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (len > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) cec_write(sd, i, msg->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /* set length (data + header) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) cec_write(sd, 0x10, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /* start transmit, enable tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) cec_write(sd, 0x11, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static const struct cec_adap_ops adv7842_cec_adap_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .adap_enable = adv7842_cec_adap_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .adap_log_addr = adv7842_cec_adap_log_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .adap_transmit = adv7842_cec_adap_transmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) u8 irq_status[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) adv7842_irq_enable(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) /* read status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) irq_status[0] = io_read(sd, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) irq_status[1] = io_read(sd, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) irq_status[2] = io_read(sd, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) irq_status[3] = io_read(sd, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) irq_status[4] = io_read(sd, 0x9d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) irq_status[5] = io_read(sd, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /* and clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if (irq_status[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) io_write(sd, 0x44, irq_status[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (irq_status[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) io_write(sd, 0x58, irq_status[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (irq_status[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) io_write(sd, 0x71, irq_status[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (irq_status[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) io_write(sd, 0x76, irq_status[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (irq_status[4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) io_write(sd, 0x9e, irq_status[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (irq_status[5])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) io_write(sd, 0x67, irq_status[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) adv7842_irq_enable(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) irq_status[0], irq_status[1], irq_status[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) irq_status[3], irq_status[4], irq_status[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /* format change CP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) fmt_change_cp = irq_status[0] & 0x9c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /* format change SDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (state->mode == ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) fmt_change_sdp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* digital format CP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (is_digital_input(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) fmt_change_digital = irq_status[3] & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) fmt_change_digital = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /* format change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) __func__, fmt_change_cp, fmt_change_digital,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) fmt_change_sdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* HDMI/DVI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (irq_status[5] & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) set_rgb_quantization_range(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) /* cec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) adv7842_cec_isr(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) /* tx 5v detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (irq_status[2] & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) adv7842_s_detect_tx_5v_ctrl(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) u8 *data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) switch (edid->pad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) case ADV7842_EDID_PORT_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) case ADV7842_EDID_PORT_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (state->hdmi_edid.present & (0x04 << edid->pad))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) data = state->hdmi_edid.edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) case ADV7842_EDID_PORT_VGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (state->vga_edid.present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) data = state->vga_edid.edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) if (edid->start_block == 0 && edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) edid->blocks = data ? 2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (edid->start_block >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (edid->start_block + edid->blocks > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) edid->blocks = 2 - edid->start_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) memset(e->reserved, 0, sizeof(e->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if (e->pad > ADV7842_EDID_PORT_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) if (e->start_block != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (e->blocks > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) e->blocks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) /* todo, per edid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) e->edid[0x16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) switch (e->pad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) case ADV7842_EDID_PORT_VGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) memset(&state->vga_edid.edid, 0, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) state->vga_edid.present = e->blocks ? 0x1 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) err = edid_write_vga_segment(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) case ADV7842_EDID_PORT_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) case ADV7842_EDID_PORT_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) memset(&state->hdmi_edid.edid, 0, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (e->blocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) state->hdmi_edid.present |= 0x04 << e->pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) state->hdmi_edid.present &= ~(0x04 << e->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) adv7842_s_detect_tx_5v_ctrl(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) err = edid_write_hdmi_segment(sd, e->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) struct adv7842_cfg_read_infoframe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) const char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) u8 present_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) u8 head_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) u8 payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) u8 buffer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) union hdmi_infoframe frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) if (!(io_read(sd, 0x60) & cri->present_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) v4l2_info(sd, "%s infoframe not received\n", cri->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) buffer[i] = infoframe_read(sd, cri->head_addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) len = buffer[2] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (len + 3 > sizeof(buffer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (hdmi_infoframe_unpack(&frame, buffer, len + 3) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) hdmi_infoframe_log(KERN_INFO, dev, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static void adv7842_log_infoframes(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) static const struct adv7842_cfg_read_infoframe cri[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) { "AVI", 0x01, 0xe0, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) { "Audio", 0x02, 0xe3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) { "SDP", 0x04, 0xe6, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) { "Vendor", 0x10, 0xec, 0x54 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) if (!(hdmi_read(sd, 0x05) & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) for (i = 0; i < ARRAY_SIZE(cri); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) log_infoframe(sd, &cri[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /* Let's keep it here for now, as it could be useful for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) static const char * const prim_mode_txt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) "SDP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) "Component",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) "Graphics",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) "CVBS & HDMI AUDIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) "HDMI-Comp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) "HDMI-GR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /* SDP (Standard definition processor) block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) v4l2_info(sd, "SDP: free run: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) "valid SD/PR signal detected" : "invalid/no signal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (sdp_signal_detected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) static const char * const sdp_std_txt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) "NTSC-M/J",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) "1?",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) "NTSC-443",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) "60HzSECAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) "PAL-M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) "5?",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) "PAL-60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) "7?", "8?", "9?", "a?", "b?",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) "PAL-CombN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) "d?",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) "PAL-BGHID",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) "SECAM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) v4l2_info(sd, "SDP: standard %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) v4l2_info(sd, "SDP: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) v4l2_info(sd, "SDP: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) v4l2_info(sd, "SDP: deinterlacer %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) v4l2_info(sd, "SDP: csc %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static int adv7842_cp_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) /* CP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) u8 reg_io_0x02 = io_read(sd, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) u8 reg_io_0x21 = io_read(sd, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) u8 reg_rep_0x77 = rep_read(sd, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) u8 reg_rep_0x7d = rep_read(sd, 0x7d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) bool audio_mute = io_read(sd, 0x65) & 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static const char * const csc_coeff_sel_rb[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) "reserved", "reserved", "reserved", "reserved", "manual"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static const char * const input_color_space_txt[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) "RGB limited range (16-235)", "RGB full range (0-255)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) "xvYCC Bt.601", "xvYCC Bt.709",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) "invalid", "invalid", "invalid", "invalid", "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) "invalid", "invalid", "automatic"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static const char * const rgb_quantization_range_txt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) "Automatic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) "RGB limited range (16-235)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) "RGB full range (0-255)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static const char * const deep_color_mode_txt[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) "8-bits per channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) "10-bits per channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) "12-bits per channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) "16-bits per channel (not supported)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) v4l2_info(sd, "-----Chip status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) state->hdmi_port_a ? "A" : "B");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) v4l2_info(sd, "EDID A %s, B %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) v4l2_info(sd, "HPD A %s, B %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) reg_io_0x21 & 0x02 ? "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) reg_io_0x21 & 0x01 ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (state->cec_enabled_adap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) bool is_valid = state->cec_valid_addrs & (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (is_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) v4l2_info(sd, "CEC Logical Address: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) state->cec_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) v4l2_info(sd, "-----Signal status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) if (state->hdmi_port_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) v4l2_info(sd, "Cable detected (+5V power): %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) io_read(sd, 0x6f) & 0x02 ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) v4l2_info(sd, "TMDS signal detected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) v4l2_info(sd, "TMDS signal locked: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) v4l2_info(sd, "Cable detected (+5V power):%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) io_read(sd, 0x6f) & 0x01 ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) v4l2_info(sd, "TMDS signal detected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) v4l2_info(sd, "TMDS signal locked: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) v4l2_info(sd, "CP free run: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) (io_read(sd, 0x01) & 0x70) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) v4l2_info(sd, "-----Video Timings-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (no_cp_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) v4l2_info(sd, "STDI: not locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) u32 lcvs = cp_read(sd, 0xb3) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) v4l2_info(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) lcf, bl, lcvs, fcl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) (cp_read(sd, 0xb1) & 0x40) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) "interlaced" : "progressive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) hs_pol, vs_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) if (adv7842_query_dv_timings(sd, &timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) v4l2_info(sd, "No video detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) v4l2_print_dv_timings(sd->name, "Detected format: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) &timings, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) v4l2_print_dv_timings(sd->name, "Configured format: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) &state->timings, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (no_cp_signal(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) v4l2_info(sd, "-----Color space-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) v4l2_info(sd, "RGB quantization range ctrl: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) rgb_quantization_range_txt[state->rgb_quantization_range]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) v4l2_info(sd, "Input color space: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) input_color_space_txt[reg_io_0x02 >> 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) "(16-235)" : "(0-255)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) v4l2_info(sd, "Color space conversion: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (!is_digital_input(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) v4l2_info(sd, "HDCP encrypted content: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) v4l2_info(sd, "HDCP keys read: %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) if (!is_hdmi(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) audio_pll_locked ? "locked" : "not locked",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) audio_sample_packet_detect ? "detected" : "not detected",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) audio_mute ? "muted" : "enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) if (audio_pll_locked && audio_sample_packet_detect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) v4l2_info(sd, "Audio format: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) (hdmi_read(sd, 0x5c) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) (hdmi_read(sd, 0x5d) & 0xf0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) (hdmi_read(sd, 0x5e) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) hdmi_read(sd, 0x5f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) v4l2_info(sd, "AV Mute: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) v4l2_info(sd, "Deep color mode: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) adv7842_log_infoframes(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) static int adv7842_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (state->mode == ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return adv7842_sdp_log_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) return adv7842_cp_log_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (state->mode != ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) if (!(sdp_read(sd, 0x5A) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) *std = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) switch (sdp_read(sd, 0x52) & 0x0f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) /* NTSC-M/J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) *std &= V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) /* NTSC-443 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) *std &= V4L2_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) /* 60HzSECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) *std &= V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) /* PAL-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) *std &= V4L2_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) /* PAL-60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) *std &= V4L2_STD_PAL_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) case 0xc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) /* PAL-CombN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) *std &= V4L2_STD_PAL_Nc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) case 0xe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) /* PAL-BGHID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) *std &= V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) case 0xf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) /* SECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) *std &= V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) *std &= V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) if (s && s->adjust) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) sdp_io_write(sd, 0x97, s->hs_width & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) sdp_io_write(sd, 0x99, s->de_beg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) sdp_io_write(sd, 0x9b, s->de_end & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) sdp_io_write(sd, 0xa8, s->vs_beg_o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) sdp_io_write(sd, 0xa9, s->vs_beg_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) sdp_io_write(sd, 0xaa, s->vs_end_o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) sdp_io_write(sd, 0xab, s->vs_end_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) sdp_io_write(sd, 0xac, s->de_v_beg_o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) sdp_io_write(sd, 0xad, s->de_v_beg_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) sdp_io_write(sd, 0xae, s->de_v_end_o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) sdp_io_write(sd, 0xaf, s->de_v_end_e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) /* set to default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) sdp_io_write(sd, 0x94, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) sdp_io_write(sd, 0x95, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) sdp_io_write(sd, 0x96, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) sdp_io_write(sd, 0x97, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) sdp_io_write(sd, 0x98, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) sdp_io_write(sd, 0x99, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) sdp_io_write(sd, 0x9a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) sdp_io_write(sd, 0x9b, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) sdp_io_write(sd, 0xa8, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) sdp_io_write(sd, 0xa9, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) sdp_io_write(sd, 0xaa, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) sdp_io_write(sd, 0xab, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) sdp_io_write(sd, 0xac, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) sdp_io_write(sd, 0xad, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) sdp_io_write(sd, 0xae, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) sdp_io_write(sd, 0xaf, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) struct adv7842_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) if (state->mode != ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (norm & V4L2_STD_625_50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) else if (norm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) adv7842_s_sdp_io(sd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) if (norm & V4L2_STD_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) state->norm = norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) if (state->mode != ADV7842_MODE_SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) *norm = state->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) static int adv7842_core_init(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) struct adv7842_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) hdmi_write(sd, 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) (pdata->disable_pwrdnb ? 0x80 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) (pdata->disable_cable_det_rst ? 0x40 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) disable_input(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) * Disable I2C access to internal EDID ram from HDMI DDC ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) * Disable auto edid enable when leaving powerdown mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) rep_write_and_or(sd, 0x77, 0xd3, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) /* power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) io_write(sd, 0x15, 0x80); /* Power up pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /* video format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) pdata->insert_av_codes << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) pdata->replicate_av_codes << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) adv7842_setup_format(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) /* HDMI audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) /* Drive strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) io_write_and_or(sd, 0x14, 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) pdata->dr_str_data << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) pdata->dr_str_clk << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) pdata->dr_str_sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /* HDMI free run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) (pdata->hdmi_free_run_mode << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) /* SPD free run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) (pdata->sdp_free_run_cbar_en << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) (pdata->sdp_free_run_man_col_en << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) (pdata->sdp_free_run_auto << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) /* TODO from platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) /* todo, improve settings for sdram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) if (pdata->sd_ram_size >= 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (pdata->sd_ram_ddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) /* SDP setup for the AD eval board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) depends on memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) * Manual UG-214, rev 0 is bit confusing on this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) * but a '1' disables any signal if the Ram is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) select_input(sd, pdata->vid_std_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) enable_input(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) if (pdata->hpa_auto) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) /* HPA auto, HPA 0.5s after Edid set and Cable detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) hdmi_write(sd, 0x69, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /* HPA manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) hdmi_write(sd, 0x69, 0xa3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) /* HPA disable on port A and B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) io_write_and_or(sd, 0x20, 0xcf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) /* LLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) io_write(sd, 0x33, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) /* interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) io_write(sd, 0x40, 0xf2); /* Configure INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) adv7842_irq_enable(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) return v4l2_ctrl_handler_setup(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) * From ADV784x external Memory test.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) * Reset must just been performed before running test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) * Recommended to reset after test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) int pass = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) int fail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) int complete = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) io_write(sd, 0x01, 0x00); /* Program SDP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) io_write(sd, 0x15, 0xBA); /* Enable outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) io_write(sd, 0xFF, 0x04); /* Reset memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) u8 result = sdp_io_read(sd, 0xdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) if (result & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) complete++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) if (result & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) fail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) pass++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) "Ram Test: completed %d of %d: pass %d, fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) complete, i, pass, fail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if (!complete || fail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) struct adv7842_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) io_write(sd, 0xf1, pdata->i2c_sdp << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) io_write(sd, 0xf3, pdata->i2c_avlink << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) io_write(sd, 0xf4, pdata->i2c_cec << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) io_write(sd, 0xf8, pdata->i2c_afe << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) io_write(sd, 0xf9, pdata->i2c_repeater << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) io_write(sd, 0xfa, pdata->i2c_edid << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) io_write(sd, 0xfd, pdata->i2c_cp << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) io_write(sd, 0xfe, pdata->i2c_vdp << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) static int adv7842_command_ram_test(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) struct adv7842_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) v4l2_info(sd, "no sdram or no ddr sdram\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) main_reset(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) adv7842_rewrite_i2c_addresses(sd, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) /* run ram test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) ret = adv7842_ddr_ram_test(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) main_reset(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) adv7842_rewrite_i2c_addresses(sd, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) /* and re-init chip and state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) adv7842_core_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) disable_input(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) select_input(sd, state->vid_std_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) enable_input(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) edid_write_vga_segment(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) timings = state->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) adv7842_s_dv_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) case ADV7842_CMD_RAM_TEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) return adv7842_command_ram_test(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) static int adv7842_subscribe_event(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) static int adv7842_registered(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) err = cec_register_adapter(state->cec_adap, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) cec_delete_adapter(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) static void adv7842_unregistered(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) cec_unregister_adapter(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) .s_ctrl = adv7842_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) .g_volatile_ctrl = adv7842_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) static const struct v4l2_subdev_core_ops adv7842_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) .log_status = adv7842_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .ioctl = adv7842_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .interrupt_service_routine = adv7842_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) .subscribe_event = adv7842_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) .g_register = adv7842_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .s_register = adv7842_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) static const struct v4l2_subdev_video_ops adv7842_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) .g_std = adv7842_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) .s_std = adv7842_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) .s_routing = adv7842_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) .querystd = adv7842_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) .g_input_status = adv7842_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) .s_dv_timings = adv7842_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .g_dv_timings = adv7842_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .query_dv_timings = adv7842_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) .enum_mbus_code = adv7842_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) .get_fmt = adv7842_get_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) .set_fmt = adv7842_set_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) .get_edid = adv7842_get_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) .set_edid = adv7842_set_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .enum_dv_timings = adv7842_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) .dv_timings_cap = adv7842_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) static const struct v4l2_subdev_ops adv7842_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) .core = &adv7842_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) .video = &adv7842_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) .pad = &adv7842_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) .registered = adv7842_registered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) .unregistered = adv7842_unregistered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /* -------------------------- custom ctrls ---------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) .ops = &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) .name = "Analog Sampling Phase",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) .max = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) .ops = &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) .name = "Free Running Color, Manual",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .def = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .ops = &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) .name = "Free Running Color",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) .max = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) .step = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) static void adv7842_unregister_clients(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) i2c_unregister_device(state->i2c_avlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) i2c_unregister_device(state->i2c_cec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) i2c_unregister_device(state->i2c_infoframe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) i2c_unregister_device(state->i2c_sdp_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) i2c_unregister_device(state->i2c_sdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) i2c_unregister_device(state->i2c_afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) i2c_unregister_device(state->i2c_repeater);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) i2c_unregister_device(state->i2c_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) i2c_unregister_device(state->i2c_hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) i2c_unregister_device(state->i2c_cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) i2c_unregister_device(state->i2c_vdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) state->i2c_avlink = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) state->i2c_cec = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) state->i2c_infoframe = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) state->i2c_sdp_io = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) state->i2c_sdp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) state->i2c_afe = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) state->i2c_repeater = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) state->i2c_edid = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) state->i2c_hdmi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) state->i2c_cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) state->i2c_vdp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) u8 addr, u8 io_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) struct i2c_client *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) io_write(sd, io_reg, addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) if (addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) v4l2_err(sd, "no %s i2c addr configured\n", desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) if (IS_ERR(cp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) desc, addr, PTR_ERR(cp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) return cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) static int adv7842_register_clients(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) struct adv7842_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) if (!state->i2c_avlink ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) !state->i2c_cec ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) !state->i2c_infoframe ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) !state->i2c_sdp_io ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) !state->i2c_sdp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) !state->i2c_afe ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) !state->i2c_repeater ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) !state->i2c_edid ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) !state->i2c_hdmi ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) !state->i2c_cp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) !state->i2c_vdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) static int adv7842_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) struct adv7842_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) static const struct v4l2_dv_timings cea640x480 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) V4L2_DV_BT_CEA_640X480P59_94;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) struct adv7842_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) u16 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) client->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) v4l_err(client, "No platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) /* platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) state->pdata = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) state->timings = cea640x480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) sd->internal_ops = &adv7842_int_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) state->mode = pdata->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) state->restart_stdi_once = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) /* i2c access to adv7842? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) adv_smbus_read_byte_data_check(client, 0xeb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) if (rev != 0x2012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) adv_smbus_read_byte_data_check(client, 0xeb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) if (rev != 0x2012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) client->addr << 1, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) if (pdata->chip_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) main_reset(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) /* control handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) hdl = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) v4l2_ctrl_handler_init(hdl, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) /* add in ascending ID order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) V4L2_CID_CONTRAST, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) V4L2_CID_SATURATION, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) V4L2_CID_HUE, 0, 128, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) /* custom controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) &adv7842_ctrl_analog_sampling_phase, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) &adv7842_ctrl_free_run_color_manual, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) &adv7842_ctrl_free_run_color, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) state->rgb_quantization_range_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) 0, V4L2_DV_RGB_RANGE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) err = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) if (adv7842_s_detect_tx_5v_ctrl(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) if (adv7842_register_clients(sd) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) v4l2_err(sd, "failed to create all i2c clients\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) adv7842_delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) sd->entity.function = MEDIA_ENT_F_DV_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) state->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) err = media_entity_pads_init(&sd->entity, 1, &state->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) err = adv7842_core_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) goto err_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) state, dev_name(&client->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) err = PTR_ERR_OR_ZERO(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) goto err_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) err_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) err_work_queues:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) cancel_delayed_work(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) adv7842_unregister_clients(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) err_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) static int adv7842_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) struct adv7842_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) adv7842_irq_enable(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) adv7842_unregister_clients(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) static const struct i2c_device_id adv7842_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) { "adv7842", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) MODULE_DEVICE_TABLE(i2c, adv7842_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) static struct i2c_driver adv7842_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) .name = "adv7842",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) .probe = adv7842_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .remove = adv7842_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) .id_table = adv7842_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) module_i2c_driver(adv7842_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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