^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Analog Devices ADV748X 8 channel analog front end (AFE) receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * with standard definition processor (SDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "adv748x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * SDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADV748X_AFE_STD_AD_PAL_N_NTSC_J_SECAM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADV748X_AFE_STD_AD_PAL_N_NTSC_M_SECAM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADV748X_AFE_STD_NTSC_J 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADV748X_AFE_STD_NTSC_M 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADV748X_AFE_STD_PAL60 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADV748X_AFE_STD_NTSC_443 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADV748X_AFE_STD_PAL_BG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADV748X_AFE_STD_PAL_N 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADV748X_AFE_STD_PAL_M 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADV748X_AFE_STD_PAL_M_PED 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADV748X_AFE_STD_PAL_COMB_N 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADV748X_AFE_STD_PAL_COMB_N_PED 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADV748X_AFE_STD_PAL_SECAM 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADV748X_AFE_STD_PAL_SECAM_PED 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int adv748x_afe_read_ro_map(struct adv748x_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Select SDP Read-Only Main Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = sdp_write(state, ADV748X_SDP_MAP_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ADV748X_SDP_MAP_SEL_RO_MAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return sdp_read(state, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int adv748x_afe_status(struct adv748x_afe *afe, u32 *signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Read status from reg 0x10 of SDP RO Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) info = adv748x_afe_read_ro_map(state, ADV748X_SDP_RO_10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (info < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *signal = info & ADV748X_SDP_RO_10_IN_LOCK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0 : V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Standard not valid if there is no signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!(info & ADV748X_SDP_RO_10_IN_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) switch (info & 0x70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *std = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *std = V4L2_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *std = V4L2_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 0x30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *std = V4L2_STD_PAL_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *std = V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 0x50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *std = V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *std = V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 0x70:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *std = V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void adv748x_afe_fill_format(struct adv748x_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_mbus_framefmt *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) memset(fmt, 0, sizeof(*fmt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) fmt->field = V4L2_FIELD_ALTERNATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) fmt->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) fmt->height = afe->curr_norm & V4L2_STD_525_60 ? 480 : 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Field height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) fmt->height /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int adv748x_afe_std(v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (std == V4L2_STD_PAL_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ADV748X_AFE_STD_PAL60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (std == V4L2_STD_NTSC_443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ADV748X_AFE_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (std == V4L2_STD_PAL_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ADV748X_AFE_STD_PAL_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (std == V4L2_STD_PAL_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ADV748X_AFE_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (std == V4L2_STD_PAL_Nc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ADV748X_AFE_STD_PAL_COMB_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (std & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ADV748X_AFE_STD_NTSC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (std & V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ADV748X_AFE_STD_PAL_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (std & V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ADV748X_AFE_STD_PAL_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void adv748x_afe_set_video_standard(struct adv748x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int sdpstd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sdp_clrset(state, ADV748X_SDP_VID_SEL, ADV748X_SDP_VID_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (sdpstd & 0xf) << ADV748X_SDP_VID_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return sdp_write(state, ADV748X_SDP_INSEL, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int adv748x_afe_g_pixelaspect(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_fract *aspect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (afe->curr_norm & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) aspect->numerator = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) aspect->denominator = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) aspect->numerator = 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) aspect->denominator = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * v4l2_subdev_video_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int adv748x_afe_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *norm = afe->curr_norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int adv748x_afe_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int afe_std = adv748x_afe_std(std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (afe_std < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return afe_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) adv748x_afe_set_video_standard(state, afe_std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) afe->curr_norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int adv748x_afe_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int afe_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (afe->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Set auto detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) adv748x_afe_set_video_standard(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Read detected standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = adv748x_afe_status(afe, NULL, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) afe_std = adv748x_afe_std(afe->curr_norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (afe_std < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Restore original state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) adv748x_afe_set_video_standard(state, afe_std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int adv748x_afe_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *norm = V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int adv748x_afe_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = adv748x_afe_status(afe, status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int adv748x_afe_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 signal = V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = adv748x_afe_s_input(afe, afe->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = adv748x_tx_power(afe->tx, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) afe->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) adv748x_afe_status(afe, &signal, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (signal != V4L2_IN_ST_NO_SIGNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) adv_dbg(state, "Detected SDP signal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) adv_dbg(state, "Couldn't detect SDP video signal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct v4l2_subdev_video_ops adv748x_afe_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .g_std = adv748x_afe_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .s_std = adv748x_afe_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .querystd = adv748x_afe_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .g_tvnorms = adv748x_afe_g_tvnorms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .g_input_status = adv748x_afe_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .s_stream = adv748x_afe_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .g_pixelaspect = adv748x_afe_g_pixelaspect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * v4l2_subdev_pad_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int adv748x_afe_propagate_pixelrate(struct adv748x_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct v4l2_subdev *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tx = adv748x_get_remote_sd(&afe->pads[ADV748X_AFE_SOURCE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * The ADV748x ADC sampling frequency is twice the externally supplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * clock whose frequency is required to be 28.63636 MHz. It oversamples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * with a factor of 4 resulting in a pixel rate of 14.3180180 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return adv748x_csi2_set_pixelrate(tx, 14318180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int adv748x_afe_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int adv748x_afe_get_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct v4l2_subdev_format *sdformat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct adv748x_afe *afe = adv748x_sd_to_afe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct v4l2_mbus_framefmt *mbusformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* It makes no sense to get the format of the analog sink pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (sdformat->pad != ADV748X_AFE_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sdformat->format = *mbusformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) adv748x_afe_fill_format(afe, &sdformat->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) adv748x_afe_propagate_pixelrate(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int adv748x_afe_set_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct v4l2_subdev_format *sdformat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct v4l2_mbus_framefmt *mbusformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* It makes no sense to get the format of the analog sink pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (sdformat->pad != ADV748X_AFE_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return adv748x_afe_get_format(sd, cfg, sdformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mbusformat = v4l2_subdev_get_try_format(sd, cfg, sdformat->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *mbusformat = sdformat->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct v4l2_subdev_pad_ops adv748x_afe_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .enum_mbus_code = adv748x_afe_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .set_fmt = adv748x_afe_set_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .get_fmt = adv748x_afe_get_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * v4l2_subdev_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct v4l2_subdev_ops adv748x_afe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .video = &adv748x_afe_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pad = &adv748x_afe_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const char * const afe_ctrl_frp_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "Solid Blue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "Grey Ramp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "Cb Ramp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "Cr Ramp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "Boundary"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int adv748x_afe_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct adv748x_afe *afe = adv748x_ctrl_to_afe(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = sdp_write(state, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = sdp_write(state, ADV748X_SDP_BRI, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Hue is inverted according to HSL chart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = sdp_write(state, ADV748X_SDP_HUE, -ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = sdp_write(state, ADV748X_SDP_CON, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = sdp_write(state, ADV748X_SDP_SD_SAT_U, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = sdp_write(state, ADV748X_SDP_SD_SAT_V, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) enable = !!ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Enable/Disable Color bar test patterns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = sdp_clrset(state, ADV748X_SDP_DEF, ADV748X_SDP_DEF_VAL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = sdp_clrset(state, ADV748X_SDP_FRP, ADV748X_SDP_FRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) enable ? ctrl->val - 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct v4l2_ctrl_ops adv748x_afe_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .s_ctrl = adv748x_afe_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int adv748x_afe_init_controls(struct adv748x_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) v4l2_ctrl_handler_init(&afe->ctrl_hdl, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Use our mutex for the controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) afe->ctrl_hdl.lock = &state->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) V4L2_CID_BRIGHTNESS, ADV748X_SDP_BRI_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ADV748X_SDP_BRI_MAX, 1, ADV748X_SDP_BRI_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) V4L2_CID_CONTRAST, ADV748X_SDP_CON_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ADV748X_SDP_CON_MAX, 1, ADV748X_SDP_CON_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) V4L2_CID_SATURATION, ADV748X_SDP_SAT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ADV748X_SDP_SAT_MAX, 1, ADV748X_SDP_SAT_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) v4l2_ctrl_new_std(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) V4L2_CID_HUE, ADV748X_SDP_HUE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ADV748X_SDP_HUE_MAX, 1, ADV748X_SDP_HUE_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) v4l2_ctrl_new_std_menu_items(&afe->ctrl_hdl, &adv748x_afe_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ARRAY_SIZE(afe_ctrl_frp_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0, 0, afe_ctrl_frp_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) afe->sd.ctrl_handler = &afe->ctrl_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (afe->ctrl_hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) v4l2_ctrl_handler_free(&afe->ctrl_hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return afe->ctrl_hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return v4l2_ctrl_handler_setup(&afe->ctrl_hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int adv748x_afe_init(struct adv748x_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct adv748x_state *state = adv748x_afe_to_state(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) afe->input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) afe->streaming = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) afe->curr_norm = V4L2_STD_NTSC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) adv748x_subdev_init(&afe->sd, state, &adv748x_afe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MEDIA_ENT_F_ATV_DECODER, "afe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Identify the first connector found as a default input if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (i = ADV748X_PORT_AIN0; i <= ADV748X_PORT_AIN7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Inputs and ports are 1-indexed to match the data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (state->endpoints[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) afe->input = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) adv748x_afe_s_input(afe, afe->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) adv_dbg(state, "AFE Default input set to %d\n", afe->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Entity pads and sinks are 0-indexed to match the pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) for (i = ADV748X_AFE_SINK_AIN0; i <= ADV748X_AFE_SINK_AIN7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) afe->pads[i].flags = MEDIA_PAD_FL_SINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) afe->pads[ADV748X_AFE_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = media_entity_pads_init(&afe->sd.entity, ADV748X_AFE_NR_PADS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) afe->pads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = adv748x_afe_init_controls(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) media_entity_cleanup(&afe->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) void adv748x_afe_cleanup(struct adv748x_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) v4l2_device_unregister_subdev(&afe->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) media_entity_cleanup(&afe->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) v4l2_ctrl_handler_free(&afe->ctrl_hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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