^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ADV7343 encoder related structure and register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed .as is. WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef ADV7343_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ADV7343_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct adv7343_std_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 standard_val3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 fsc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) v4l2_std_id stdid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Register offset macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADV7343_POWER_MODE_REG (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADV7343_MODE_SELECT_REG (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADV7343_MODE_REG0 (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADV7343_DAC2_OUTPUT_LEVEL (0x0b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADV7343_SOFT_RESET (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADV7343_HD_MODE_REG1 (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADV7343_HD_MODE_REG2 (0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADV7343_HD_MODE_REG3 (0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADV7343_HD_MODE_REG4 (0x33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADV7343_HD_MODE_REG5 (0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADV7343_HD_MODE_REG6 (0x35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADV7343_HD_MODE_REG7 (0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADV7343_SD_MODE_REG1 (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADV7343_SD_MODE_REG2 (0x82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADV7343_SD_MODE_REG3 (0x83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADV7343_SD_MODE_REG4 (0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADV7343_SD_MODE_REG5 (0x86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADV7343_SD_MODE_REG6 (0x87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADV7343_SD_MODE_REG7 (0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADV7343_SD_MODE_REG8 (0x89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADV7343_FSC_REG0 (0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADV7343_FSC_REG1 (0x8D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADV7343_FSC_REG2 (0x8E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADV7343_FSC_REG3 (0x8F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADV7343_SD_CGMS_WSS0 (0x99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADV7343_SD_HUE_REG (0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADV7343_SD_BRIGHTNESS_WSS (0xA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Default values for the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADV7343_POWER_MODE_REG_DEFAULT (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADV7343_HD_MODE_REG1_DEFAULT (0x3C) /* Changed Default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 720p EAVSAV code*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADV7343_HD_MODE_REG2_DEFAULT (0x01) /* Changed Pixel data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADV7343_HD_MODE_REG3_DEFAULT (0x00) /* Color delay 0 clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADV7343_HD_MODE_REG4_DEFAULT (0xE8) /* Changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADV7343_HD_MODE_REG5_DEFAULT (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADV7343_HD_MODE_REG6_DEFAULT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADV7343_HD_MODE_REG7_DEFAULT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADV7343_SD_MODE_REG8_DEFAULT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADV7343_SOFT_RESET_DEFAULT (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADV7343_COMPOSITE_POWER_VALUE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADV7343_COMPONENT_POWER_VALUE (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADV7343_SVIDEO_POWER_VALUE (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADV7343_SD_HUE_REG_DEFAULT (127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADV7343_SD_CGMS_WSS0_DEFAULT (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADV7343_SD_MODE_REG1_DEFAULT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADV7343_SD_MODE_REG2_DEFAULT (0xC9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADV7343_SD_MODE_REG3_DEFAULT (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADV7343_SD_MODE_REG4_DEFAULT (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADV7343_SD_MODE_REG5_DEFAULT (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ADV7343_SD_MODE_REG6_DEFAULT (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADV7343_SD_MODE_REG7_DEFAULT (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADV7343_SD_MODE_REG8_DEFAULT (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Bit masks for Mode Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define INPUT_MODE_MASK (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SD_INPUT_MODE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HD_720P_INPUT_MODE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HD_1080I_INPUT_MODE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Bit masks for Mode Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEST_PATTERN_BLACK_BAR_EN (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define YUV_OUTPUT_SELECT (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RGB_OUTPUT_SELECT (0xDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Bit masks for DAC output levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DAC_OUTPUT_LEVEL_MASK (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Bit masks for soft reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SOFT_RESET (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Bit masks for HD Mode Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OUTPUT_STD_MASK (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OUTPUT_STD_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OUTPUT_STD_EIA0_2 (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OUTPUT_STD_EIA0_1 (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OUTPUT_STD_FULL (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EMBEDDED_SYNC (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EXTERNAL_SYNC (0xFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STD_MODE_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STD_MODE_MASK (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STD_MODE_720P (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define STD_MODE_720P_25 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STD_MODE_720P_30 (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STD_MODE_720P_50 (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STD_MODE_1080I (0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STD_MODE_1080I_25fps (0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define STD_MODE_1080P_24 (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define STD_MODE_1080P_25 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define STD_MODE_1080P_30 (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define STD_MODE_525P (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STD_MODE_625P (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Bit masks for SD Mode Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SD_STD_MASK (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SD_STD_NTSC (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SD_STD_PAL_BDGHI (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SD_STD_PAL_M (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SD_STD_PAL_N (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SD_LUMA_FLTR_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SD_LUMA_FLTR_SHIFT (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SD_CHROMA_FLTR_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SD_CHROMA_FLTR_SHIFT (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Bit masks for SD Mode Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SD_PBPR_SSAF_EN (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SD_PBPR_SSAF_DI (0xFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SD_DAC_1_DI (0xFD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SD_DAC_2_DI (0xFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SD_PEDESTAL_EN (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SD_PEDESTAL_DI (0xF7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SD_SQUARE_PIXEL_EN (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SD_SQUARE_PIXEL_DI (0xEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SD_PIXEL_DATA_VALID (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SD_ACTIVE_EDGE_EN (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SD_ACTIVE_EDGE_DI (0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Bit masks for HD Mode Register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HD_RGB_INPUT_EN (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HD_RGB_INPUT_DI (0xFD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HD_PBPR_SYNC_EN (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HD_PBPR_SYNC_DI (0xFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HD_DAC_SWAP_EN (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HD_DAC_SWAP_DI (0xF7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HD_GAMMA_CURVE_A (0xEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HD_GAMMA_CURVE_B (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HD_GAMMA_EN (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HD_GAMMA_DI (0xDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HD_ADPT_FLTR_MODEB (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HD_ADPT_FLTR_MODEA (0xBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HD_ADPT_FLTR_EN (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HD_ADPT_FLTR_DI (0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ADV7343_BRIGHTNESS_MAX (127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ADV7343_BRIGHTNESS_MIN (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ADV7343_BRIGHTNESS_DEF (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ADV7343_HUE_MAX (255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ADV7343_HUE_MIN (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ADV7343_HUE_DEF (127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ADV7343_GAIN_MAX (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ADV7343_GAIN_MIN (-64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ADV7343_GAIN_DEF (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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