^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * adv7343 - ADV7343 Video Encoder Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The encoder hardware does not support SECAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed .as is. WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/i2c/adv7343.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "adv7343_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_DESCRIPTION("ADV7343 video encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(debug, "Debug level 0-1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct adv7343_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct adv7343_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 reg00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 reg01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 reg02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 reg35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 reg80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 reg82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return container_of(sd, struct adv7343_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const u8 adv7343_init_reg_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 2^32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * FSC(reg) = FSC (HZ) * --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct adv7343_std_info stdinfo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* FSC(Hz) = 3,579,545.45 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* FSC(Hz) = 3,575,611.00 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* FSC(Hz) = 3,582,056.00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* FSC(Hz) = 4,433,618.75 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* FSC(Hz) = 4,433,618.75 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* FSC(Hz) = 4,433,618.75 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* FSC(Hz) = 4,433,618.75 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct adv7343_std_info *std_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int num_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) char *fsc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) std_info = (struct adv7343_std_info *)stdinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) num_std = ARRAY_SIZE(stdinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < num_std; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (std_info[i].stdid & std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (i == num_std) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "Invalid std or std is not supported: %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Set the standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = state->reg80 & (~(SD_STD_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val |= std_info[i].standard_val3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto setstd_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) state->reg80 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Configure the input mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = state->reg01 & (~((u8) INPUT_MODE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= SD_INPUT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto setstd_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) state->reg01 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Program the sub carrier frequency registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg = ADV7343_FSC_REG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) err = adv7343_write(sd, reg, *fsc_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto setstd_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = state->reg80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Filter settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) else if (std & ~V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto setstd_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) state->reg80 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) setstd_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) v4l2_err(sd, "Error setting std, write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (output_type > ADV7343_SVIDEO_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Invalid output type or output type not supported:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) output_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Enable Appropriate DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val = state->reg00 & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* configure default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!state->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (output_type == ADV7343_COMPOSITE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val |= ADV7343_COMPOSITE_POWER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else if (output_type == ADV7343_COMPONENT_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val |= ADV7343_COMPONENT_POWER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val |= ADV7343_SVIDEO_POWER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val = state->pdata->mode_config.sleep_mode << 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) state->pdata->mode_config.pll_control << 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) state->pdata->mode_config.dac[2] << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) state->pdata->mode_config.dac[1] << 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) state->pdata->mode_config.dac[0] << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) state->pdata->mode_config.dac[5] << 5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) state->pdata->mode_config.dac[4] << 6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) state->pdata->mode_config.dac[3] << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto setoutput_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) state->reg00 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Enable YUV output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = state->reg02 | YUV_OUTPUT_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) err = adv7343_write(sd, ADV7343_MODE_REG0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto setoutput_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) state->reg02 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) val = val | (state->pdata->sd_config.sd_dac_out[0] << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val = val | (state->pdata->sd_config.sd_dac_out[1] << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto setoutput_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) state->reg82 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto setoutput_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) state->reg35 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) setoutput_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) v4l2_err(sd, "Error setting output, write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int adv7343_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ((state->output == 1) ? "Component" : "S-Video"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .s_ctrl = adv7343_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct v4l2_subdev_core_ops adv7343_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .log_status = adv7343_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (state->std == std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err = adv7343_setstd(sd, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) state->std = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int adv7343_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (state->output == output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err = adv7343_setoutput(sd, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) state->output = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct v4l2_subdev_video_ops adv7343_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .s_std_output = adv7343_s_std_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .s_routing = adv7343_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct v4l2_subdev_ops adv7343_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .core = &adv7343_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .video = &adv7343_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int adv7343_initialize(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) err = adv7343_write(sd, adv7343_init_reg_val[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) adv7343_init_reg_val[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) v4l2_err(sd, "Error initializing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Configure for default video standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) err = adv7343_setoutput(sd, state->output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) v4l2_err(sd, "Error setting output during init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err = adv7343_setstd(sd, state->std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) v4l2_err(sd, "Error setting std during init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct adv7343_platform_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) adv7343_get_pdata(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct adv7343_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pdata->mode_config.sleep_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) of_property_read_bool(np, "adi,power-mode-sleep-mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pdata->mode_config.pll_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) of_property_read_bool(np, "adi,power-mode-pll-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) of_property_read_u32_array(np, "adi,dac-enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pdata->mode_config.dac, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) of_property_read_u32_array(np, "adi,sd-dac-enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pdata->sd_config.sd_dac_out, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int adv7343_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct adv7343_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Copy board specific information here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) state->pdata = adv7343_get_pdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) state->reg00 = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) state->reg01 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) state->reg02 = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) state->reg35 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) state->output = ADV7343_COMPOSITE_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) state->std = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) v4l2_ctrl_handler_init(&state->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ADV7343_BRIGHTNESS_MAX, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ADV7343_BRIGHTNESS_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) V4L2_CID_HUE, ADV7343_HUE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ADV7343_HUE_MAX, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ADV7343_HUE_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) V4L2_CID_GAIN, ADV7343_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ADV7343_GAIN_MAX, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ADV7343_GAIN_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) state->sd.ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (state->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) v4l2_ctrl_handler_setup(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) err = adv7343_initialize(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err = v4l2_async_register_subdev(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int adv7343_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct adv7343_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) v4l2_async_unregister_subdev(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct i2c_device_id adv7343_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {"adv7343", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_DEVICE_TABLE(i2c, adv7343_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct of_device_id adv7343_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {.compatible = "adi,adv7343", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_DEVICE_TABLE(of, adv7343_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct i2c_driver adv7343_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .of_match_table = of_match_ptr(adv7343_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = "adv7343",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .probe_new = adv7343_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .remove = adv7343_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .id_table = adv7343_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) module_i2c_driver(adv7343_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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