Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * adv7183 - Analog Devices ADV7183 video decoder registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ADV7183_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ADV7183_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ADV7183_IN_CTRL            0x00 /* Input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ADV7183_VD_SEL             0x01 /* Video selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ADV7183_OUT_CTRL           0x03 /* Output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ADV7183_EXT_OUT_CTRL       0x04 /* Extended output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ADV7183_AUTO_DET_EN        0x07 /* Autodetect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ADV7183_CONTRAST           0x08 /* Contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ADV7183_BRIGHTNESS         0x0A /* Brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ADV7183_HUE                0x0B /* Hue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADV7183_DEF_Y              0x0C /* Default value Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADV7183_DEF_C              0x0D /* Default value C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADV7183_ADI_CTRL           0x0E /* ADI control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADV7183_POW_MANAGE         0x0F /* Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADV7183_STATUS_1           0x10 /* Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADV7183_IDENT              0x11 /* Ident */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADV7183_STATUS_2           0x12 /* Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADV7183_STATUS_3           0x13 /* Status 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADV7183_ANAL_CLAMP_CTRL    0x14 /* Analog clamp control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADV7183_DIGI_CLAMP_CTRL_1  0x15 /* Digital clamp control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADV7183_SHAP_FILT_CTRL     0x17 /* Shaping filter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADV7183_SHAP_FILT_CTRL_2   0x18 /* Shaping filter control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADV7183_COMB_FILT_CTRL     0x19 /* Comb filter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADV7183_ADI_CTRL_2         0x1D /* ADI control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADV7183_PIX_DELAY_CTRL     0x27 /* Pixel delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADV7183_MISC_GAIN_CTRL     0x2B /* Misc gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADV7183_AGC_MODE_CTRL      0x2C /* AGC mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADV7183_CHRO_GAIN_CTRL_1   0x2D /* Chroma gain control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADV7183_CHRO_GAIN_CTRL_2   0x2E /* Chroma gain control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADV7183_LUMA_GAIN_CTRL_1   0x2F /* Luma gain control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADV7183_LUMA_GAIN_CTRL_2   0x30 /* Luma gain control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADV7183_VS_FIELD_CTRL_1    0x31 /* Vsync field control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADV7183_VS_FIELD_CTRL_2    0x32 /* Vsync field control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADV7183_VS_FIELD_CTRL_3    0x33 /* Vsync field control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADV7183_HS_POS_CTRL_1      0x34 /* Hsync position control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADV7183_HS_POS_CTRL_2      0x35 /* Hsync position control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADV7183_HS_POS_CTRL_3      0x36 /* Hsync position control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADV7183_POLARITY           0x37 /* Polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADV7183_NTSC_COMB_CTRL     0x38 /* NTSC comb control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADV7183_PAL_COMB_CTRL      0x39 /* PAL comb control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADV7183_ADC_CTRL           0x3A /* ADC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADV7183_MAN_WIN_CTRL       0x3D /* Manual window control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADV7183_RESAMPLE_CTRL      0x41 /* Resample control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADV7183_GEMSTAR_CTRL_1     0x48 /* Gemstar ctrl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADV7183_GEMSTAR_CTRL_2     0x49 /* Gemstar ctrl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADV7183_GEMSTAR_CTRL_3     0x4A /* Gemstar ctrl 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADV7183_GEMSTAR_CTRL_4     0x4B /* Gemstar ctrl 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADV7183_GEMSTAR_CTRL_5     0x4C /* Gemstar ctrl 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADV7183_CTI_DNR_CTRL_1     0x4D /* CTI DNR ctrl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADV7183_CTI_DNR_CTRL_2     0x4E /* CTI DNR ctrl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADV7183_CTI_DNR_CTRL_4     0x50 /* CTI DNR ctrl 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADV7183_LOCK_CNT           0x51 /* Lock count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADV7183_FREE_LINE_LEN      0x8F /* Free-Run line length 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADV7183_VBI_INFO           0x90 /* VBI info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADV7183_WSS_1              0x91 /* WSS 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADV7183_WSS_2              0x92 /* WSS 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADV7183_EDTV_1             0x93 /* EDTV 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADV7183_EDTV_2             0x94 /* EDTV 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADV7183_EDTV_3             0x95 /* EDTV 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADV7183_CGMS_1             0x96 /* CGMS 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADV7183_CGMS_2             0x97 /* CGMS 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADV7183_CGMS_3             0x98 /* CGMS 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADV7183_CCAP_1             0x99 /* CCAP 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADV7183_CCAP_2             0x9A /* CCAP 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADV7183_LETTERBOX_1        0x9B /* Letterbox 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADV7183_LETTERBOX_2        0x9C /* Letterbox 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADV7183_LETTERBOX_3        0x9D /* Letterbox 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADV7183_CRC_EN             0xB2 /* CRC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADV7183_ADC_SWITCH_1       0xC3 /* ADC switch 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADV7183_ADC_SWITCH_2       0xC4 /* ADC switch 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADV7183_LETTERBOX_CTRL_1   0xDC /* Letterbox control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADV7183_LETTERBOX_CTRL_2   0xDD /* Letterbox control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADV7183_SD_OFFSET_CB       0xE1 /* SD offset Cb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADV7183_SD_OFFSET_CR       0xE2 /* SD offset Cr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADV7183_SD_SATURATION_CB   0xE3 /* SD saturation Cb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADV7183_SD_SATURATION_CR   0xE4 /* SD saturation Cr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADV7183_NTSC_V_BEGIN       0xE5 /* NTSC V bit begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADV7183_NTSC_V_END         0xE6 /* NTSC V bit end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADV7183_NTSC_F_TOGGLE      0xE7 /* NTSC F bit toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ADV7183_PAL_V_BEGIN        0xE8 /* PAL V bit begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADV7183_PAL_V_END          0xE9 /* PAL V bit end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADV7183_PAL_F_TOGGLE       0xEA /* PAL F bit toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADV7183_DRIVE_STR          0xF4 /* Drive strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADV7183_IF_COMP_CTRL       0xF8 /* IF comp control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADV7183_VS_MODE_CTRL       0xF9 /* VS mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif