^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7183.c Analog Devices ADV7183 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/i2c/adv7183.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "adv7183_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct adv7183 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) v4l2_std_id std; /* Current set standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned reset_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned oe_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct v4l2_mbus_framefmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* EXAMPLES USING 27 MHz CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Mode 1 CVBS Input (Composite Video on AIN5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const unsigned char adv7183_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ADV7183_IN_CTRL, 0x04, /* CVBS input on AIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ADV7183_SHAP_FILT_CTRL, 0x41, /* Set CSFM to SH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ADV7183_ADC_CTRL, 0x16, /* Power down ADC 1 and ADC 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ADV7183_CTI_DNR_CTRL_4, 0x04, /* Set DNR threshold to 4 for flat response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ADI recommended programming sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ADV7183_ADI_CTRL, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ADV7183_CTI_DNR_CTRL_4, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x52, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0x58, 0xED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x77, 0xC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x7C, 0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x7D, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0xD0, 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0xD5, 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0xD7, 0xEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ADV7183_SD_SATURATION_CR, 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADV7183_PAL_V_END, 0x3E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADV7183_PAL_F_TOGGLE, 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ADV7183_ADI_CTRL, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline struct adv7183 *to_adv7183(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return container_of(sd, struct adv7183, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int adv7183_writeregs(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const unsigned char *regs, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned char reg, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (num & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) v4l2_err(sd, "invalid regs array\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while (cnt < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg = *regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data = *regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cnt += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) adv7183_write(sd, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int adv7183_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) adv7183_read(sd, ADV7183_IN_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) adv7183_read(sd, ADV7183_VD_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) adv7183_read(sd, ADV7183_OUT_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) adv7183_read(sd, ADV7183_AUTO_DET_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) adv7183_read(sd, ADV7183_CONTRAST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) adv7183_read(sd, ADV7183_BRIGHTNESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) adv7183_read(sd, ADV7183_HUE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) adv7183_read(sd, ADV7183_DEF_Y));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) adv7183_read(sd, ADV7183_DEF_C));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) adv7183_read(sd, ADV7183_ADI_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) adv7183_read(sd, ADV7183_POW_MANAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) adv7183_read(sd, ADV7183_STATUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) adv7183_read(sd, ADV7183_STATUS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) adv7183_read(sd, ADV7183_STATUS_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) adv7183_read(sd, ADV7183_IDENT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) adv7183_read(sd, ADV7183_ADI_CTRL_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) adv7183_read(sd, ADV7183_POLARITY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) adv7183_read(sd, ADV7183_ADC_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) adv7183_read(sd, ADV7183_SD_OFFSET_CB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) adv7183_read(sd, ADV7183_SD_OFFSET_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) adv7183_read(sd, ADV7183_SD_SATURATION_CB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) adv7183_read(sd, ADV7183_SD_SATURATION_CR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) adv7183_read(sd, ADV7183_DRIVE_STR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int adv7183_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *std = decoder->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (std == V4L2_STD_PAL_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) reg |= 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) else if (std == V4L2_STD_NTSC_443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg |= 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else if (std == V4L2_STD_PAL_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg |= 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else if (std == V4L2_STD_PAL_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg |= 0xA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else if (std == V4L2_STD_PAL_Nc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg |= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else if (std & V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else if (std & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg |= 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else if (std & V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg |= 0xE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) adv7183_write(sd, ADV7183_IN_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) decoder->std = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) adv7183_write(sd, ADV7183_POW_MANAGE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* wait 5ms before any further i2c writes are performed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int adv7183_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if ((input > ADV7183_COMPONENT1) || (output > ADV7183_16BIT_OUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (input != decoder->input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) decoder->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case ADV7183_COMPOSITE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case ADV7183_COMPOSITE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case ADV7183_COMPOSITE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case ADV7183_COMPOSITE4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case ADV7183_COMPOSITE5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg |= 0x5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case ADV7183_COMPOSITE6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg |= 0xB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case ADV7183_COMPOSITE7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reg |= 0xC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case ADV7183_COMPOSITE8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg |= 0xD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case ADV7183_COMPOSITE9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg |= 0xE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case ADV7183_COMPOSITE10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reg |= 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case ADV7183_SVIDEO0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reg |= 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case ADV7183_SVIDEO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) reg |= 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case ADV7183_SVIDEO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg |= 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case ADV7183_COMPONENT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) reg |= 0x9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case ADV7183_COMPONENT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg |= 0xA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) adv7183_write(sd, ADV7183_IN_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (output != decoder->output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) decoder->output = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) switch (output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case ADV7183_16BIT_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg |= 0x9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reg |= 0xC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) adv7183_write(sd, ADV7183_OUT_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = 127 - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) adv7183_write(sd, ADV7183_BRIGHTNESS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) adv7183_write(sd, ADV7183_CONTRAST, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int adv7183_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* enable autodetection block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) adv7183_write(sd, ADV7183_IN_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* wait autodetection switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* get autodetection result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg = adv7183_read(sd, ADV7183_STATUS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) switch ((reg >> 0x4) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *std &= V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *std &= V4L2_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *std &= V4L2_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *std &= V4L2_STD_PAL_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *std &= V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *std &= V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *std &= V4L2_STD_PAL_Nc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *std &= V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* after std detection, write back user set std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) adv7183_s_std(sd, decoder->std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int adv7183_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *status = V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg = adv7183_read(sd, ADV7183_STATUS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (reg & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (code->pad || code->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int adv7183_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct v4l2_mbus_framefmt *fmt = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (decoder->std & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) fmt->field = V4L2_FIELD_SEQ_TB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fmt->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fmt->height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fmt->field = V4L2_FIELD_SEQ_BT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) fmt->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) fmt->height = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) decoder->fmt = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cfg->try_fmt = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int adv7183_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) format->format = decoder->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct adv7183 *decoder = to_adv7183(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) gpio_set_value(decoder->oe_pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpio_set_value(decoder->oe_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reg->val = adv7183_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .s_ctrl = adv7183_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct v4l2_subdev_core_ops adv7183_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .log_status = adv7183_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .reset = adv7183_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .g_register = adv7183_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .s_register = adv7183_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct v4l2_subdev_video_ops adv7183_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .g_std = adv7183_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .s_std = adv7183_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .s_routing = adv7183_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .querystd = adv7183_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .g_input_status = adv7183_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .s_stream = adv7183_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .enum_mbus_code = adv7183_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .get_fmt = adv7183_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .set_fmt = adv7183_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct v4l2_subdev_ops adv7183_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .core = &adv7183_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .video = &adv7183_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .pad = &adv7183_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int adv7183_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct adv7183 *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct v4l2_subdev_format fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const unsigned *pin_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pin_array = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (pin_array == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (decoder == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) decoder->reset_pin = pin_array[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) decoder->oe_pin = pin_array[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GPIOF_OUT_INIT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "ADV7183 Output Enable")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) sd = &decoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) hdl = &decoder->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* hook the control handler into the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* v4l2 doesn't support an autodetect standard, pick PAL as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) decoder->std = V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) decoder->input = ADV7183_COMPOSITE4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) decoder->output = ADV7183_8BIT_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* reset pulse width at least 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) gpio_set_value(decoder->reset_pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* wait 5ms before any further i2c writes are performed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) adv7183_s_std(sd, decoder->std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) fmt.format.width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) fmt.format.height = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) adv7183_set_fmt(sd, NULL, &fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* initialize the hardware to the default control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = v4l2_ctrl_handler_setup(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int adv7183_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct i2c_device_id adv7183_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {"adv7183", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_DEVICE_TABLE(i2c, adv7183_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static struct i2c_driver adv7183_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = "adv7183",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .probe = adv7183_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .remove = adv7183_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .id_table = adv7183_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) module_i2c_driver(adv7183_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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