Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * adv7181 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_CHIP_ID			0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CHIP_ID				0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_SC_CTRL_MODE		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define     SC_CTRL_MODE_STANDBY	0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define     SC_CTRL_MODE_STREAMING	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_NULL			0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ADV7181_XVCLK_FREQ		24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ADV7181_LANES			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ADV7181_BITS_PER_SAMPLE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ADV7181_SKIP_TOP		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const char * const adv7181_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	"dvdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"dvddio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ADV7181_NUM_SUPPLIES ARRAY_SIZE(adv7181_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct adv7181_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) struct adv7181 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct clk		*xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct gpio_desc	*reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct regulator_bulk_data supplies[ADV7181_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	bool			streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct mutex		mutex; /* lock to serialize v4l2 callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct v4l2_subdev	subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct media_pad	pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int			skip_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	const struct adv7181_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define to_adv7181(sd) container_of(sd, struct adv7181, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* PLL settings bases on 28M xvclk, resolution 720x480 30fps*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct regval adv7181_cvbs_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{0x00, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{0x04, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{0x17, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{0x1D, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{0x31, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{0x3A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{0x3B, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{0x3D, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{0x3E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{0x3F, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{0x86, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{0xF3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{0xF9, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{0x0E, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{0x52, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{0x54, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{0x7F, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{0x81, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{0x90, 0xC9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{0x91, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{0x92, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{0x93, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{0x94, 0xD5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{0xB1, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{0xB6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{0xC0, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{0xCF, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{0xD0, 0x4E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{0xD1, 0xB9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{0xD6, 0xDD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{0xD7, 0xE2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{0xE5, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{0xF6, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{0x0E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{0x03, 0x4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{REG_NULL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct adv7181_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.reg_list = adv7181_cvbs_30fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int adv7181_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		dev_err(&client->dev, "write reg error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int adv7181_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			       const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		ret = adv7181_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline u8 adv7181_read_reg(struct i2c_client *client, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void adv7181_fill_fmt(const struct adv7181_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			     struct v4l2_mbus_framefmt *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	fmt->width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	fmt->height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int adv7181_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			   struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* only one mode supported for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	adv7181_fill_fmt(adv7181->cur_mode, mbus_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int adv7181_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			   struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			   struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	adv7181_fill_fmt(adv7181->cur_mode, mbus_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int adv7181_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				  struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				  struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (code->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int adv7181_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				    struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				    struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 index = fse->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	fse->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	fse->min_width  = supported_modes[index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	fse->max_width  = supported_modes[index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	fse->max_height = supported_modes[index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	fse->min_height = supported_modes[index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int adv7181_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	*lines = adv7181->skip_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int adv7181_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Only NTSC now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	*std = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int __adv7181_power_on(struct adv7181 *adv7181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct device *dev = &adv7181->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (!IS_ERR(adv7181->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ret = clk_prepare_enable(adv7181->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	gpiod_set_value_cansleep(adv7181->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = regulator_bulk_enable(ADV7181_NUM_SUPPLIES, adv7181->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	gpiod_set_value_cansleep(adv7181->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (!IS_ERR(adv7181->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		clk_disable_unprepare(adv7181->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __adv7181_power_off(struct adv7181 *adv7181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (!IS_ERR(adv7181->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		clk_disable_unprepare(adv7181->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	gpiod_set_value_cansleep(adv7181->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	regulator_bulk_disable(ADV7181_NUM_SUPPLIES, adv7181->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int adv7181_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct i2c_client *client = adv7181->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mutex_lock(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (on == adv7181->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		ret = pm_runtime_get_sync(&adv7181->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = adv7181_write_array(adv7181->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					  adv7181->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		ret = adv7181_write_reg(client, REG_SC_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 					SC_CTRL_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		adv7181_write_reg(client, REG_SC_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				  SC_CTRL_MODE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	adv7181->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mutex_unlock(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int adv7181_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct v4l2_mbus_framefmt *try_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	mutex_lock(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	try_fmt = v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	adv7181_fill_fmt(&supported_modes[0], try_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mutex_unlock(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int adv7181_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return __adv7181_power_on(adv7181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int adv7181_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	__adv7181_power_off(adv7181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct dev_pm_ops adv7181_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	SET_RUNTIME_PM_OPS(adv7181_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			   adv7181_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct v4l2_subdev_video_ops adv7181_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.s_stream = adv7181_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.querystd = adv7181_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct v4l2_subdev_pad_ops adv7181_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.enum_mbus_code = adv7181_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.enum_frame_size = adv7181_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.get_fmt = adv7181_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.set_fmt = adv7181_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct v4l2_subdev_sensor_ops adv7181_sensor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.g_skip_top_lines	= adv7181_g_skip_top_lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct v4l2_subdev_ops adv7181_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.video	= &adv7181_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.pad	= &adv7181_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	.sensor = &adv7181_sensor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct v4l2_subdev_internal_ops adv7181_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.open = adv7181_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int adv7181_check_sensor_id(struct adv7181 *adv7181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 				  struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct device *dev = &adv7181->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	id = adv7181_read_reg(client, REG_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		dev_err(dev, "Wrong camera sensor id(%04x)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	dev_info(dev, "Detected ADV7181 (%04x) sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int adv7181_configure_regulators(struct adv7181 *adv7181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	for (i = 0; i < ADV7181_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		adv7181->supplies[i].supply = adv7181_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	return devm_regulator_bulk_get(&adv7181->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 				       ADV7181_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 				       adv7181->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int adv7181_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct adv7181 *adv7181;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	adv7181 = devm_kzalloc(dev, sizeof(*adv7181), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (!adv7181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	adv7181->skip_top = ADV7181_SKIP_TOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	adv7181->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	adv7181->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	adv7181->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	if (!IS_ERR(adv7181->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		ret = clk_set_rate(adv7181->xvclk, ADV7181_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		if (clk_get_rate(adv7181->xvclk) != ADV7181_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			dev_warn(dev, "xvclk mismatched, it requires 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	adv7181->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	if (IS_ERR(adv7181->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		dev_err(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	ret = adv7181_configure_regulators(adv7181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	mutex_init(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	v4l2_i2c_subdev_init(&adv7181->subdev, client, &adv7181_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	ret = __adv7181_power_on(adv7181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	ret = adv7181_check_sensor_id(adv7181, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	adv7181->subdev.internal_ops = &adv7181_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	adv7181->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	adv7181->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	adv7181->subdev.entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	ret = media_entity_init(&adv7181->subdev.entity, 1, &adv7181->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	ret = v4l2_async_register_subdev(&adv7181->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	media_entity_cleanup(&adv7181->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	__adv7181_power_off(adv7181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	mutex_destroy(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int adv7181_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	struct adv7181 *adv7181 = to_adv7181(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	mutex_destroy(&adv7181->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		__adv7181_power_off(adv7181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct i2c_device_id adv7181_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	{"adv7181", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct of_device_id adv7181_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	{ .compatible = "adi,adv7181" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_DEVICE_TABLE(of, adv7181_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct i2c_driver adv7181_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		.name = "adv7181",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		.pm = &adv7181_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		.of_match_table = adv7181_of_match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	.probe		= adv7181_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	.remove		= adv7181_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	.id_table	= adv7181_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) module_i2c_driver(adv7181_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_DESCRIPTION("adv7181 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_LICENSE("GPL v2");