^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7180.c Analog Devices ADV7180 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADV7180_STD_NTSC_J 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADV7180_STD_NTSC_M 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADV7180_STD_PAL60 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADV7180_STD_NTSC_443 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADV7180_STD_PAL_BG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADV7180_STD_PAL_N 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADV7180_STD_PAL_M 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADV7180_STD_PAL_M_PED 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADV7180_STD_PAL_COMB_N 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADV7180_STD_PAL_COMB_N_PED 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADV7180_STD_PAL_SECAM 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADV7180_STD_PAL_SECAM_PED 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADV7180_REG_INPUT_CONTROL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADV7182_REG_INPUT_VIDSEL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADV7180_REG_OUTPUT_CONTROL 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADV7180_AUTODETECT_DEFAULT 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADV7180_REG_CON 0x0008 /*Unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADV7180_CON_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADV7180_CON_DEF 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADV7180_CON_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Brightness*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADV7180_REG_BRI 0x000a /*Signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADV7180_BRI_MIN -128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADV7180_BRI_DEF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADV7180_BRI_MAX 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Hue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADV7180_HUE_MIN -127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADV7180_HUE_DEF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADV7180_HUE_MAX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADV7180_REG_CTRL 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADV7180_CTRL_IRQ_SPACE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADV7180_REG_PWR_MAN 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADV7180_PWR_MAN_ON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADV7180_PWR_MAN_OFF 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADV7180_PWR_MAN_RES 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADV7180_REG_STATUS1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADV7180_STATUS1_IN_LOCK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADV7180_STATUS1_AUTOD_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADV7180_STATUS1_AUTOD_SECAM 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ADV7180_REG_IDENT 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADV7180_ID_7180 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADV7180_REG_STATUS3 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADV7180_REG_CTRL_2 0x001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ADV7180_REG_LOCK_CNT 0x0051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ADV7180_REG_CVBS_TRIM 0x0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ADV7180_REG_CLAMP_ADJ 0x005a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ADV7180_REG_RES_CIR 0x005f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ADV7180_REG_DIFF_MODE 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ADV7180_REG_ICONF1 0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ADV7180_ICONF1_ACTIVE_LOW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ADV7180_ICONF1_PSYNC_ONLY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADV7180_SAT_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ADV7180_SAT_DEF 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ADV7180_SAT_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ADV7180_IRQ1_LOCK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADV7180_IRQ1_UNLOCK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ADV7180_REG_ISR1 0x2042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ADV7180_REG_ICR1 0x2043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ADV7180_REG_IMR1 0x2044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ADV7180_REG_IMR2 0x2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADV7180_IRQ3_AD_CHANGE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ADV7180_REG_ISR3 0x204A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ADV7180_REG_ICR3 0x204B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADV7180_REG_IMR3 0x204C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ADV7180_REG_IMR4 0x2050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ADV7180_REG_ACE_CTRL1 0x4080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ADV7180_REG_ACE_CTRL5 0x4084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ADV7180_REG_FLCONTROL 0x40e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ADV7180_FLCONTROL_FL_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ADV7180_REG_RST_CLAMP 0x809c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ADV7180_REG_AGC_ADJ1 0x80b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ADV7180_REG_AGC_ADJ2 0x80c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ADV7180_CSI_REG_PWRDN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ADV7180_CSI_PWRDN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ADV7180_INPUT_CVBS_AIN1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ADV7180_INPUT_CVBS_AIN2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ADV7180_INPUT_CVBS_AIN3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ADV7180_INPUT_CVBS_AIN4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ADV7180_INPUT_CVBS_AIN5 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ADV7180_INPUT_CVBS_AIN6 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ADV7182_INPUT_CVBS_AIN1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ADV7182_INPUT_CVBS_AIN2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ADV7182_INPUT_CVBS_AIN3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ADV7182_INPUT_CVBS_AIN4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ADV7182_INPUT_CVBS_AIN5 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ADV7182_INPUT_CVBS_AIN6 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ADV7182_INPUT_CVBS_AIN7 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ADV7182_INPUT_CVBS_AIN8 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Initial number of frames to skip to avoid possible garbage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ADV7180_NUM_OF_SKIP_FRAMES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct adv7180_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ADV7180_FLAG_RESET_POWERED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ADV7180_FLAG_V2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ADV7180_FLAG_I2P BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct adv7180_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int valid_input_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int (*set_std)(struct adv7180_state *st, unsigned int std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int (*select_input)(struct adv7180_state *st, unsigned int input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int (*init)(struct adv7180_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct adv7180_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct v4l2_ctrl_handler ctrl_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mutex mutex; /* mutual excl. when accessing chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) v4l2_std_id curr_norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bool powered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int register_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct i2c_client *csi_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct i2c_client *vpp_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct adv7180_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) enum v4l2_field field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct adv7180_state, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ctrl_hdl)->sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (state->register_page != page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) state->register_page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int adv7180_write(struct adv7180_state *state, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) lockdep_assert_held(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) adv7180_select_page(state, reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int adv7180_read(struct adv7180_state *state, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) lockdep_assert_held(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) adv7180_select_page(state, reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return i2c_smbus_read_byte_data(state->client, reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return i2c_smbus_write_byte_data(state->csi_client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int adv7180_set_video_standard(struct adv7180_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return state->chip_info->set_std(state, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* in case V4L2_IN_ST_NO_SIGNAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!(status1 & ADV7180_STATUS1_IN_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case ADV7180_STATUS1_AUTOD_NTSM_M_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case ADV7180_STATUS1_AUTOD_NTSC_4_43:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return V4L2_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case ADV7180_STATUS1_AUTOD_PAL_M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return V4L2_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case ADV7180_STATUS1_AUTOD_PAL_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return V4L2_STD_PAL_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case ADV7180_STATUS1_AUTOD_PAL_B_G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case ADV7180_STATUS1_AUTOD_SECAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case ADV7180_STATUS1_AUTOD_PAL_COMB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case ADV7180_STATUS1_AUTOD_SECAM_525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int v4l2_std_to_adv7180(v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (std == V4L2_STD_PAL_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ADV7180_STD_PAL60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (std == V4L2_STD_NTSC_443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ADV7180_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (std == V4L2_STD_PAL_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ADV7180_STD_PAL_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (std == V4L2_STD_PAL_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ADV7180_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (std == V4L2_STD_PAL_Nc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ADV7180_STD_PAL_COMB_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (std & V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ADV7180_STD_PAL_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (std & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ADV7180_STD_NTSC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (std & V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ADV7180_STD_PAL_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static u32 adv7180_status_to_v4l2(u8 status1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!(status1 & ADV7180_STATUS1_IN_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int __adv7180_status(struct adv7180_state *state, u32 *status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (status1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *status = adv7180_status_to_v4l2(status1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *std = adv7180_std_to_v4l2(status1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return container_of(sd, struct adv7180_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int err = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (state->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err = adv7180_set_video_standard(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __adv7180_status(state, NULL, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) err = v4l2_std_to_adv7180(state->curr_norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) err = adv7180_set_video_standard(state, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int ret = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = state->chip_info->select_input(state, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) state->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = __adv7180_status(state, status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int adv7180_program_std(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = v4l2_std_to_adv7180(state->curr_norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = adv7180_set_video_standard(state, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int ret = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Make sure we can support this std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = v4l2_std_to_adv7180(std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) state->curr_norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = adv7180_program_std(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *norm = state->curr_norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (state->curr_norm & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fi->interval.numerator = 1001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) fi->interval.denominator = 30000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fi->interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fi->interval.denominator = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!state->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) gpiod_set_value_cansleep(state->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) gpiod_set_value_cansleep(state->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int adv7180_set_power(struct adv7180_state *state, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) val = ADV7180_PWR_MAN_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = ADV7180_PWR_MAN_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) adv7180_csi_write(state, 0xDE, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) adv7180_csi_write(state, 0xD2, 0xF7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) adv7180_csi_write(state, 0xD8, 0x65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) adv7180_csi_write(state, 0xE0, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) adv7180_csi_write(state, 0x2C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (state->field == V4L2_FIELD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) adv7180_csi_write(state, 0x1D, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) adv7180_csi_write(state, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) adv7180_csi_write(state, 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int adv7180_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = adv7180_set_power(state, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) state->powered = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = adv7180_write(state, ADV7180_REG_BRI, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*Hue is inverted according to HSL chart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = adv7180_write(state, ADV7180_REG_HUE, -val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = adv7180_write(state, ADV7180_REG_CON, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *Let's not confuse the user, everybody understands saturation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case V4L2_CID_ADV_FAST_SWITCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* ADI required write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) adv7180_write(state, 0x80d9, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) adv7180_write(state, ADV7180_REG_FLCONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ADV7180_FLCONTROL_FL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* ADI required write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) adv7180_write(state, 0x80d9, 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .s_ctrl = adv7180_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .ops = &adv7180_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .id = V4L2_CID_ADV_FAST_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "Fast Switching",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int adv7180_init_controls(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) V4L2_CID_CONTRAST, ADV7180_CON_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) V4L2_CID_SATURATION, ADV7180_SAT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) V4L2_CID_HUE, ADV7180_HUE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) state->sd.ctrl_handler = &state->ctrl_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (state->ctrl_hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int err = state->ctrl_hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) v4l2_ctrl_handler_free(&state->ctrl_hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) v4l2_ctrl_handler_setup(&state->ctrl_hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void adv7180_exit_controls(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) v4l2_ctrl_handler_free(&state->ctrl_hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct v4l2_mbus_framefmt *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fmt->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (state->field == V4L2_FIELD_ALTERNATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fmt->height /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int adv7180_set_field_mode(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (state->field == V4L2_FIELD_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) adv7180_csi_write(state, 0x01, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) adv7180_csi_write(state, 0x02, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) adv7180_csi_write(state, 0x03, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) adv7180_csi_write(state, 0x04, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) adv7180_csi_write(state, 0x05, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) adv7180_csi_write(state, 0x06, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) adv7180_csi_write(state, 0x07, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) adv7180_csi_write(state, 0x08, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) adv7180_vpp_write(state, 0xa3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) adv7180_vpp_write(state, 0x5b, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) adv7180_vpp_write(state, 0x55, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) adv7180_csi_write(state, 0x01, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) adv7180_csi_write(state, 0x02, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) adv7180_csi_write(state, 0x03, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) adv7180_csi_write(state, 0x04, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) adv7180_csi_write(state, 0x05, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) adv7180_csi_write(state, 0x06, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) adv7180_csi_write(state, 0x07, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) adv7180_csi_write(state, 0x08, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) adv7180_vpp_write(state, 0xa3, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) adv7180_vpp_write(state, 0x5b, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) adv7180_vpp_write(state, 0x55, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int adv7180_get_pad_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) adv7180_mbus_fmt(sd, &format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) format->format.field = state->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int adv7180_set_pad_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct v4l2_mbus_framefmt *framefmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) switch (format->format.field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case V4L2_FIELD_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (state->chip_info->flags & ADV7180_FLAG_I2P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) format->format.field = V4L2_FIELD_ALTERNATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = adv7180_mbus_fmt(sd, &format->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (state->field != format->format.field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) state->field = format->format.field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) adv7180_set_power(state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) adv7180_set_field_mode(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) adv7180_set_power(state, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) *framefmt = format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int adv7180_init_cfg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct v4l2_subdev_format fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .which = cfg ? V4L2_SUBDEV_FORMAT_TRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) : V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return adv7180_set_pad_format(sd, cfg, &fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) cfg->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) cfg->flags = V4L2_MBUS_CSI2_1_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * The ADV7180 sensor supports BT.601/656 output modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * The BT.656 is default and not yet configurable by s/w.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) V4L2_MBUS_DATA_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) cfg->type = V4L2_MBUS_BT656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) *frames = ADV7180_NUM_OF_SKIP_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (state->curr_norm & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) aspect->numerator = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) aspect->denominator = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) aspect->numerator = 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) aspect->denominator = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *norm = V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* It's always safe to stop streaming, no need to take the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) state->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Must wait until querystd released the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = mutex_lock_interruptible(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) state->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int adv7180_subscribe_event(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct v4l2_subdev_video_ops adv7180_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .s_std = adv7180_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .g_std = adv7180_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .g_frame_interval = adv7180_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .querystd = adv7180_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .g_input_status = adv7180_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .s_routing = adv7180_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .g_pixelaspect = adv7180_g_pixelaspect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .g_tvnorms = adv7180_g_tvnorms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .s_stream = adv7180_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct v4l2_subdev_core_ops adv7180_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .s_power = adv7180_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .subscribe_event = adv7180_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .init_cfg = adv7180_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .enum_mbus_code = adv7180_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .set_fmt = adv7180_set_pad_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .get_fmt = adv7180_get_pad_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .get_mbus_config = adv7180_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .g_skip_frames = adv7180_get_skip_frames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const struct v4l2_subdev_ops adv7180_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .core = &adv7180_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .video = &adv7180_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .pad = &adv7180_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .sensor = &adv7180_sensor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static irqreturn_t adv7180_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct adv7180_state *state = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u8 isr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) isr3 = adv7180_read(state, ADV7180_REG_ISR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) adv7180_write(state, ADV7180_REG_ICR3, isr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct v4l2_event src_ch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) v4l2_subdev_notify_event(&state->sd, &src_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int adv7180_init(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* ITU-R BT.656-4 compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Manually set V bit end position in NTSC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) (std << 4) | state->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret |= input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int adv7182_init(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (state->chip_info->flags & ADV7180_FLAG_I2P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (state->chip_info->flags & ADV7180_FLAG_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* ADI recommended writes for improved video quality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) adv7180_write(state, 0x0080, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) adv7180_write(state, 0x0081, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) adv7180_write(state, 0x0082, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* ADI required writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (state->chip_info->flags & ADV7180_FLAG_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) adv7180_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) adv7180_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) adv7180_write(state, 0x0013, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) enum adv7182_input_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ADV7182_INPUT_TYPE_CVBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ADV7182_INPUT_TYPE_DIFF_CVBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ADV7182_INPUT_TYPE_SVIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ADV7182_INPUT_TYPE_YPBPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case ADV7182_INPUT_CVBS_AIN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) case ADV7182_INPUT_CVBS_AIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case ADV7182_INPUT_CVBS_AIN3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case ADV7182_INPUT_CVBS_AIN4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case ADV7182_INPUT_CVBS_AIN5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case ADV7182_INPUT_CVBS_AIN6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) case ADV7182_INPUT_CVBS_AIN7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) case ADV7182_INPUT_CVBS_AIN8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return ADV7182_INPUT_TYPE_CVBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return ADV7182_INPUT_TYPE_SVIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ADV7182_INPUT_TYPE_YPBPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ADV7182_INPUT_TYPE_DIFF_CVBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) default: /* Will never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static unsigned int adv7182_lbias_settings[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static unsigned int adv7280_lbias_settings[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) enum adv7182_input_type input_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unsigned int *lbias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Reset clamp circuitry - ADI recommended writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) input_type = adv7182_get_input_type(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) switch (input_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) case ADV7182_INPUT_TYPE_CVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) case ADV7182_INPUT_TYPE_DIFF_CVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* ADI recommends to use the SH1 filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (state->chip_info->flags & ADV7180_FLAG_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) lbias = adv7280_lbias_settings[input_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) lbias = adv7182_lbias_settings[input_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* ADI required writes to make differential CVBS work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const struct adv7180_chip_info adv7180_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .flags = ADV7180_FLAG_RESET_POWERED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * all inputs and let the card driver take care of validation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) BIT(ADV7180_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) BIT(ADV7180_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) BIT(ADV7180_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) BIT(ADV7180_INPUT_CVBS_AIN5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) BIT(ADV7180_INPUT_CVBS_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .init = adv7180_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .set_std = adv7180_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .select_input = adv7180_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const struct adv7180_chip_info adv7182_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) BIT(ADV7182_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) BIT(ADV7182_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const struct adv7180_chip_info adv7280_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) BIT(ADV7182_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) BIT(ADV7182_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct adv7180_chip_info adv7280_m_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) BIT(ADV7182_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) BIT(ADV7182_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) BIT(ADV7182_INPUT_CVBS_AIN5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) BIT(ADV7182_INPUT_CVBS_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) BIT(ADV7182_INPUT_CVBS_AIN7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) BIT(ADV7182_INPUT_CVBS_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static const struct adv7180_chip_info adv7281_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) BIT(ADV7182_INPUT_CVBS_AIN7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) BIT(ADV7182_INPUT_CVBS_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static const struct adv7180_chip_info adv7281_m_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) BIT(ADV7182_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) BIT(ADV7182_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) BIT(ADV7182_INPUT_CVBS_AIN7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) BIT(ADV7182_INPUT_CVBS_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const struct adv7180_chip_info adv7281_ma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) BIT(ADV7182_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) BIT(ADV7182_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) BIT(ADV7182_INPUT_CVBS_AIN5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) BIT(ADV7182_INPUT_CVBS_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) BIT(ADV7182_INPUT_CVBS_AIN7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) BIT(ADV7182_INPUT_CVBS_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static const struct adv7180_chip_info adv7282_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) BIT(ADV7182_INPUT_CVBS_AIN7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) BIT(ADV7182_INPUT_CVBS_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static const struct adv7180_chip_info adv7282_m_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) BIT(ADV7182_INPUT_CVBS_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) BIT(ADV7182_INPUT_CVBS_AIN3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) BIT(ADV7182_INPUT_CVBS_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) BIT(ADV7182_INPUT_CVBS_AIN7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) BIT(ADV7182_INPUT_CVBS_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .init = adv7182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .set_std = adv7182_set_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .select_input = adv7182_select_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int init_device(struct adv7180_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mutex_lock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) adv7180_set_power_pin(state, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = state->chip_info->init(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = adv7180_program_std(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) adv7180_set_field_mode(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* register for interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (state->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /* config the Interrupt pin to be active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = adv7180_write(state, ADV7180_REG_ICONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ADV7180_ICONF1_ACTIVE_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ADV7180_ICONF1_PSYNC_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* enable AD change interrupts interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = adv7180_write(state, ADV7180_REG_IMR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ADV7180_IRQ3_AD_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mutex_unlock(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int adv7180_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct adv7180_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) state->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) state->field = V4L2_FIELD_ALTERNATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) state->chip_info = (struct adv7180_chip_info *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (IS_ERR(state->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret = PTR_ERR(state->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) v4l_err(client, "request for power pin failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) state->csi_client = i2c_new_dummy_device(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ADV7180_DEFAULT_CSI_I2C_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (IS_ERR(state->csi_client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return PTR_ERR(state->csi_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (state->chip_info->flags & ADV7180_FLAG_I2P) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) state->vpp_client = i2c_new_dummy_device(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ADV7180_DEFAULT_VPP_I2C_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (IS_ERR(state->vpp_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ret = PTR_ERR(state->vpp_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) goto err_unregister_csi_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) state->irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) mutex_init(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) state->curr_norm = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) state->powered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) state->powered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) state->input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = adv7180_init_controls(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) goto err_unregister_vpp_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) state->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) goto err_free_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = init_device(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) goto err_media_entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (state->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) KBUILD_MODNAME, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) goto err_media_entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) client->addr, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (state->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) free_irq(client->irq, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) err_media_entity_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) err_free_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) adv7180_exit_controls(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) err_unregister_vpp_client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) i2c_unregister_device(state->vpp_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) err_unregister_csi_client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) i2c_unregister_device(state->csi_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) mutex_destroy(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static int adv7180_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (state->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) free_irq(client->irq, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) adv7180_exit_controls(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) i2c_unregister_device(state->vpp_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) i2c_unregister_device(state->csi_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) adv7180_set_power_pin(state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mutex_destroy(&state->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static const struct i2c_device_id adv7180_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) { "adv7180", (kernel_ulong_t)&adv7180_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) { "adv7180cp", (kernel_ulong_t)&adv7180_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) { "adv7180st", (kernel_ulong_t)&adv7180_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) { "adv7182", (kernel_ulong_t)&adv7182_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) { "adv7280", (kernel_ulong_t)&adv7280_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) { "adv7281", (kernel_ulong_t)&adv7281_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) { "adv7282", (kernel_ulong_t)&adv7282_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) MODULE_DEVICE_TABLE(i2c, adv7180_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int adv7180_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return adv7180_set_power(state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static int adv7180_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct adv7180_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ret = init_device(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ret = adv7180_set_power(state, state->powered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define ADV7180_PM_OPS (&adv7180_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define ADV7180_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const struct of_device_id adv7180_of_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) { .compatible = "adi,adv7180", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) { .compatible = "adi,adv7180cp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) { .compatible = "adi,adv7180st", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) { .compatible = "adi,adv7182", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) { .compatible = "adi,adv7280", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { .compatible = "adi,adv7280-m", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) { .compatible = "adi,adv7281", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) { .compatible = "adi,adv7281-m", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { .compatible = "adi,adv7281-ma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) { .compatible = "adi,adv7282", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) { .compatible = "adi,adv7282-m", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) MODULE_DEVICE_TABLE(of, adv7180_of_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static struct i2c_driver adv7180_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .pm = ADV7180_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .of_match_table = of_match_ptr(adv7180_of_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .probe = adv7180_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .remove = adv7180_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .id_table = adv7180_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) module_i2c_driver(adv7180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) MODULE_AUTHOR("Mocean Laboratories");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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