^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7175 - adv7175a video encoder driver version 0.0.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 Wolfgang Scherr <scherr@net4you.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - some corrections for Pinnacle Systems Inc. DC10plus card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Changes by Ronald Bultje <rbultje@ronald.bitfreak.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_DESCRIPTION("Analog Devices ADV7175 video encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_AUTHOR("Dave Perks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_ADV7175 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_ADV7176 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct adv7175 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline struct adv7175 *to_adv7175(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return container_of(sd, struct adv7175, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static char *inputs[] = { "pass_through", "play_back", "color_bar" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u32 adv7175_codes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MEDIA_BUS_FMT_UYVY8_1X16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline int adv7175_write(struct v4l2_subdev *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline int adv7175_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int adv7175_write_block(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const u8 *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* the adv7175 has an autoincrement function, use it if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * the adapter understands raw I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* do raw I2C, not smbus compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 block_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) block_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) block_data[block_len++] = reg = data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) block_data[block_len++] = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } while (len >= 2 && data[0] == reg && block_len < 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = i2c_master_send(client, block_data, block_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* do some slow I2C emulation kind of thing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = adv7175_write(sd, reg, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void set_subcarrier_freq(struct v4l2_subdev *sd, int pass_through)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* for some reason pass_through NTSC needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * a different sub-carrier freq to remain stable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (pass_through)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) adv7175_write(sd, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) adv7175_write(sd, 0x02, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) adv7175_write(sd, 0x03, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) adv7175_write(sd, 0x04, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) adv7175_write(sd, 0x05, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Output filter: S-Video Composite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MR050 0x11 /* 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MR060 0x14 /* 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TR0MODE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TR0RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TR1CAPT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TR1PLAY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const unsigned char init_common[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x00, MR050, /* MR0, PAL enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x01, 0x00, /* MR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x02, 0x0c, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x03, 0x8c, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x04, 0x79, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x05, 0x26, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x06, 0x40, /* subc. phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x07, TR0MODE, /* TR0, 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x08, 0x21, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x09, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x0a, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x0b, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x0c, TR1CAPT, /* TR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x0d, 0x4f, /* MR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x0e, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x0f, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x10, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x11, 0x00, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const unsigned char init_pal[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x00, MR050, /* MR0, PAL enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x01, 0x00, /* MR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x02, 0x0c, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x03, 0x8c, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x04, 0x79, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x05, 0x26, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x06, 0x40, /* subc. phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const unsigned char init_ntsc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0x00, MR060, /* MR0, NTSC enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0x01, 0x00, /* MR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0x02, 0x55, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x03, 0x55, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x04, 0x55, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x05, 0x25, /* subc. freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x06, 0x1a, /* subc. phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int adv7175_init(struct v4l2_subdev *sd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* This is just for testing!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) adv7175_write_block(sd, init_common, sizeof(init_common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int adv7175_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct adv7175 *encoder = to_adv7175(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (std & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) adv7175_write_block(sd, init_ntsc, sizeof(init_ntsc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (encoder->input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) adv7175_write(sd, 0x0d, 0x4f); /* Enable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else if (std & V4L2_STD_PAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) adv7175_write_block(sd, init_pal, sizeof(init_pal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (encoder->input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) adv7175_write(sd, 0x0d, 0x4f); /* Enable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else if (std & V4L2_STD_SECAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* This is an attempt to convert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * SECAM->PAL (typically it does not work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * due to genlock: when decoder is in SECAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * and encoder in in PAL the subcarrier can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * not be synchronized with horizontal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * quency) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) adv7175_write_block(sd, init_pal, sizeof(init_pal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (encoder->input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) adv7175_write(sd, 0x0d, 0x49); /* Disable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) v4l2_dbg(1, debug, sd, "illegal norm: %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) v4l2_dbg(1, debug, sd, "switched to %llx\n", (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) encoder->norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int adv7175_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct adv7175 *encoder = to_adv7175(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* RJ: input = 0: input is from decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) input = 1: input is from ZR36060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) input = 2: color bar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) adv7175_write(sd, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (encoder->norm & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) set_subcarrier_freq(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) adv7175_write(sd, 0x0c, TR1CAPT); /* TR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (encoder->norm & V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) adv7175_write(sd, 0x0d, 0x49); /* Disable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) adv7175_write(sd, 0x0d, 0x4f); /* Enable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*udelay(10);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) adv7175_write(sd, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (encoder->norm & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) set_subcarrier_freq(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) adv7175_write(sd, 0x0c, TR1PLAY); /* TR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) adv7175_write(sd, 0x0d, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* udelay(10); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) adv7175_write(sd, 0x01, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (encoder->norm & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) set_subcarrier_freq(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) adv7175_write(sd, 0x0d, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* udelay(10); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) v4l2_dbg(1, debug, sd, "illegal input: %d\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) v4l2_dbg(1, debug, sd, "switched to %s\n", inputs[input]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) encoder->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int adv7175_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (code->pad || code->index >= ARRAY_SIZE(adv7175_codes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) code->code = adv7175_codes[code->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int adv7175_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 val = adv7175_read(sd, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if ((val & 0x40) == (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mf->code = MEDIA_BUS_FMT_UYVY8_1X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mf->width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mf->height = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mf->field = V4L2_FIELD_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int adv7175_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 val = adv7175_read(sd, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (mf->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case MEDIA_BUS_FMT_UYVY8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "illegal v4l2_mbus_framefmt code: %d\n", mf->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = adv7175_write(sd, 0x7, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int adv7175_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) adv7175_write(sd, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) adv7175_write(sd, 0x01, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct v4l2_subdev_core_ops adv7175_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .init = adv7175_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .s_power = adv7175_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct v4l2_subdev_video_ops adv7175_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .s_std_output = adv7175_s_std_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .s_routing = adv7175_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct v4l2_subdev_pad_ops adv7175_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .enum_mbus_code = adv7175_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .get_fmt = adv7175_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .set_fmt = adv7175_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct v4l2_subdev_ops adv7175_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .core = &adv7175_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .video = &adv7175_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .pad = &adv7175_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int adv7175_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct adv7175 *encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) encoder = devm_kzalloc(&client->dev, sizeof(*encoder), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (encoder == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sd = &encoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) v4l2_i2c_subdev_init(sd, client, &adv7175_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) encoder->norm = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) encoder->input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) i = adv7175_write_block(sd, init_common, sizeof(init_common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) i = adv7175_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) i = adv7175_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i = adv7175_read(sd, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) v4l2_dbg(1, debug, sd, "revision %d\n", i & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) v4l2_dbg(1, debug, sd, "init error 0x%x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int adv7175_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct i2c_device_id adv7175_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { "adv7175", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { "adv7176", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DEVICE_TABLE(i2c, adv7175_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct i2c_driver adv7175_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .name = "adv7175",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .probe = adv7175_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .remove = adv7175_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .id_table = adv7175_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) module_i2c_driver(adv7175_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags