^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * adv7170 - adv7170, adv7171 video encoder driver version 0.0.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on adv7176 driver by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999 Wolfgang Scherr <scherr@net4you.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - some corrections for Pinnacle Systems Inc. DC10plus card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Changes by Ronald Bultje <rbultje@ronald.bitfreak.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - moved over to linux>=2.4.x i2c protocol (1/1/2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_DESCRIPTION("Analog Devices ADV7170 video encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_AUTHOR("Maxim Yevtyushkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct adv7170 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned char reg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline struct adv7170 *to_adv7170(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return container_of(sd, struct adv7170, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static char *inputs[] = { "pass_through", "play_back" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u32 adv7170_codes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MEDIA_BUS_FMT_UYVY8_1X16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline int adv7170_write(struct v4l2_subdev *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct adv7170 *encoder = to_adv7170(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) encoder->reg[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline int adv7170_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int adv7170_write_block(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const u8 *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct adv7170 *encoder = to_adv7170(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* the adv7170 has an autoincrement function, use it if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * the adapter understands raw I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* do raw I2C, not smbus compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 block_data[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) block_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) block_data[block_len++] = reg = data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) block_data[block_len++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) encoder->reg[reg++] = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } while (len >= 2 && data[0] == reg && block_len < 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = i2c_master_send(client, block_data, block_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* do some slow I2C emulation kind of thing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) while (len >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = adv7170_write(sd, reg, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TR0MODE 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TR0RST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TR1CAPT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TR1PLAY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const unsigned char init_NTSC[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x00, 0x10, /* MR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x01, 0x20, /* MR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x02, 0x0e, /* MR2 RTC control: bits 2 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x03, 0x80, /* MR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x04, 0x30, /* MR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x05, 0x00, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x06, 0x00, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x07, TR0MODE, /* TM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x08, TR1CAPT, /* TM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x09, 0x16, /* Fsc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x0a, 0x7c, /* Fsc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x0b, 0xf0, /* Fsc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x0c, 0x21, /* Fsc3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x0d, 0x00, /* Subcarrier Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x0e, 0x00, /* Closed Capt. Ext 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x0f, 0x00, /* Closed Capt. Ext 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x10, 0x00, /* Closed Capt. 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x11, 0x00, /* Closed Capt. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x12, 0x00, /* Pedestal Ctl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x13, 0x00, /* Pedestal Ctl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x14, 0x00, /* Pedestal Ctl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x15, 0x00, /* Pedestal Ctl 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x16, 0x00, /* CGMS_WSS_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x17, 0x00, /* CGMS_WSS_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0x18, 0x00, /* CGMS_WSS_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x19, 0x00, /* Teletext Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const unsigned char init_PAL[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x00, 0x71, /* MR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x01, 0x20, /* MR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x02, 0x0e, /* MR2 RTC control: bits 2 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x03, 0x80, /* MR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x04, 0x30, /* MR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x05, 0x00, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x06, 0x00, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x07, TR0MODE, /* TM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x08, TR1CAPT, /* TM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x09, 0xcb, /* Fsc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x0a, 0x8a, /* Fsc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x0b, 0x09, /* Fsc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x0c, 0x2a, /* Fsc3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x0d, 0x00, /* Subcarrier Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x0e, 0x00, /* Closed Capt. Ext 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x0f, 0x00, /* Closed Capt. Ext 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x10, 0x00, /* Closed Capt. 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x11, 0x00, /* Closed Capt. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0x12, 0x00, /* Pedestal Ctl 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0x13, 0x00, /* Pedestal Ctl 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0x14, 0x00, /* Pedestal Ctl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0x15, 0x00, /* Pedestal Ctl 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x16, 0x00, /* CGMS_WSS_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x17, 0x00, /* CGMS_WSS_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x18, 0x00, /* CGMS_WSS_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x19, 0x00, /* Teletext Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int adv7170_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct adv7170 *encoder = to_adv7170(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) v4l2_dbg(1, debug, sd, "set norm %llx\n", (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (std & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) adv7170_write_block(sd, init_NTSC, sizeof(init_NTSC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (encoder->input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) adv7170_write(sd, 0x02, 0x0e); /* Enable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) adv7170_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) adv7170_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else if (std & V4L2_STD_PAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) adv7170_write_block(sd, init_PAL, sizeof(init_PAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (encoder->input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) adv7170_write(sd, 0x02, 0x0e); /* Enable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) adv7170_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) adv7170_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) v4l2_dbg(1, debug, sd, "illegal norm: %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) v4l2_dbg(1, debug, sd, "switched to %llx\n", (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) encoder->norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int adv7170_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct adv7170 *encoder = to_adv7170(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* RJ: input = 0: input is from decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) input = 1: input is from ZR36060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) input = 2: color bar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) v4l2_dbg(1, debug, sd, "set input from %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) input == 0 ? "decoder" : "ZR36060");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) adv7170_write(sd, 0x01, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) adv7170_write(sd, 0x08, TR1CAPT); /* TR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) adv7170_write(sd, 0x02, 0x0e); /* Enable genlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) adv7170_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) adv7170_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* udelay(10); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) adv7170_write(sd, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) adv7170_write(sd, 0x08, TR1PLAY); /* TR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) adv7170_write(sd, 0x02, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) adv7170_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) adv7170_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* udelay(10); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) v4l2_dbg(1, debug, sd, "illegal input: %d\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) v4l2_dbg(1, debug, sd, "switched to %s\n", inputs[input]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) encoder->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int adv7170_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (code->pad || code->index >= ARRAY_SIZE(adv7170_codes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) code->code = adv7170_codes[code->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int adv7170_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 val = adv7170_read(sd, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if ((val & 0x40) == (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mf->code = MEDIA_BUS_FMT_UYVY8_1X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mf->width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mf->height = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mf->field = V4L2_FIELD_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int adv7170_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 val = adv7170_read(sd, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (mf->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case MEDIA_BUS_FMT_UYVY8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "illegal v4l2_mbus_framefmt code: %d\n", mf->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return adv7170_write(sd, 0x7, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct v4l2_subdev_video_ops adv7170_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .s_std_output = adv7170_s_std_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .s_routing = adv7170_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct v4l2_subdev_pad_ops adv7170_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .enum_mbus_code = adv7170_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .get_fmt = adv7170_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .set_fmt = adv7170_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct v4l2_subdev_ops adv7170_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .video = &adv7170_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .pad = &adv7170_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int adv7170_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct adv7170 *encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) encoder = devm_kzalloc(&client->dev, sizeof(*encoder), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (encoder == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sd = &encoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) v4l2_i2c_subdev_init(sd, client, &adv7170_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) encoder->norm = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) encoder->input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) i = adv7170_write_block(sd, init_NTSC, sizeof(init_NTSC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) i = adv7170_write(sd, 0x07, TR0MODE | TR0RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i = adv7170_write(sd, 0x07, TR0MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) i = adv7170_read(sd, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) v4l2_dbg(1, debug, sd, "revision %d\n", i & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) v4l2_dbg(1, debug, sd, "init error 0x%x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int adv7170_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct i2c_device_id adv7170_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { "adv7170", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { "adv7171", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_DEVICE_TABLE(i2c, adv7170_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct i2c_driver adv7170_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "adv7170",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .probe = adv7170_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .remove = adv7170_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .id_table = adv7170_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) module_i2c_driver(adv7170_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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