^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog Devices AD9389B/AD9889B video encoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * HDMI Transitter, Rev. A, October 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/i2c/ad9389b.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(debug, "debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MASK_AD9389B_EDID_RDY_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MASK_AD9389B_MSEN_INT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MASK_AD9389B_HPD_INT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MASK_AD9389B_HPD_DETECT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MASK_AD9389B_MSEN_DETECT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MASK_AD9389B_EDID_RDY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EDID_MAX_RETRIES (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EDID_DELAY 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EDID_MAX_SEGM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Arrays with configuration parameters for the AD9389B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct ad9389b_state_edid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* total number of blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Number of segments read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 segments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 data[EDID_MAX_SEGM * 256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Number of EDID read retries left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned read_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ad9389b_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ad9389b_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int chip_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Is the ad9389b powered on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Did we receive hotplug and rx-sense signals? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool have_monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* timings from s_dv_timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct v4l2_dv_timings dv_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct v4l2_ctrl *hdmi_mode_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct v4l2_ctrl *hotplug_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct v4l2_ctrl *rx_sense_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct v4l2_ctrl *have_edid0_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct v4l2_ctrl *rgb_quantization_range_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2c_client *edid_i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ad9389b_state_edid edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Running counter of the number of detected EDIDs (for debugging) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned edid_detect_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct delayed_work edid_handler; /* work entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void ad9389b_setup(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return container_of(sd, struct ad9389b_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* ------------------------ I2C ----------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) and then the value-mask (to be OR-ed). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 clr_mask, u8 val_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u16 A1, u16 A2, u16 A3, u16 A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u16 B1, u16 B2, u16 B3, u16 B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u16 C1, u16 C2, u16 C3, u16 C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ad9389b_wr(sd, 0x19, A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ad9389b_wr(sd, 0x1B, A2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ad9389b_wr(sd, 0x1d, A3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ad9389b_wr(sd, 0x1f, A4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ad9389b_wr(sd, 0x21, B1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ad9389b_wr(sd, 0x23, B2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ad9389b_wr(sd, 0x25, B3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ad9389b_wr(sd, 0x27, B4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ad9389b_wr(sd, 0x29, C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ad9389b_wr(sd, 0x2B, C2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ad9389b_wr(sd, 0x2D, C3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ad9389b_wr(sd, 0x2F, C4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 csc_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ad9389b_csc_conversion_mode(sd, csc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ad9389b_csc_coeff(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 4096-564, 0, 0, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0, 4096-564, 0, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0, 0, 4096-564, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* enable CSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* AVI infoframe: Limited range RGB (16-235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* disable CSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* AVI infoframe: Full range RGB (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* CE format, not IT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* IT format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case V4L2_DV_RGB_RANGE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* CE format, RGB limited range (16-235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ad9389b_csc_rgb_full2limit(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* not CE format, RGB full range (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ad9389b_csc_rgb_full2limit(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case V4L2_DV_RGB_RANGE_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* RGB limited range (16-235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ad9389b_csc_rgb_full2limit(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case V4L2_DV_RGB_RANGE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* RGB full range (0-255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ad9389b_csc_rgb_full2limit(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Workaround for TMDS PLL problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * The TMDS PLL in AD9389b change gear when the chip is heated above a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * certain temperature. The output is disabled when the PLL change gear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * so the monitor has to lock on the signal again. A workaround for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * this is to use the manual PLL gears. This is a solution from Analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Devices that is not documented in the datasheets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * The pixel frequency ranges are based on readout of the gear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * automatic gearing selects for different pixel clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * (read from 0x9e [3:1]).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (pixelclock > 140000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) gear = 0xc0; /* 4th gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else if (pixelclock > 117000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) gear = 0xb0; /* 3rd gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else if (pixelclock > 87000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) gear = 0xa0; /* 2nd gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) else if (pixelclock > 60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) gear = 0x90; /* 1st gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gear = 0x80; /* 0th gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* ------------------------------ CTRL OPS ------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (state->hdmi_mode_ctrl == ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Set HDMI or DVI-D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ad9389b_wr_and_or(sd, 0xaf, 0xfd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (state->rgb_quantization_range_ctrl == ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ad9389b_set_rgb_quantization_mode(sd, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .s_ctrl = ad9389b_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* ---------------------------- CORE OPS ------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg->val = ad9389b_rd(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int ad9389b_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct ad9389b_state_edid *edid = &state->edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const char * const states[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "in reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "reading EDID",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "initializing HDCP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "HDCP enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "initializing HDCP repeater",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const char * const errors[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "no error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "bad receiver BKSV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "Ri mismatch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "Pj mismatch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "i2c error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "timed out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "max repeater cascade exceeded",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "hash check failed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "too many devices",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "9", "A", "B", "C", "D", "E", "F"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 manual_gear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) v4l2_info(sd, "chip revision %d\n", state->chip_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "detected" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "detected" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) edid->segments ? "found" : "no", edid->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) v4l2_info(sd, "%s output %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (ad9389b_rd(sd, 0xaf) & 0x02) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "HDMI" : "DVI-D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (ad9389b_rd(sd, 0xa1) & 0x3c) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "disabled" : "enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "encrypted" : "no encryption");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) states[ad9389b_rd(sd, 0xc8) & 0xf],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) errors[ad9389b_rd(sd, 0xc8) >> 4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) state->edid_detect_counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) v4l2_info(sd, "ad9389b: %s gear %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) manual_gear ? "manual" : "automatic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ad9389b_rd(sd, 0xaf) & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* HDMI only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ad9389b_rd(sd, 0x02) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ad9389b_rd(sd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (manual_cts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ad9389b_rd(sd, 0x08) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ad9389b_rd(sd, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ad9389b_rd(sd, 0x05) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ad9389b_rd(sd, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ad9389b_rd(sd, 0x02) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ad9389b_rd(sd, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) manual_cts ? "manual" : "automatic", N, CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) vic_detect, vic_sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (state->dv_timings.type == V4L2_DV_BT_656_1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) v4l2_print_dv_timings(sd->name, "timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &state->dv_timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) v4l2_info(sd, "no timings set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Power up/down ad9389b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct ad9389b_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) const int retries = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) state->power_on = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* The ad9389b does not always come up immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) Retry multiple times. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (i = 0; i < retries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (i == retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ad9389b_s_power(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (i > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "needed %d retries to powerup the ad9389b\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Select chip: AD9389B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Reserved registers that must be set according to REF_01 p. 11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ad9389b_wr(sd, 0x9c, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Differential output drive strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (pdata->diff_data_drive_strength > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ad9389b_wr(sd, 0xa2, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (pdata->diff_clk_drive_strength > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ad9389b_wr(sd, 0xa3, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ad9389b_wr(sd, 0x0a, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ad9389b_wr(sd, 0xbb, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Set number of attempts to read the EDID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ad9389b_wr(sd, 0xc9, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 irqs_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int retries = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* The datasheet says that the EDID ready interrupt should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) disabled if there is no hotplug. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else if (ad9389b_have_hotplug(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) irqs |= MASK_AD9389B_EDID_RDY_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * This i2c write can fail (approx. 1 in 1000 writes). But it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * is essential that this register is correct, so retry it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * multiple times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * Note that the i2c write does not report an error, but the readback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * clearly shows the wrong value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ad9389b_wr(sd, 0x94, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) irqs_rd = ad9389b_rd(sd, 0x94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } while (retries-- && irqs_rd != irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (irqs_rd != irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) v4l2_err(sd, "Could not set interrupts: hw failure?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* disable interrupts to prevent a race condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ad9389b_set_isr(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) irq_status = ad9389b_rd(sd, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* clear detected interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ad9389b_wr(sd, 0x96, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ad9389b_set_isr(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) v4l2_dbg(1, debug, sd, "%s: irq_status 0x%x\n", __func__, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (irq_status & (MASK_AD9389B_HPD_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ad9389b_check_monitor_present_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (irq_status & MASK_AD9389B_EDID_RDY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ad9389b_check_edid_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .log_status = ad9389b_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .g_register = ad9389b_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .s_register = ad9389b_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .s_power = ad9389b_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .interrupt_service_routine = ad9389b_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* ------------------------------ VIDEO OPS ------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Enable/disable ad9389b output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ad9389b_check_monitor_present_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ad9389b_s_power(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* quick sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if the format is one of the CEA or DMT timings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* save timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) state->dv_timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* update quantization range based on new dv_timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* update PLL gear based on new dv_timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* update AVI infoframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ad9389b_set_IT_content_AVI_InfoFrame(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *timings = state->dv_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *cap = ad9389b_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .s_stream = ad9389b_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .s_dv_timings = ad9389b_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .g_dv_timings = ad9389b_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* ------------------------------ PAD OPS ------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (edid->blocks == 0 || edid->blocks > 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!state->edid.segments) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (edid->start_block >= state->edid.segments * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (edid->blocks + edid->start_block >= state->edid.segments * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) edid->blocks = state->edid.segments * 2 - edid->start_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 128 * edid->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .get_edid = ad9389b_get_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .enum_dv_timings = ad9389b_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .dv_timings_cap = ad9389b_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* ------------------------------ AUDIO OPS ------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case 32000: N = 4096; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case 44100: N = 6272; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case 48000: N = 6144; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case 88200: N = 12544; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case 96000: N = 12288; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case 176400: N = 25088; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case 192000: N = 24576; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Set N (used with CTS to regenerate the audio clock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ad9389b_wr(sd, 0x03, N & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 i2s_sf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case 32000: i2s_sf = 0x30; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case 44100: i2s_sf = 0x00; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case 48000: i2s_sf = 0x20; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case 88200: i2s_sf = 0x80; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case 96000: i2s_sf = 0xa0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case 176400: i2s_sf = 0xc0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case 192000: i2s_sf = 0xe0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Set sampling frequency for I2S audio to 48 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* TODO based on input/output/config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* TODO See datasheet "Programmers guide" p. 39-40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Only 2 channels in use for application */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Speaker mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ad9389b_wr(sd, 0x51, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* TODO Where should this be placed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* 16 bit audio word length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .s_stream = ad9389b_s_audio_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .s_clock_freq = ad9389b_s_clock_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .s_routing = ad9389b_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* --------------------- SUBDEV OPS --------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const struct v4l2_subdev_ops ad9389b_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .core = &ad9389b_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .video = &ad9389b_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .audio = &ad9389b_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .pad = &ad9389b_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int segment, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (debug < lvl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) for (i = 0; i < 256; i += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u8 b[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u8 *bp = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (i == 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) v4l2_dbg(lvl, debug, sd, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (j = i; j < i + 16; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sprintf(bp, "0x%02x, ", buf[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bp += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) bp[0] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) v4l2_dbg(lvl, debug, sd, "%s\n", b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static void ad9389b_edid_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct ad9389b_state *state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) container_of(dwork, struct ad9389b_state, edid_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct ad9389b_edid_detect ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ad9389b_check_edid_status(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Return if we received the EDID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (ad9389b_have_hotplug(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* We must retry reading the EDID several times, it is possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * that initially the EDID couldn't be read due to i2c errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * (DVI connectors are particularly prone to this problem). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (state->edid.read_retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) state->edid.read_retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ad9389b_s_power(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ad9389b_s_power(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) schedule_delayed_work(&state->edid_handler, EDID_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* We failed to read the EDID, so send an event for this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ed.present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ed.segment = ad9389b_rd(sd, 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static void ad9389b_audio_setup(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) v4l2_dbg(1, debug, sd, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ad9389b_s_i2s_clock_freq(sd, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ad9389b_s_clock_freq(sd, 48000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ad9389b_s_routing(sd, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Initial setup of AD9389b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Configure hdmi transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static void ad9389b_setup(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) v4l2_dbg(1, debug, sd, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Input format: RGB 4:4:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Output format: RGB 4:4:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) Aspect ratio: 16:9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Output format: RGB 4:4:4, Active Format Information is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Underscanned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Setup video format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ad9389b_wr(sd, 0x3c, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Active format aspect ratio: same as picure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ad9389b_wr(sd, 0x47, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* No encryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Positive clk edge capture for input video clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ad9389b_audio_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) v4l2_ctrl_handler_setup(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ad9389b_set_IT_content_AVI_InfoFrame(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct ad9389b_monitor_detect mdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mdt.present = state->have_monitor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static void ad9389b_update_monitor_present_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* read hotplug and rx-sense state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u8 status = ad9389b_rd(sd, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (status & MASK_AD9389B_HPD_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) state->have_monitor = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!ad9389b_s_power(sd, true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "%s: monitor detected, powerup failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ad9389b_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ad9389b_notify_monitor_detect(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) state->edid.read_retries = EDID_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) schedule_delayed_work(&state->edid_handler, EDID_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) state->have_monitor = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ad9389b_notify_monitor_detect(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ad9389b_s_power(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* update read only ctrls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* update with setting from ctrls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ad9389b_s_ctrl(state->rgb_quantization_range_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ad9389b_s_ctrl(state->hdmi_mode_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ad9389b_update_monitor_present_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * Rapid toggling of the hotplug may leave the chip powered off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * even if we think it is on. In that case reset and power up again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (++retry > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) v4l2_err(sd, "retried %d times, give up\n", retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) v4l2_dbg(1, debug, sd, "%s: reset and re-check status (%d)\n", __func__, retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ad9389b_notify_monitor_detect(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) cancel_delayed_work_sync(&state->edid_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ad9389b_s_power(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ad9389b_update_monitor_present_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static bool edid_block_verify_crc(u8 *edid_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) for (i = 0; i < 128; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) sum += edid_block[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return sum == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 blocks = state->edid.blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u8 *data = state->edid.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (edid_block_verify_crc(&data[segment * 256])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if ((segment + 1) * 2 <= blocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return edid_block_verify_crc(&data[segment * 256 + 128]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const u8 hdmi_header[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u8 *data = state->edid.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (data[i] != hdmi_header[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct ad9389b_edid_detect ed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u8 edidRdy = ad9389b_rd(sd, 0xc5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) __func__, EDID_MAX_RETRIES - state->edid.read_retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!(edidRdy & MASK_AD9389B_EDID_RDY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) segment = ad9389b_rd(sd, 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (segment >= EDID_MAX_SEGM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) v4l2_err(sd, "edid segment number too big\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ad9389b_dbg_dump_edid(2, debug, sd, segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) &state->edid.data[segment * 256]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (segment == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) state->edid.blocks = state->edid.data[0x7e] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __func__, state->edid.blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (!edid_verify_crc(sd, segment) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) !edid_verify_header(sd, segment)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* edid crc error, force reread of edid segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) v4l2_err(sd, "%s: edid crc or header error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ad9389b_s_power(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ad9389b_s_power(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* one more segment read ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) state->edid.segments = segment + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Request next EDID segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) __func__, state->edid.segments);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ad9389b_wr(sd, 0xc9, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ad9389b_wr(sd, 0xc4, state->edid.segments);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) state->edid.read_retries = EDID_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) schedule_delayed_work(&state->edid_handler, EDID_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* report when we have all segments but report only for segment 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ed.present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ed.segment = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) state->edid_detect_counter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return ed.present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void ad9389b_init_setup(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct ad9389b_state_edid *edid = &state->edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) v4l2_dbg(1, debug, sd, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ad9389b_wr(sd, 0x96, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) memset(edid, 0, sizeof(struct ad9389b_state_edid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) state->have_monitor = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ad9389b_set_isr(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct ad9389b_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct ad9389b_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) client->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) v4l_err(client, "No platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) memcpy(&state->pdata, pdata, sizeof(state->pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) hdl = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) v4l2_ctrl_handler_init(hdl, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) 0, V4L2_DV_TX_MODE_DVI_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) state->rgb_quantization_range_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) 0, V4L2_DV_RGB_RANGE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) err = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) state->pad.flags = MEDIA_PAD_FL_SINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) sd->entity.function = MEDIA_ENT_F_DV_ENCODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) err = media_entity_pads_init(&sd->entity, 1, &state->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) state->chip_revision = ad9389b_rd(sd, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (state->chip_revision != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) goto err_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ad9389b_rd(sd, 0x41), state->chip_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) state->edid_i2c_client = i2c_new_dummy_device(client->adapter, (0x7e >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (IS_ERR(state->edid_i2c_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) v4l2_err(sd, "failed to register edid i2c client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) err = PTR_ERR(state->edid_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) goto err_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) state->dv_timings = dv1080p60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ad9389b_init_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ad9389b_set_isr(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) err_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) err_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static int ad9389b_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct ad9389b_state *state = get_ad9389b_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) state->chip_revision = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ad9389b_s_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ad9389b_s_audio_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ad9389b_init_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) cancel_delayed_work_sync(&state->edid_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) i2c_unregister_device(state->edid_i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const struct i2c_device_id ad9389b_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) { "ad9389b", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) { "ad9889b", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) MODULE_DEVICE_TABLE(i2c, ad9389b_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static struct i2c_driver ad9389b_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .name = "ad9389b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .probe = ad9389b_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .remove = ad9389b_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .id_table = ad9389b_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) module_i2c_driver(ad9389b_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags