Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Zarlink zl10036 DVB-S silicon tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2006 Tino Reichardt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * The data sheet for this tuner can be found at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *    http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This one is working: (at my Avermedia DVB-S Pro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * - zl10036 (40pin, FTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * A driver for zl10038 should be very similar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "zl10036.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static int zl10036_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define dprintk(level, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define deb_info(args...)  dprintk(0x01, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define deb_i2c(args...)  dprintk(0x02, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct zl10036_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	const struct zl10036_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u8 br, bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* This driver assumes the tuner is driven by a 10.111MHz Cristal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define _XTAL 10111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* Some of the possible dividers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *   64, (write 0x05 to reg), freq step size   158kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *   10, (write 0x0a to reg), freq step size 1.011kHz (used here)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *    5, (write 0x09 to reg), freq step size 2.022kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define _RDIV 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define _RDIV_REG 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define _FR   (_XTAL/_RDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define STATUS_POR 0x80 /* Power on Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define STATUS_FL  0x40 /* Frequency & Phase Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* read/write for zl10036 and zl10038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int zl10036_read_status_reg(struct zl10036_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct i2c_msg msg[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		{ .addr = state->config->tuner_address, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		  .buf = &status, .len = sizeof(status) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (i2c_transfer(state->i2c, msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			__func__, state->config->tuner_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	deb_i2c("R(status): %02x  [FL=%d]\n", status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		(status & STATUS_FL) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (status & STATUS_POR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			 __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct i2c_msg msg[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		{ .addr = state->config->tuner_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		  .buf = buf, .len = count },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (zl10036_debug & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* every 8bit-value satisifes this!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * so only check for debug log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		if ((buf[0] & 0x80) == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			reg = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		else if ((buf[0] & 0xc0) == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			reg = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		else if ((buf[0] & 0xf0) == 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			reg = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		else if ((buf[0] & 0xf0) == 0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			reg = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		else if ((buf[0] & 0xf0) == 0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			reg = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		else if ((buf[0] & 0xf0) == 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			reg = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		deb_i2c("W(%d):", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				printk(KERN_CONT " %02x", buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ret = i2c_transfer(state->i2c, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void zl10036_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct zl10036_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int zl10036_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct zl10036_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	deb_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ret = zl10036_write(state, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * register map of the ZL10036/ZL10038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * reg[default] content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *  2[0x00]:   0 | N14 | N13 | N12 | N11 | N10 |  N9 |  N8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  *  3[0x00]:  N7 |  N6 |  N5 |  N4 |  N3 |  N2 |  N1 |  N0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *  4[0x80]:   1 |   0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *  5[0x00]:  P0 |  C1 |  C0 |  R4 |  R3 |  R2 |  R1 |  R0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *  6[0xc0]:   1 |   1 |   0 |   0 | RSD |   0 |   0 |   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *  7[0x20]:  P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 |   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *  8[0xdb]:   1 |   1 |   0 |   1 |   0 |  CC |   1 |   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *  9[0x30]: VSD |  V2 |  V1 |  V0 |  S3 |  S2 |  S1 |  S0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * 10[0xe1]:   1 |   1 |   1 |   0 |   0 | LS2 | LS1 | LS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * 11[0xf5]:  WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * 12[0xf0]:   1 |   1 |   1 |   1 |   0 |   0 |   0 |   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * 13[0x28]:  PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR |  TL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 div, foffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	div = (frequency + _FR/2) / _FR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	state->frequency = div * _FR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	foffset = frequency - state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	buf[0] = (div >> 8) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	buf[1] = (div >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		frequency, state->frequency, foffset, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return zl10036_write(state, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* fbw is measured in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u8 br, bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u8 buf_bf[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		0xc0, 0x00, /*   6/7: rsd=0 bf=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u8 buf_br[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* ensure correct values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (fbw > 35000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		fbw = 35000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (fbw <  8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		fbw =  8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* <= 28,82 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (fbw <= 28820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		br = _BR_MAXIMUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		 *  f(bw)=34,6MHz f(xtal)=10.111MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		 *  br = (10111/34600) * 63 * 1/K = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		br = ((_XTAL * 21 * 1000) / (fbw * 419));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* ensure correct values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (br < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		br = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (br > _BR_MAXIMUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		br = _BR_MAXIMUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * k = 1.257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * bf = fbw/_XTAL * br * k - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* ensure correct values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (bf > 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		bf = 62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	buf_bf[1] = (bf << 1) & 0x7e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	buf_br[1] = (br << 2) & 0x7c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (br != state->br) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		ret = zl10036_write(state, buf_br, sizeof(buf_br));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (bf != state->bf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		/* time = br/(32* fxtal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		/* minimal sleep time to be calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		ret = zl10036_write(state, zl10036_rsd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			sizeof(zl10036_rsd_off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	state->br = br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	state->bf = bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int zl10036_set_gain_params(struct zl10036_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	u8 rfg, ba, bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	rfg = 0; /* enable when using an lna */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ba = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	bg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	buf[0] = 0x80 | ((rfg << 5) & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		| ((ba  << 3) & 0x18) | ((bg  << 1) & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (!state->config->rf_loop_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		buf[0] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* P0=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	buf[1] = _RDIV_REG | ((c << 5) & 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return zl10036_write(state, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int zl10036_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct zl10036_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u32 frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u32 fbw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	u8 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* ensure correct values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 * maybe redundant as core already checks this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if ((frequency < fe->ops.info.frequency_min_hz / kHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	||  (frequency > fe->ops.info.frequency_max_hz / kHz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * alpha = 1.35 for dvb-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * fBW = (alpha*symbolrate)/(2*0.8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * 1.35 / (2*0.8) = 27 / 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	fbw = (27 * p->symbol_rate) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* scale to kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	fbw /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* Add safe margin of 3MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	fbw += 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* setting the charge pump - guessed values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (frequency < 950000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	else if (frequency < 1250000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	else if (frequency < 1750000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		c = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	else if (frequency < 2175000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		c = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = zl10036_set_gain_params(state, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	ret = zl10036_set_frequency(state, p->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ret = zl10036_set_bandwidth(state, fbw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	/* wait for tuner lock - no idea if this is really needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		ret = zl10036_read_status_reg(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		/* check Frequency & Phase Lock Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		if (ret & STATUS_FL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	struct zl10036_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	*frequency = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int zl10036_init_regs(struct zl10036_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* could also be one block from reg 2 to 13 and additional 10/11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	u8 zl10036_init_tab[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		{ 0x04, 0x00 },		/*   2/3: div=0x400 - arbitrary value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		{ 0x8b, _RDIV_REG },	/*   4/5: rfg=0 ba=1 bg=1 len=? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 					/*        p0=0 c=0 r=_RDIV_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		{ 0xc0, 0x20 },		/*   6/7: rsd=0 bf=0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		{ 0xd3, 0x40 },		/*   8/9: from datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		{ 0xe3, 0x5b },		/* 10/11: lock window level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		{ 0xf0, 0x28 },		/* 12/13: br=0xa clr=0 tl=0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		{ 0xe3, 0xf9 },		/* 10/11: unlock window level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* invalid values to trigger writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	state->br = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	state->bf = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (!state->config->rf_loop_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		zl10036_init_tab[1][0] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	deb_info("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		ret = zl10036_write(state, zl10036_init_tab[i], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int zl10036_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	struct zl10036_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	ret = zl10036_read_status_reg(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* Only init if Power-on-Reset bit is set? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	ret = zl10036_init_regs(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct dvb_tuner_ops zl10036_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		.name = "Zarlink ZL10036",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		.frequency_min_hz =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		.frequency_max_hz = 2175 * MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.init = zl10036_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.release = zl10036_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.sleep = zl10036_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.set_params = zl10036_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.get_frequency = zl10036_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 				    const struct zl10036_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 				    struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	struct zl10036_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (!config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		printk(KERN_ERR "%s: no config specified", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	ret = zl10036_read_status_reg(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		printk(KERN_ERR "%s: No zl10036 found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	ret = zl10036_init_regs(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		printk(KERN_ERR "%s: tuner initialization failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 			__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		__func__, fe->ops.tuner_ops.info.name, config->tuner_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) EXPORT_SYMBOL(zl10036_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) module_param_named(debug, zl10036_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MODULE_DESCRIPTION("DVB ZL10036 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MODULE_AUTHOR("Tino Reichardt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_AUTHOR("Matthias Schwarzott");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_LICENSE("GPL");