Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* z0194a.h Sharp z0194a tuner support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) * Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef Z0194A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define Z0194A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static int sharp_z0194a_set_symbol_rate(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 					 u32 srate, u32 ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u8 aclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	u8 bclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	if (srate < 1500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		aclk = 0xb7; bclk = 0x47; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	else if (srate < 3000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		aclk = 0xb7; bclk = 0x4b; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	else if (srate < 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		aclk = 0xb7; bclk = 0x4f; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	else if (srate < 14000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		aclk = 0xb7; bclk = 0x53; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	else if (srate < 30000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		aclk = 0xb6; bclk = 0x53; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	else if (srate < 45000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		aclk = 0xb4; bclk = 0x51; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	stv0299_writereg(fe, 0x13, aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	stv0299_writereg(fe, 0x14, bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static u8 sharp_z0194a_inittab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	0x01, 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	0x02, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	0x03, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	0x04, 0x7d,   /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	0x05, 0x35,   /* I2CT = 0, SCLT = 1, SDAT = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	0x06, 0x40,   /* DAC not used, set to high impendance mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	0x07, 0x00,   /* DAC LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	0x08, 0x40,   /* DiSEqC off, LNB power on OP2/LOCK pin on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	0x09, 0x00,   /* FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	0x0c, 0x51,   /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	0x0d, 0x82,   /* DC offset compensation = ON, beta_agc1 = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	0x0e, 0x23,   /* alpha_tmg = 2, beta_tmg = 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	0x10, 0x3f,   /* AGC2  0x3d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	0x11, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	0x12, 0xb9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	0x15, 0xc9,   /* lock detector threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	0x16, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	0x17, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	0x18, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	0x19, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	0x1a, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	0x1f, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	0x20, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	0x21, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	0x22, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	0x23, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	0x28, 0x00,  /* out imp: normal  out type: parallel FEC mode:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	0x29, 0x1e,  /* 1/2 threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	0x2a, 0x14,  /* 2/3 threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	0x2b, 0x0f,  /* 3/4 threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	0x2c, 0x09,  /* 5/6 threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	0x2d, 0x05,  /* 7/8 threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	0x2e, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	0x31, 0x1f,  /* test all FECs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	0x32, 0x19,  /* viterbi and synchro search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	0x33, 0xfc,  /* rs control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	0x34, 0x93,  /* error control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	0x0f, 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	0xff, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif