^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Driver for VES1893 and VES1993 QPSK Demodulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ves1x93.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct ves1x93_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) const struct ves1x93_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* previous uncorrected block counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum fe_spectral_inversion inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 *init_1x93_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 *init_1x93_wtab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 tab_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 demod_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define dprintk if (debug) printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEMOD_VES1893 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DEMOD_VES1993 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static u8 init_1893_tab [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u8 init_1993_tab [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x00, 0x00, 0x0e, 0x80, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u8 init_1893_wtab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 1,1,1,0,1,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static u8 init_1993_wtab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 1,1,1,0,1,1,1,1, 1,1,1,1,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 buf [] = { 0x00, reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 b0 [] = { 0x00, reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 b1 [] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = i2c_transfer (state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret != 2) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ves1x93_clr_bit (struct ves1x93_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int ves1x93_set_inversion(struct ves1x93_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum fe_spectral_inversion inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * inversion on/off are interchanged because i and q seem to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * be swapped on the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) val = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int ves1x93_set_fec(struct ves1x93_state *state, enum fe_code_rate fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (fec == FEC_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ves1x93_writereg (state, 0x0d, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else if (fec < FEC_1_2 || fec > FEC_8_9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static enum fe_code_rate ves1x93_get_fec(struct ves1x93_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 BDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 ADCONF, FCONF, FNR, AGCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 BDRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 FIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dprintk("%s: srate == %d\n", __func__, (unsigned int) srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (srate > state->config->xin/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) srate = state->config->xin/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (srate < 500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) srate = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MUL (1UL<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FIN = (state->config->xin + 6000) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tmp = srate << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ratio = tmp / FIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tmp = (tmp % FIN) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ratio = (ratio << 8) + tmp / FIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tmp = (tmp % FIN) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ratio = (ratio << 8) + tmp / FIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FNR = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ratio < MUL/3) FNR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ratio < (MUL*11)/50) FNR = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ratio < MUL/6) FNR = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ratio < MUL/9) FNR = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ratio < MUL/12) FNR = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ratio < (MUL*11)/200) FNR = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ratio < MUL/24) FNR = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ratio < (MUL*27)/1000) FNR = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ratio < MUL/48) FNR = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ratio < (MUL*137)/10000) FNR = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (FNR == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ADCONF = 0x89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FCONF = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FNR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ADCONF = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dprintk("FNR= %d\n", FNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dprintk("ratio= %08x\n", (unsigned int) ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dprintk("BDR= %08x\n", (unsigned int) BDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dprintk("BDRI= %02x\n", (unsigned int) BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (BDRI > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) BDRI = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ves1x93_writereg (state, 0x06, 0xff & BDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ves1x93_writereg (state, 0x09, BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ves1x93_writereg (state, 0x20, ADCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ves1x93_writereg (state, 0x21, FCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) AGCR = state->init_1x93_tab[0x05];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (state->config->invert_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) AGCR |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (srate < 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) AGCR |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) AGCR &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ves1x93_writereg (state, 0x05, AGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* ves1993 hates this, will lose lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (state->demod_type != DEMOD_VES1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ves1x93_clr_bit (state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int ves1x93_init (struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dprintk("%s: init chip\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 0; i < state->tab_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (state->init_1x93_wtab[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val = state->init_1x93_tab[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ves1x93_writereg (state, i, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int ves1x93_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ves1x93_writereg (state, 0x1f, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ves1x93_writereg (state, 0x1f, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ves1x93_writereg (state, 0x1f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int ves1x93_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 sync = ves1x93_readreg (state, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * The ves1893 sometimes returns sync values that make no sense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * because, e.g., the SIGNAL bit is 0, while some of the higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * bits are 1 (and how can there be a CARRIER w/o a SIGNAL?).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Tests showed that the VITERBI and SYNC bits are returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * reliably, while the SIGNAL and CARRIER bits ar sometimes wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * If such a case occurs, we read the value again, until we get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * valid value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int maxtry = 10; /* just for safety - let's not get stuck here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sync = ves1x93_readreg (state, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (sync & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (sync & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (sync & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (sync & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if ((sync & 0x1f) == 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *ber = ves1x93_readreg (state, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *ber |= (ves1x93_readreg (state, 0x16) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *ber *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 signal = ~ves1x93_readreg (state, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *strength = (signal << 8) | signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 _snr = ~ves1x93_readreg (state, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *snr = (_snr << 8) | _snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *ucblocks = ves1x93_readreg (state, 0x18) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (*ucblocks == 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *ucblocks = 0xffffffff; /* counter overflow... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ves1x93_writereg (state, 0x18, 0x80); /* dto. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int ves1x93_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ves1x93_set_inversion (state, p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ves1x93_set_fec(state, p->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ves1x93_set_symbolrate(state, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) state->inversion = p->inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) state->frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int ves1x93_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int afc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) afc = (afc * (int)(p->symbol_rate/1000/8))/16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) p->frequency = state->frequency - afc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * inversion indicator is only valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * if auto inversion was used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (state->inversion == INVERSION_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) INVERSION_OFF : INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) p->fec_inner = ves1x93_get_fec(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* XXX FIXME: timing offset !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int ves1x93_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ves1x93_writereg (state, 0x00, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void ves1x93_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct ves1x93_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ves1x93_writereg(state, 0x00, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ves1x93_writereg(state, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct dvb_frontend_ops ves1x93_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct ves1x93_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 identity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) state->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* check if the demod is there + identify it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) identity = ves1x93_readreg(state, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (identity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case 0xdc: /* VES1893A rev1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) printk("ves1x93: Detected ves1893a rev1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) state->demod_type = DEMOD_VES1893;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) state->init_1x93_tab = init_1893_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) state->init_1x93_wtab = init_1893_wtab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) state->tab_size = sizeof(init_1893_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case 0xdd: /* VES1893A rev2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) printk("ves1x93: Detected ves1893a rev2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) state->demod_type = DEMOD_VES1893;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) state->init_1x93_tab = init_1893_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) state->init_1x93_wtab = init_1893_wtab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) state->tab_size = sizeof(init_1893_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 0xde: /* VES1993 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) printk("ves1x93: Detected ves1993\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) state->demod_type = DEMOD_VES1993;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) state->init_1x93_tab = init_1993_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) state->init_1x93_wtab = init_1993_wtab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) state->tab_size = sizeof(init_1993_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct dvb_frontend_ops ves1x93_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "VLSI VES1x93 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .frequency_stepsize_hz = 125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .frequency_tolerance_hz = 29500 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* .symbol_rate_tolerance = ???,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) FE_CAN_QPSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .release = ves1x93_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .init = ves1x93_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .sleep = ves1x93_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .i2c_gate_ctrl = ves1x93_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .set_frontend = ves1x93_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .get_frontend = ves1x93_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .read_status = ves1x93_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .read_ber = ves1x93_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .read_signal_strength = ves1x93_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .read_snr = ves1x93_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .read_ucblocks = ves1x93_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .set_voltage = ves1x93_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_AUTHOR("Ralph Metzler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) EXPORT_SYMBOL(ves1x93_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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