^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) VES1820 - Single Chip Cable Channel Receiver driver module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ves1820.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct ves1820_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const struct ves1820_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* private demodulator data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static u8 ves1820_inittab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x69, 0x6A, 0x93, 0x1A, 0x12, 0x46, 0x26, 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0x00, 0x00, 0x00, 0x00, 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 buf[] = { 0x00, reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) printk("ves1820: %s(): writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return (ret != 1) ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 b0[] = { 0x00, reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) printk("ves1820: %s(): readreg error (reg == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int ves1820_setup_reg0(struct ves1820_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 reg0, enum fe_spectral_inversion inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg0 |= state->reg0 & 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (INVERSION_ON == inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!state->config->invert) reg0 |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else reg0 &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else if (INVERSION_OFF == inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!state->config->invert) reg0 &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else reg0 |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ves1820_writereg(state, 0x00, reg0 & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ves1820_writereg(state, 0x00, reg0 | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) state->reg0 = reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) s32 BDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) s32 BDRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) s16 SFIL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 NDEC = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u64 fptmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u64 fpxin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (symbolrate > state->config->xin / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) symbolrate = state->config->xin / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (symbolrate < 500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) symbolrate = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (symbolrate < state->config->xin / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) NDEC = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (symbolrate < state->config->xin / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) NDEC = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (symbolrate < state->config->xin / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) NDEC = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* yeuch! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) fpxin = state->config->xin * 10ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) fptmp = fpxin; do_div(fptmp, 123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SFIL = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) fptmp = fpxin; do_div(fptmp, 160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SFIL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) fptmp = fpxin; do_div(fptmp, 246);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SFIL = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) fptmp = fpxin; do_div(fptmp, 320);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SFIL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) fptmp = fpxin; do_div(fptmp, 492);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SFIL = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) fptmp = fpxin; do_div(fptmp, 640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SFIL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fptmp = fpxin; do_div(fptmp, 984);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (symbolrate < fptmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SFIL = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) fin = state->config->xin >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) symbolrate <<= NDEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ratio = (symbolrate << 4) / fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tmp = ((symbolrate << 4) % fin) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ratio = (ratio << 8) + tmp / fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tmp = (tmp % fin) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ratio = (ratio << 8) + DIV_ROUND_CLOSEST(tmp, fin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BDR = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (BDRI > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BDRI = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) NDEC = (NDEC << 6) | ves1820_inittab[0x03];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ves1820_writereg(state, 0x03, NDEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ves1820_writereg(state, 0x0a, BDR & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ves1820_writereg(state, 0x0d, BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ves1820_writereg(state, 0x0e, SFIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int ves1820_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ves1820_writereg(state, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < sizeof(ves1820_inittab); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ves1820_writereg(state, i, ves1820_inittab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (state->config->selagc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ves1820_writereg(state, 0x34, state->pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int ves1820_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const u8 reg0x01[] = { 140, 140, 106, 100, 92 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const u8 reg0x05[] = { 135, 100, 70, 54, 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int real_qam = p->modulation - QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (real_qam < 0 || real_qam > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ves1820_set_symbolrate(state, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ves1820_writereg(state, 0x34, state->pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ves1820_writereg(state, 0x01, reg0x01[real_qam]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ves1820_writereg(state, 0x05, reg0x05[real_qam]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ves1820_writereg(state, 0x08, reg0x08[real_qam]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ves1820_writereg(state, 0x09, reg0x09[real_qam]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ves1820_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sync = ves1820_readreg(state, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (sync & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (sync & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (sync & 2) /* XXX FIXME! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (sync & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (sync & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 _ber = ves1820_readreg(state, 0x14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (ves1820_readreg(state, 0x15) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *ber = 10 * _ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 gain = ves1820_readreg(state, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *strength = (gain << 8) | gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 quality = ~ves1820_readreg(state, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *snr = (quality << 8) | quality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (*ucblocks == 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *ucblocks = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* reset uncorrected block counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int ves1820_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) s8 afc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) sync = ves1820_readreg(state, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) afc = ves1820_readreg(state, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (verbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* AFC only valid when carrier has been recovered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->symbol_rate * afc) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!state->config->invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) p->fec_inner = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) p->frequency = ((p->frequency + 31250) / 62500) * 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (sync & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) p->frequency -= ((s32) p->symbol_rate * afc) >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int ves1820_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ves1820_writereg(state, 0x00, 0x80); /* standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fesettings->min_delay_ms = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void ves1820_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct ves1820_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct dvb_frontend_ops ves1820_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct i2c_adapter* i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct ves1820_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) state->reg0 = ves1820_inittab[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) state->pwm = pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) printk("ves1820: pwm=0x%02x\n", state->pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct dvb_frontend_ops ves1820_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .delsys = { SYS_DVBC_ANNEX_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "VLSI VES1820 DVB-C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .frequency_min_hz = 47 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .caps = FE_CAN_QAM_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FE_CAN_QAM_32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FE_CAN_QAM_128 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FE_CAN_QAM_256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FE_CAN_FEC_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .release = ves1820_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .init = ves1820_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .sleep = ves1820_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .set_frontend = ves1820_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .get_frontend = ves1820_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .get_tune_settings = ves1820_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .read_status = ves1820_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .read_ber = ves1820_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .read_signal_strength = ves1820_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .read_snr = ves1820_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .read_ucblocks = ves1820_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) module_param(verbose, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) EXPORT_SYMBOL(ves1820_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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