^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Infineon tua6100 pll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 2006 Andrew de Quincey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on code found in budget-av.c, which has the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Compiled from various sources by Michael Hunold <michael@mihu.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * CI interface support (c) 2004 Olivier Gournet <ogournet@anevia.com> &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Andrew de Quincey <adq_dvb@lidskialf.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2002 Ralph Metzler <rjkm@metzlerbros.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1999-2002 Ralph Metzler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * & Marcus Metzler for convergence integrated media GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "tua6100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct tua6100_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* i2c details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void tua6100_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int tua6100_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct tua6100_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 reg0[] = { 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct i2c_msg msg = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if ((ret = i2c_transfer (priv->i2c, &msg, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) printk("%s: i2c error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return (ret == 1) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int tua6100_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct tua6100_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 reg0[] = { 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 reg2[] = { 0x02, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2c_msg msg0 = { .addr = priv->i2c_address, .flags = 0, .buf = reg0, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define _R_VAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define _P_VAL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define _ri 4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) // setup register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (c->frequency < 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg0[1] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg0[1] = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) // setup register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (c->frequency < 1630000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg1[1] = 0x2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg1[1] = 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (_P_VAL == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg1[1] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (c->frequency >= 1525000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg1[1] |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) // register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg2[1] = (_R_VAL >> 8) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg2[2] = _R_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (c->frequency < 1455000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg2[1] |= 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else if (c->frequency < 1630000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg2[1] |= 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg2[1] |= 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * The N divisor ratio (note: c->frequency is in kHz, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * need it in Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) prediv = (c->frequency * _R_VAL) / (_ri / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) div = prediv / _P_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg1[1] |= (div >> 9) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg1[2] = div >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg1[3] = (div << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) priv->frequency = ((div * _P_VAL) * (_ri / 1000)) / _R_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) // Finally, calculate and store the value for A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #undef _R_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #undef _P_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #undef _ri
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (i2c_transfer(priv->i2c, &msg0, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (i2c_transfer(priv->i2c, &msg2, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (i2c_transfer(priv->i2c, &msg1, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int tua6100_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct tua6100_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct dvb_tuner_ops tua6100_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "Infineon TUA6100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .frequency_step_hz = 1 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .release = tua6100_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .sleep = tua6100_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .set_params = tua6100_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .get_frequency = tua6100_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct dvb_frontend *tua6100_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct tua6100_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 b1 [] = { 0x80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 b2 [] = { 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct i2c_msg msg [] = { { .addr = addr, .flags = 0, .buf = b1, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .addr = addr, .flags = I2C_M_RD, .buf = b2, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = i2c_transfer (i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) priv = kzalloc(sizeof(struct tua6100_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) priv->i2c_address = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) memcpy(&fe->ops.tuner_ops, &tua6100_tuner_ops, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EXPORT_SYMBOL(tua6100_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_DESCRIPTION("DVB tua6100 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_AUTHOR("Andrew de Quincey");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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