^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Montage Technology TS2020 - Silicon Tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2009-2012 TurboSight.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ts2020.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TS2020_XTAL_FREQ 27000 /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FREQ_OFFSET_LOW_SYM_RATE 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct ts2020_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mutex regmap_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct regmap_config regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct delayed_work stat_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int (*get_agc_pwm)(struct dvb_frontend *fe, u8 *_agc_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* i2c details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bool loop_through:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 clk_out:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 clk_out_div:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool dont_poll:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 frequency_div; /* LO output divider switch frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 frequency_khz; /* actual used LO frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TS2020_M88TS2020 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TS2020_M88TS2022 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct ts2020_reg_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void ts2020_stat_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void ts2020_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct i2c_client *client = priv->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) i2c_unregister_device(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int ts2020_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (priv->tuner == TS2020_M88TS2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8tmp = 0x0a; /* XXX: probably wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8tmp = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = regmap_write(priv->regmap, u8tmp, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* stop statistics polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!priv->dont_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) cancel_delayed_work_sync(&priv->stat_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int ts2020_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (priv->tuner == TS2020_M88TS2020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_write(priv->regmap, 0x42, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) regmap_write(priv->regmap, 0x05, priv->clk_out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regmap_write(priv->regmap, 0x20, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) regmap_write(priv->regmap, 0x07, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) regmap_write(priv->regmap, 0x11, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_write(priv->regmap, 0x60, 0xf9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) regmap_write(priv->regmap, 0x08, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regmap_write(priv->regmap, 0x00, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct ts2020_reg_val reg_vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {0x7d, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {0x7c, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {0x7a, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {0x3b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {0x63, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {0x61, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {0x22, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {0x30, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {0x20, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {0x24, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {0x12, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_write(priv->regmap, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) regmap_write(priv->regmap, 0x00, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) switch (priv->clk_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case TS2020_CLK_OUT_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8tmp = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case TS2020_CLK_OUT_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8tmp = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_write(priv->regmap, 0x05, priv->clk_out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case TS2020_CLK_OUT_ENABLED_XTALOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8tmp = 0x6c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8tmp = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_write(priv->regmap, 0x42, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (priv->loop_through)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8tmp = 0xec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8tmp = 0x6c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_write(priv->regmap, 0x62, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (i = 0; i < ARRAY_SIZE(reg_vals); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) regmap_write(priv->regmap, reg_vals[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg_vals[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Initialise v5 stats here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) c->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) c->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) c->strength.stat[0].uvalue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Start statistics polling by invoking the work function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ts2020_stat_work(&priv->stat_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = regmap_write(priv->regmap, 0x51, 0x1f - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret |= regmap_write(priv->regmap, 0x51, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret |= regmap_write(priv->regmap, 0x50, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret |= regmap_write(priv->regmap, 0x50, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct ts2020_priv *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = regmap_read(dev->regmap, 0x3d, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) utmp &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (utmp < 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) utmp = 0xa1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else if (utmp == 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) utmp = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) utmp = 0xf9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) regmap_write(dev->regmap, 0x60, utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = ts2020_tuner_gate_ctrl(fe, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int ts2020_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 f3db, gdiv28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u16 u16tmp, value, lpf_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 buf[3], reg10, lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int frequency_khz = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Integer-N PLL synthesizer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * kHz is used for all calculations to keep calculations within 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) f_ref_khz = TS2020_XTAL_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* select LO output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (frequency_khz < priv->frequency_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) div_out = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg10 = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) div_out = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) reg10 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) f_vco_khz = frequency_khz * div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pll_n = f_vco_khz * div_ref / f_ref_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pll_n += pll_n % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) priv->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_debug("frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) priv->frequency_khz, priv->frequency_khz - c->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) f_vco_khz, pll_n, div_ref, div_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (priv->tuner == TS2020_M88TS2020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) lpf_coeff = 2766;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg10 |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = regmap_write(priv->regmap, 0x10, reg10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) lpf_coeff = 3200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg10 |= 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = regmap_write(priv->regmap, 0x10, reg10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret |= regmap_write(priv->regmap, 0x11, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16tmp = pll_n - 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) buf[0] = (u16tmp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) buf[1] = (u16tmp >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) buf[2] = div_ref - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret |= regmap_write(priv->regmap, 0x01, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret |= regmap_write(priv->regmap, 0x02, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret |= regmap_write(priv->regmap, 0x03, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret |= ts2020_tuner_gate_ctrl(fe, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Tuner RF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (priv->tuner == TS2020_M88TS2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret |= ts2020_set_tuner_rf(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret |= regmap_write(priv->regmap, 0x04, gdiv28 & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (priv->tuner == TS2020_M88TS2022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = regmap_write(priv->regmap, 0x25, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret |= regmap_write(priv->regmap, 0x27, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret |= regmap_write(priv->regmap, 0x41, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret |= regmap_write(priv->regmap, 0x08, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regmap_read(priv->regmap, 0x26, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) value = utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) f3db = (c->bandwidth_hz / 1000 / 2) + 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) f3db += FREQ_OFFSET_LOW_SYM_RATE; /* FIXME: ~always too wide filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) f3db = clamp(f3db, 7000U, 40000U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) gdiv28 = gdiv28 * 207 / (value * 2 + 151);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mlpf_max = gdiv28 * 135 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mlpf_min = gdiv28 * 78 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (mlpf_max > 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mlpf_max = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) (TS2020_XTAL_FREQ / 1000) + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (nlpf > 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) nlpf = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (nlpf < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) nlpf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * lpf_coeff * 2 / f3db + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (lpf_mxdiv < mlpf_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) nlpf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * lpf_coeff * 2 / f3db + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (lpf_mxdiv > mlpf_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) lpf_mxdiv = mlpf_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = regmap_write(priv->regmap, 0x04, lpf_mxdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret |= regmap_write(priv->regmap, 0x06, nlpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret |= ts2020_tuner_gate_ctrl(fe, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) msleep(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return (ret < 0) ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *frequency = priv->frequency_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int ts2020_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *frequency = 0; /* Zero-IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Get the tuner gain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @fe: The front end for which we're determining the gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @v_agc: The voltage of the AGC from the demodulator (0-2600mV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @_gain: Where to store the gain (in 0.001dB units)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Returns 0 or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int ts2020_read_tuner_gain(struct dvb_frontend *fe, unsigned v_agc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __s64 *_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long gain1, gain2, gain3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Read the RF gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = regmap_read(priv->regmap, 0x3d, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) gain1 = utmp & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Read the baseband gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = regmap_read(priv->regmap, 0x21, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) gain2 = utmp & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (priv->tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case TS2020_M88TS2020:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) gain1 = clamp_t(long, gain1, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) gain2 = clamp_t(long, gain2, 0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) v_agc = clamp_t(long, v_agc, 400, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *_gain = -((__s64)gain1 * 2330 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) gain2 * 3500 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) v_agc * 24 / 10 * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* gain in range -19600 to -116850 in units of 0.001dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case TS2020_M88TS2022:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = regmap_read(priv->regmap, 0x66, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) gain3 = (utmp >> 3) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) gain1 = clamp_t(long, gain1, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) gain2 = clamp_t(long, gain2, 2, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) gain3 = clamp_t(long, gain3, 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) v_agc = clamp_t(long, v_agc, 600, 1600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *_gain = -((__s64)gain1 * 2650 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) gain2 * 3380 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) gain3 * 2850 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) v_agc * 176 / 100 * 10 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 30000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* gain in range -47320 to -158950 in units of 0.001dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Get the AGC information from the demodulator and use that to calculate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * tuner gain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int ts2020_get_tuner_gain(struct dvb_frontend *fe, __s64 *_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int v_agc = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 agc_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Read the AGC PWM rate from the demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (priv->get_agc_pwm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = priv->get_agc_pwm(fe, &agc_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) switch (priv->tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case TS2020_M88TS2020:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) v_agc = (int)agc_pwm * 20 - 1166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case TS2020_M88TS2022:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) v_agc = (int)agc_pwm * 16 - 670;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (v_agc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) v_agc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ts2020_read_tuner_gain(fe, v_agc, _gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Gather statistics on a regular basis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void ts2020_stat_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct ts2020_priv *priv = container_of(work, struct ts2020_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) stat_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct i2c_client *client = priv->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct dtv_frontend_properties *c = &priv->fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = ts2020_get_tuner_gain(priv->fe, &c->strength.stat[0].svalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) c->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!priv->dont_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) schedule_delayed_work(&priv->stat_work, msecs_to_jiffies(2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Read TS2020 signal strength in v3 format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int ts2020_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u16 *_signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct ts2020_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __s64 gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (priv->dont_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ts2020_stat_work(&priv->stat_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (c->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *_signal_strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) gain = c->strength.stat[0].svalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Calculate the signal strength based on the total gain of the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (gain < -85000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* 0%: no signal or weak signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) else if (gain < -65000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* 0% - 60%: weak signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) strength = 0 + div64_s64((85000 + gain) * 3, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) else if (gain < -45000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* 60% - 90%: normal signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) strength = 60 + div64_s64((65000 + gain) * 3, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* 90% - 99%: strong signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) strength = 90 + div64_s64((45000 + gain), 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *_signal_strength = strength * 65535 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct dvb_tuner_ops ts2020_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = "TS2020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .frequency_max_hz = 2150 * MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .init = ts2020_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .release = ts2020_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .sleep = ts2020_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .set_params = ts2020_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .get_frequency = ts2020_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .get_if_frequency = ts2020_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .get_rf_strength = ts2020_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const struct ts2020_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct i2c_board_info board_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* This is only used by ts2020_probe() so can be on the stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct ts2020_config pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) memcpy(&pdata, config, sizeof(pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pdata.fe = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pdata.attach_in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) memset(&board_info, 0, sizeof(board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) strscpy(board_info.type, "ts2020", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) board_info.addr = config->tuner_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) board_info.platform_data = &pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) client = i2c_new_client_device(i2c, &board_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!i2c_client_has_driver(client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) EXPORT_SYMBOL(ts2020_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * We implement own regmap locking due to legacy DVB attach which uses frontend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * gate control callback to control I2C bus access. We can open / close gate and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * serialize whole open / I2C-operation / close sequence at the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void ts2020_regmap_lock(void *__dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ts2020_priv *dev = __dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mutex_lock(&dev->regmap_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (dev->fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev->fe->ops.i2c_gate_ctrl(dev->fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void ts2020_regmap_unlock(void *__dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct ts2020_priv *dev = __dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (dev->fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev->fe->ops.i2c_gate_ctrl(dev->fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_unlock(&dev->regmap_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int ts2020_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct ts2020_config *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct dvb_frontend *fe = pdata->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ts2020_priv *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) char *chip_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* create regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mutex_init(&dev->regmap_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev->regmap_config.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev->regmap_config.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev->regmap_config.lock = ts2020_regmap_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev->regmap_config.unlock = ts2020_regmap_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev->regmap_config.lock_arg = dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (IS_ERR(dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = PTR_ERR(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev->i2c = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev->i2c_address = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev->loop_through = pdata->loop_through;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev->clk_out = pdata->clk_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev->clk_out_div = pdata->clk_out_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev->dont_poll = pdata->dont_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev->frequency_div = pdata->frequency_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev->fe = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev->get_agc_pwm = pdata->get_agc_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fe->tuner_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) INIT_DELAYED_WORK(&dev->stat_work, ts2020_stat_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* check if the tuner is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = regmap_read(dev->regmap, 0x00, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if ((utmp & 0x03) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = regmap_write(dev->regmap, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) usleep_range(2000, 50000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = regmap_write(dev->regmap, 0x00, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) usleep_range(2000, 50000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = regmap_read(dev->regmap, 0x00, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_dbg(&client->dev, "chip_id=%02x\n", utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) switch (utmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case 0x41:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case 0x81:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev->tuner = TS2020_M88TS2020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) chip_str = "TS2020";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!dev->frequency_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev->frequency_div = 1060000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case 0xc3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case 0x83:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev->tuner = TS2020_M88TS2022;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) chip_str = "TS2022";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!dev->frequency_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev->frequency_div = 1103000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (dev->tuner == TS2020_M88TS2022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) switch (dev->clk_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case TS2020_CLK_OUT_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8tmp = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case TS2020_CLK_OUT_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u8tmp = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = regmap_write(dev->regmap, 0x05, dev->clk_out_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case TS2020_CLK_OUT_ENABLED_XTALOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u8tmp = 0x6c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = regmap_write(dev->regmap, 0x42, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (dev->loop_through)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8tmp = 0xec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8tmp = 0x6c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = regmap_write(dev->regmap, 0x62, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = regmap_write(dev->regmap, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto err_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "Montage Technology %s successfully identified\n", chip_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!pdata->attach_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) fe->ops.tuner_ops.release = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) i2c_set_clientdata(client, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) err_regmap_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_exit(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int ts2020_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct ts2020_priv *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* stop statistics polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!dev->dont_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) cancel_delayed_work_sync(&dev->stat_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) regmap_exit(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const struct i2c_device_id ts2020_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {"ts2020", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {"ts2022", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MODULE_DEVICE_TABLE(i2c, ts2020_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct i2c_driver ts2020_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .name = "ts2020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .probe = ts2020_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .remove = ts2020_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .id_table = ts2020_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) module_i2c_driver(ts2020_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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