^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) TDA8261 8PSK/QPSK tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) Manu Abraham (abraham.manu@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "tda8261.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct tda8261_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const struct tda8261_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* state cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int tda8261_read(struct tda8261_state *state, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const struct tda8261_config *config = state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pr_err("%s: read error, err=%d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int tda8261_write(struct tda8261_state *state, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct tda8261_config *config = state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pr_err("%s: write error, err=%d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int tda8261_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct tda8261_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if ((err = tda8261_read(state, &result)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pr_err("%s: I/O Error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if ((result >> 6) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_debug("%s: Tuner Phase Locked\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const u32 div_tab[] = { 2000, 1000, 500, 250, 125 }; /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int tda8261_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tda8261_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *frequency = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int tda8261_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct tda8261_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct tda8261_config *config = state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 frequency, N, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * N = Max VCO Frequency / Channel Spacing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Max VCO Frequency = VCO frequency + (channel spacing - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * (to account for half channel spacing on either side)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if ((frequency < 950000) || (frequency > 2150000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_warn("%s: Frequency beyond limits, frequency=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __func__, frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) N = (frequency + (div_tab[config->step_size] - 1)) / div_tab[config->step_size];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pr_debug("%s: Step size=%d, Divider=%d, PG=0x%02x (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __func__, config->step_size, div_tab[config->step_size], N, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) buf[0] = (N >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) buf[1] = N & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (frequency < 1450000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else if (frequency < 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) buf[3] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else if (frequency < 2150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) buf[3] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Set params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) err = tda8261_write(state, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pr_err("%s: I/O Error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* sleep for some time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pr_debug("%s: Waiting to Phase LOCK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* check status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if ((err = tda8261_get_status(fe, &status)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pr_err("%s: I/O Error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_debug("%s: Tuner Phase locked: status=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) state->frequency = frequency; /* cache successful state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_debug("%s: No Phase lock: status=%d\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void tda8261_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tda8261_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct dvb_tuner_ops tda8261_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "TDA8261",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .set_params = tda8261_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .get_frequency = tda8261_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .get_status = tda8261_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .release = tda8261_release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const struct tda8261_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct tda8261_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if ((state = kzalloc(sizeof (struct tda8261_state), GFP_KERNEL)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) state->fe = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fe->ops.tuner_ops = tda8261_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) fe->ops.tuner_ops.info.frequency_step_hz = div_tab[config->step_size] * kHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pr_info("%s: Attaching TDA8261 8PSK/QPSK tuner\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EXPORT_SYMBOL(tda8261_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_AUTHOR("Manu Abraham");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_DESCRIPTION("TDA8261 8PSK/QPSK Tuner");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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