Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Driver for Philips TDA8083 based QPSK Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     Copyright (C) 2001 Convergence Integrated Media GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)     written by Ralph Metzler <ralph@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)     adoption to the new DVB frontend API and diagnostic ioctl's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)     by Holger Waechtler <holger@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "tda8083.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct tda8083_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	const struct tda8083_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		if (debug) printk(KERN_DEBUG "tda8083: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static u8 tda8083_init_tab [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	0x04, 0x00, 0x4a, 0x79, 0x04, 0x00, 0xff, 0xea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	0x48, 0x42, 0x79, 0x60, 0x70, 0x52, 0x9a, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	0x0e, 0x10, 0xf2, 0xa7, 0x93, 0x0b, 0x05, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	0x9d, 0x00, 0x42, 0x80, 0x00, 0x60, 0x40, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	0x00, 0x75, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	0x00, 0x00, 0x00, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int tda8083_writereg (struct tda8083_state* state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u8 buf [] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		dprintk ("%s: writereg error (reg %02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			__func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return (ret != 1) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int tda8083_readregs (struct tda8083_state* state, u8 reg1, u8 *b, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			   { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		dprintk ("%s: readreg error (reg %02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			__func__, reg1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return ret == 2 ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static inline u8 tda8083_readreg (struct tda8083_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	tda8083_readregs (state, reg, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int tda8083_set_inversion(struct tda8083_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				 enum fe_spectral_inversion inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/*  XXX FIXME: implement other modes than FEC_AUTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (inversion == INVERSION_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int tda8083_set_fec(struct tda8083_state *state, enum fe_code_rate fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (fec == FEC_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return tda8083_writereg (state, 0x07, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (fec >= FEC_1_2 && fec <= FEC_8_9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return tda8083_writereg (state, 0x07, 1 << (FEC_8_9 - fec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static enum fe_code_rate tda8083_get_fec(struct tda8083_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	static enum fe_code_rate fec_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		FEC_8_9, FEC_1_2, FEC_2_3, FEC_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		FEC_4_5, FEC_5_6, FEC_6_7, FEC_7_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	index = tda8083_readreg(state, 0x0e) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return fec_tab [index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int tda8083_set_symbolrate (struct tda8083_state* state, u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (srate > 32000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		srate = 32000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (srate < 500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		srate = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (srate < 24000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		filter = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (srate < 16000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		filter = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	tmp = 31250 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ratio = tmp / srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tmp = (tmp % srate) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ratio = (ratio << 8) + tmp / srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	tmp = (tmp % srate) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	ratio = (ratio << 8) + tmp / srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	dprintk("tda8083: ratio == %08x\n", (unsigned int) ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tda8083_writereg (state, 0x05, filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tda8083_writereg (state, 0x02, (ratio >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	tda8083_writereg (state, 0x03, (ratio >>  8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tda8083_writereg (state, 0x04, (ratio      ) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	tda8083_writereg (state, 0x00, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tda8083_writereg (state, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void tda8083_wait_diseqc_fifo (struct tda8083_state* state, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned long start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	while (jiffies - start < timeout &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	       !(tda8083_readreg(state, 0x02) & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int tda8083_set_tone(struct tda8083_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			    enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tda8083_writereg (state, 0x26, 0xf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return tda8083_writereg (state, 0x29, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return tda8083_writereg (state, 0x29, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int tda8083_set_voltage(struct tda8083_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			       enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return tda8083_writereg (state, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return tda8083_writereg (state, 0x20, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int tda8083_send_diseqc_burst(struct tda8083_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				     enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	switch (burst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	case SEC_MINI_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		tda8083_writereg (state, 0x29, (5 << 2));  /* send burst A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case SEC_MINI_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		tda8083_writereg (state, 0x29, (7 << 2));  /* send B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	tda8083_wait_diseqc_fifo (state, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int tda8083_send_diseqc_msg(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				   struct dvb_diseqc_master_cmd *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	tda8083_writereg (state, 0x29, (m->msg_len - 3) | (1 << 2)); /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	for (i=0; i<m->msg_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		tda8083_writereg (state, 0x23 + i, m->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	tda8083_writereg (state, 0x29, (m->msg_len - 3) | (3 << 2)); /* send!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	tda8083_wait_diseqc_fifo (state, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int tda8083_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			       enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	u8 signal = ~tda8083_readreg (state, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	u8 sync = tda8083_readreg (state, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (signal > 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		*status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (sync & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		*status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (sync & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		*status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (sync & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		*status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (sync & 0x20) /* frontend can not lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		*status |= FE_TIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if ((sync & 0x1f) == 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		*status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int tda8083_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if ((ret = tda8083_readregs(state, 0x0b, buf, sizeof(buf))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	*ber = ((buf[0] & 0x1f) << 16) | (buf[1] << 8) | buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int tda8083_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u8 signal = ~tda8083_readreg (state, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	*strength = (signal << 8) | signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int tda8083_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	u8 _snr = tda8083_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	*snr = (_snr << 8) | _snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int tda8083_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	*ucblocks = tda8083_readreg(state, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (*ucblocks == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		*ucblocks = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int tda8083_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	tda8083_set_inversion (state, p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	tda8083_set_fec(state, p->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	tda8083_set_symbolrate(state, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	tda8083_writereg (state, 0x00, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	tda8083_writereg (state, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int tda8083_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/*  FIXME: get symbolrate & frequency offset...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/*p->frequency = ???;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	p->inversion = (tda8083_readreg (state, 0x0e) & 0x80) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	p->fec_inner = tda8083_get_fec(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/*p->symbol_rate = tda8083_get_symbolrate (state);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int tda8083_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	tda8083_writereg (state, 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int tda8083_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	for (i=0; i<44; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		tda8083_writereg (state, i, tda8083_init_tab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	tda8083_writereg (state, 0x00, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	tda8083_writereg (state, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int tda8083_diseqc_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				     enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	tda8083_send_diseqc_burst (state, burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	tda8083_writereg (state, 0x00, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	tda8083_writereg (state, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int tda8083_diseqc_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 				   enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	tda8083_set_tone (state, tone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	tda8083_writereg (state, 0x00, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	tda8083_writereg (state, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int tda8083_diseqc_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 				      enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	tda8083_set_voltage (state, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	tda8083_writereg (state, 0x00, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	tda8083_writereg (state, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void tda8083_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct tda8083_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct dvb_frontend_ops tda8083_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dvb_frontend* tda8083_attach(const struct tda8083_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 				    struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct tda8083_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	/* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	state = kzalloc(sizeof(struct tda8083_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	/* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	/* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	if ((tda8083_readreg(state, 0x00)) != 0x05) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	/* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	memcpy(&state->frontend.ops, &tda8083_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct dvb_frontend_ops tda8083_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.name			= "Philips TDA8083 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.frequency_min_hz	=  920 * MHz,     /* TDA8060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.frequency_max_hz	= 2200 * MHz,    /* TDA8060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.frequency_stepsize_hz	=  125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.symbol_rate_min	= 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		.symbol_rate_max	= 30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	/*      .symbol_rate_tolerance	= ???,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		.caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 			FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			FE_CAN_QPSK | FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.release = tda8083_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	.init = tda8083_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.sleep = tda8083_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.set_frontend = tda8083_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	.get_frontend = tda8083_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	.read_status = tda8083_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.read_signal_strength = tda8083_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.read_snr = tda8083_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.read_ber = tda8083_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	.read_ucblocks = tda8083_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.diseqc_send_master_cmd = tda8083_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.diseqc_send_burst = tda8083_diseqc_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.set_tone = tda8083_diseqc_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.set_voltage = tda8083_diseqc_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_DESCRIPTION("Philips TDA8083 DVB-S Demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) EXPORT_SYMBOL(tda8083_attach);