^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Driver for Philips tda10086 DVBS Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) (c) 2006 Andrew de Quincey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "tda10086.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SACLK 96000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct tda10086_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct tda10086_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* private demod data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool has_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (debug) printk(KERN_DEBUG "tda10086: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int tda10086_write_byte(struct tda10086_state *state, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 b0[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct i2c_msg msg = { .flags = 0, .buf = b0, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) msg.addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return (ret != 1) ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int tda10086_read_byte(struct tda10086_state *state, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) msg[0].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) msg[1].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* read a byte and check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val = tda10086_read_byte(state, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* mask if off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val = val & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val |= data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* write it out again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return tda10086_write_byte(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int tda10086_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 t22k_off = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (state->config->diseqc_tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) t22k_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tda10086_write_byte(state, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* misc setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tda10086_write_byte(state, 0x01, 0x94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tda10086_write_byte(state, 0x02, 0x35); /* NOTE: TT drivers appear to disable CSWP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tda10086_write_byte(state, 0x03, 0xe4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tda10086_write_byte(state, 0x04, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tda10086_write_byte(state, 0x0c, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tda10086_write_byte(state, 0x1b, 0xb0); /* noise threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tda10086_write_byte(state, 0x20, 0x89); /* misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tda10086_write_byte(state, 0x30, 0x04); /* acquisition period length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tda10086_write_byte(state, 0x32, 0x00); /* irq off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tda10086_write_byte(state, 0x31, 0x56); /* setup AFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* setup PLL (this assumes SACLK = 96MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tda10086_write_byte(state, 0x55, 0x2c); /* misc PLL setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (state->config->xtal_freq == TDA10086_XTAL_16M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tda10086_write_byte(state, 0x3a, 0x0b); /* M=12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tda10086_write_byte(state, 0x3b, 0x01); /* P=2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) tda10086_write_byte(state, 0x3a, 0x17); /* M=24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tda10086_write_byte(state, 0x3b, 0x00); /* P=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tda10086_write_mask(state, 0x55, 0x20, 0x00); /* powerup PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* setup TS interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tda10086_write_byte(state, 0x11, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) tda10086_write_byte(state, 0x12, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tda10086_write_byte(state, 0x19, 0x40); /* parallel mode A + MSBFIRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tda10086_write_byte(state, 0x56, 0x80); /* powerdown WPLL - unused in the mode we use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) tda10086_write_byte(state, 0x57, 0x08); /* bypass WPLL - unused in the mode we use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tda10086_write_byte(state, 0x10, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* setup ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tda10086_write_byte(state, 0x58, 0x61); /* ADC setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tda10086_write_mask(state, 0x58, 0x01, 0x00); /* powerup ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* setup AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tda10086_write_byte(state, 0x05, 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tda10086_write_byte(state, 0x37, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tda10086_write_byte(state, 0x3f, 0x0a); /* NOTE: flydvb varies it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tda10086_write_byte(state, 0x40, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tda10086_write_byte(state, 0x41, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tda10086_write_byte(state, 0x42, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* setup viterbi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tda10086_write_byte(state, 0x1a, 0x11); /* VBER 10^6, DVB, QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* setup carrier recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tda10086_write_byte(state, 0x3d, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* setup SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tda10086_write_byte(state, 0x36, t22k_off); /* all SEC off, 22k tone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tda10086_write_byte(state, 0x34, (((1<<19) * (22000/1000)) / (SACLK/1000)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tda10086_write_byte(state, 0x35, (((1<<19) * (22000/1000)) / (SACLK/1000)) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void tda10086_diseqc_wait(struct tda10086_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long timeout = jiffies + msecs_to_jiffies(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) while (!(tda10086_read_byte(state, 0x50) & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if(time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) printk("%s: diseqc queue not ready, command may be lost.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int tda10086_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 t22k_off = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (state->config->diseqc_tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) t22k_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tda10086_write_byte(state, 0x36, t22k_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tda10086_write_byte(state, 0x36, 0x01 + t22k_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int tda10086_send_master_cmd (struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct dvb_diseqc_master_cmd* cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 t22k_off = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (state->config->diseqc_tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) t22k_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (cmd->msg_len > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) oldval = tda10086_read_byte(state, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for(i=0; i< cmd->msg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tda10086_write_byte(state, 0x36, (0x08 + t22k_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) | ((cmd->msg_len - 1) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tda10086_diseqc_wait(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tda10086_write_byte(state, 0x36, oldval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int tda10086_send_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) enum fe_sec_mini_cmd minicmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 oldval = tda10086_read_byte(state, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 t22k_off = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (state->config->diseqc_tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) t22k_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch(minicmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case SEC_MINI_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tda10086_write_byte(state, 0x36, 0x04 + t22k_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case SEC_MINI_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tda10086_write_byte(state, 0x36, 0x06 + t22k_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tda10086_diseqc_wait(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tda10086_write_byte(state, 0x36, oldval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int tda10086_set_inversion(struct tda10086_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct dtv_frontend_properties *fe_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 invval = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dprintk ("%s %i %i\n", __func__, fe_params->inversion, state->config->invert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) switch(fe_params->inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) invval = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) invval = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) invval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tda10086_write_mask(state, 0x0c, 0xc0, invval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int tda10086_set_symbol_rate(struct tda10086_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct dtv_frontend_properties *fe_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 dfn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 afs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 byp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 reg37 = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 reg42 = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u64 big;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 bdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 bdri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 symbol_rate = fe_params->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dprintk ("%s %i\n", __func__, symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* setup the decimation and anti-aliasing filters.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (symbol_rate < SACLK / 10000 * 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dfn=4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) afs=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else if (symbol_rate < SACLK / 10000 * 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dfn=4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) afs=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } else if (symbol_rate < SACLK / 10000 * 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dfn=3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) afs=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } else if (symbol_rate < SACLK / 10000 * 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dfn=3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) afs=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else if (symbol_rate < SACLK / 10000 * 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dfn=2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) afs=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else if (symbol_rate < SACLK / 10000 * 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dfn=2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) afs=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else if (symbol_rate < SACLK / 10000 * 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dfn=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) afs=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else if (symbol_rate < SACLK / 10000 * 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dfn=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) afs=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else if (symbol_rate < SACLK / 10000 * 2200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dfn=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) afs=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else if (symbol_rate < SACLK / 10000 * 3333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dfn=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) afs=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) reg37 = 0x63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) reg42 = 0x4f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) byp=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* calculate BDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) big = (1ULL<<21) * ((u64) symbol_rate/1000ULL) * (1ULL<<dfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) big += ((SACLK/1000ULL)-1ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) do_div(big, (SACLK/1000ULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bdr = big & 0xfffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* calculate BDRI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) tmp = (1<<dfn)*(symbol_rate/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bdri = ((32 * (SACLK/1000)) + (tmp-1)) / tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tda10086_write_byte(state, 0x21, (afs << 7) | dfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tda10086_write_mask(state, 0x20, 0x08, byp << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tda10086_write_byte(state, 0x06, bdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tda10086_write_byte(state, 0x07, bdr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tda10086_write_byte(state, 0x08, bdr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tda10086_write_byte(state, 0x09, bdri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tda10086_write_byte(state, 0x37, reg37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tda10086_write_byte(state, 0x42, reg42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int tda10086_set_fec(struct tda10086_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct dtv_frontend_properties *fe_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 fecval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dprintk("%s %i\n", __func__, fe_params->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (fe_params->fec_inner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fecval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fecval = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fecval = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case FEC_4_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fecval = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fecval = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case FEC_6_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fecval = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fecval = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case FEC_8_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fecval = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fecval = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tda10086_write_byte(state, 0x0d, fecval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int tda10086_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct tda10086_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int freqoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* modify parameters for tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tda10086_write_byte(state, 0x02, 0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) state->has_lock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* set params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (fe->ops.tuner_ops.get_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fe->ops.tuner_ops.get_frequency(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* calculate the frequency offset (in *Hz* not kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) freqoff = fe_params->frequency - freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) freqoff = ((1<<16) * freqoff) / (SACLK/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tda10086_write_byte(state, 0x3d, 0x80 | ((freqoff >> 8) & 0x7f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tda10086_write_byte(state, 0x3e, freqoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if ((ret = tda10086_set_inversion(state, fe_params)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if ((ret = tda10086_set_symbol_rate(state, fe_params)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if ((ret = tda10086_set_fec(state, fe_params)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* soft reset + disable TS output until lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tda10086_write_mask(state, 0x10, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) tda10086_write_mask(state, 0x00, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) state->symbol_rate = fe_params->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) state->frequency = fe_params->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int tda10086_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct dtv_frontend_properties *fe_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u64 tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* check for invalid symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (fe_params->symbol_rate < 500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* calculate the updated frequency (note: we convert from Hz->kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tmp64 = ((u64)tda10086_read_byte(state, 0x52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) | (tda10086_read_byte(state, 0x51) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (tmp64 & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tmp64 |= 0xffffffffffff0000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tmp64 = (tmp64 * (SACLK/1000ULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) do_div(tmp64, (1ULL<<15) * (1ULL<<1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fe_params->frequency = (int) state->frequency + (int) tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* the inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val = tda10086_read_byte(state, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (val & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) switch(val & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fe_params->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) fe_params->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) fe_params->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fe_params->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) tda10086_read_byte(state, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) switch(val & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fe_params->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) fe_params->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fe_params->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fe_params->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* calculate the updated symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) tmp = tda10086_read_byte(state, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (tmp & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) tmp |= 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tmp = (tmp * 480 * (1<<1)) / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) fe_params->symbol_rate = state->symbol_rate + tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* the FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) switch(val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) fe_params->fec_inner = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) fe_params->fec_inner = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) fe_params->fec_inner = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fe_params->fec_inner = FEC_4_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) fe_params->fec_inner = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case 0x05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fe_params->fec_inner = FEC_6_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 0x06:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fe_params->fec_inner = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case 0x07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fe_params->fec_inner = FEC_8_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int tda10086_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) enum fe_status *fe_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val = tda10086_read_byte(state, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *fe_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (val & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *fe_status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (val & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) *fe_status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (val & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) *fe_status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (val & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *fe_status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (val & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *fe_status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!state->has_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) state->has_lock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* modify parameters for stable reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tda10086_write_byte(state, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int tda10086_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 _str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) _str = 0xff - tda10086_read_byte(state, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *signal = (_str << 8) | _str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int tda10086_read_snr(struct dvb_frontend* fe, u16 * snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 _snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) _snr = 0xff - tda10086_read_byte(state, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) *snr = (_snr << 8) | _snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int tda10086_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* read it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) *ucblocks = tda10086_read_byte(state, 0x18) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tda10086_write_byte(state, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tda10086_write_byte(state, 0x18, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int tda10086_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* read it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *ber |= tda10086_read_byte(state, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) *ber |= tda10086_read_byte(state, 0x16) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *ber |= (tda10086_read_byte(state, 0x17) & 0xf) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int tda10086_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) tda10086_write_mask(state, 0x00, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int tda10086_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct tda10086_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) tda10086_write_mask(state, 0x00, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tda10086_write_mask(state, 0x00, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int tda10086_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (p->symbol_rate > 20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) fesettings->min_delay_ms = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fesettings->step_size = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) fesettings->max_drift = 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else if (p->symbol_rate > 12000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) fesettings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) fesettings->step_size = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) fesettings->max_drift = 9000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else if (p->symbol_rate > 8000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) fesettings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) fesettings->step_size = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) fesettings->max_drift = 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) } else if (p->symbol_rate > 4000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fesettings->min_delay_ms = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) fesettings->step_size = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) fesettings->max_drift = 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else if (p->symbol_rate > 2000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fesettings->min_delay_ms = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) fesettings->step_size = p->symbol_rate / 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) fesettings->max_drift = 14 * fesettings->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) fesettings->min_delay_ms = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) fesettings->step_size = p->symbol_rate / 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) fesettings->max_drift = 18 * fesettings->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void tda10086_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct tda10086_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) tda10086_sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const struct dvb_frontend_ops tda10086_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .name = "Philips TDA10086 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .frequency_stepsize_hz = 125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) FE_CAN_QPSK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .release = tda10086_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .init = tda10086_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .sleep = tda10086_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .i2c_gate_ctrl = tda10086_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .set_frontend = tda10086_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .get_frontend = tda10086_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .get_tune_settings = tda10086_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .read_status = tda10086_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .read_ber = tda10086_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .read_signal_strength = tda10086_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .read_snr = tda10086_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .read_ucblocks = tda10086_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .diseqc_send_master_cmd = tda10086_send_master_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .diseqc_send_burst = tda10086_send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .set_tone = tda10086_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct dvb_frontend* tda10086_attach(const struct tda10086_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct tda10086_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) state = kzalloc(sizeof(struct tda10086_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (tda10086_read_byte(state, 0x1e) != 0xe1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) memcpy(&state->frontend.ops, &tda10086_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MODULE_DESCRIPTION("Philips TDA10086 DVB-S Demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MODULE_AUTHOR("Andrew de Quincey");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) EXPORT_SYMBOL(tda10086_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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