Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * NXP TDA10071 + Conexant CX24118A DVB-S/S2 demodulator + tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef TDA10071_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define TDA10071_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * I2C address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * 0x05, 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * struct tda10071_platform_data - Platform data for the tda10071 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * @clk: Clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * @i2c_wr_max: Max bytes I2C adapter can write at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * @ts_mode: TS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * @spec_inv: Input spectrum inversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @pll_multiplier: PLL multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * @tuner_i2c_addr: CX24118A tuner I2C address (0x14, 0x54, ...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * @get_dvb_frontend: Get DVB frontend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct tda10071_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u16 i2c_wr_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TDA10071_TS_SERIAL        0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TDA10071_TS_PARALLEL      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u8 ts_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	bool spec_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u8 pll_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u8 tuner_i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	struct dvb_frontend* (*get_dvb_frontend)(struct i2c_client *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif /* TDA10071_H */