^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Driver for Philips tda1004xh OFDM Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This driver needs external firmware. Please use the commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * "<kerneldir>/scripts/get_dvb_firmware tda10045",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * "<kerneldir>/scripts/get_dvb_firmware tda10046" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * download/extract them, and then copy them to /usr/lib/hotplug/firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * or /lib/firmware (depending on configuration of firmware hotplug).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "tda1004x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (debug) printk(KERN_DEBUG "tda1004x: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TDA1004X_CHIPID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TDA1004X_AUTO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TDA1004X_IN_CONF1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TDA1004X_IN_CONF2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TDA1004X_OUT_CONF1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TDA1004X_OUT_CONF2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TDA1004X_STATUS_CD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TDA1004X_CONFC4 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TDA1004X_DSSPARE2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TDA10045H_CODE_IN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TDA10045H_FWPAGE 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TDA1004X_SCAN_CPT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TDA1004X_DSP_CMD 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TDA1004X_DSP_ARG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TDA1004X_DSP_DATA1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TDA1004X_DSP_DATA2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TDA1004X_CONFADC1 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TDA1004X_CONFC1 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TDA10045H_S_AGC 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TDA10046H_AGC_TUN_LEVEL 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TDA1004X_SNR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TDA1004X_CONF_TS1 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TDA1004X_CONF_TS2 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TDA1004X_CBER_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TDA1004X_CBER_MSB 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TDA1004X_CBER_LSB 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TDA1004X_CVBER_LUT 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TDA1004X_VBER_MSB 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TDA1004X_VBER_MID 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TDA1004X_VBER_LSB 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TDA1004X_UNCOR 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TDA10045H_CONFPLL_P 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TDA10045H_CONFPLL_M_MSB 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TDA10045H_CONFPLL_M_LSB 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TDA10045H_CONFPLL_N 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TDA10046H_CONFPLL1 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TDA10046H_CONFPLL2 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TDA10046H_CONFPLL3 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TDA10046H_TIME_WREF1 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TDA10046H_TIME_WREF2 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TDA10046H_TIME_WREF3 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TDA10046H_TIME_WREF4 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TDA10046H_TIME_WREF5 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TDA10045H_UNSURW_MSB 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TDA10045H_UNSURW_LSB 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TDA10045H_WREF_MSB 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TDA10045H_WREF_MID 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TDA10045H_WREF_LSB 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TDA10045H_MUXOUT 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TDA1004X_CONFADC2 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TDA10045H_IOFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TDA10046H_CONF_TRISTATE1 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TDA10046H_CONF_TRISTATE2 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TDA10046H_CONF_POLARITY 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TDA10046H_FREQ_OFFSET 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TDA10046H_GPIO_OUT_SEL 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TDA10046H_GPIO_SELECT 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TDA10046H_AGC_CONF 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TDA10046H_AGC_THR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TDA10046H_AGC_RENORM 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TDA10046H_AGC_GAINS 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TDA10046H_AGC_TUN_MIN 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TDA10046H_AGC_TUN_MAX 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TDA10046H_AGC_IF_MIN 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TDA10046H_AGC_IF_MAX 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TDA10046H_FREQ_PHY2_MSB 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TDA10046H_FREQ_PHY2_LSB 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TDA10046H_CVBER_CTRL 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TDA10046H_AGC_IF_LEVEL 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TDA10046H_CODE_CPT 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TDA10046H_CODE_IN 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) msg.addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) __func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return (ret != 1) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dprintk("%s: reg=0x%x\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) msg[0].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) msg[1].addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg, b1[0], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) // read a byte and check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = tda1004x_read_byte(state, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) // mask if off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = val & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) val |= data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) // write it out again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return tda1004x_write_byteI(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) result = tda1004x_write_byteI(state, reg + i, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int tda10045h_set_bandwidth(struct tda1004x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int tda10046h_set_bandwidth(struct tda1004x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int tda10046_clk53m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if ((state->config->if_freq == TDA10046_FREQ_045) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (state->config->if_freq == TDA10046_FREQ_052))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tda10046_clk53m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tda10046_clk53m = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch (bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (tda10046_clk53m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sizeof(bandwidth_6mhz_53M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sizeof(bandwidth_6mhz_48M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (state->config->if_freq == TDA10046_FREQ_045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (tda10046_clk53m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sizeof(bandwidth_7mhz_53M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) sizeof(bandwidth_7mhz_48M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (state->config->if_freq == TDA10046_FREQ_045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (tda10046_clk53m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) sizeof(bandwidth_8mhz_53M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sizeof(bandwidth_8mhz_48M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (state->config->if_freq == TDA10046_FREQ_045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int tda1004x_do_upload(struct tda1004x_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const unsigned char *mem, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 dspCodeCounterReg, u8 dspCodeInReg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 buf[65];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* clear code counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tda1004x_write_byteI(state, dspCodeCounterReg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) fw_msg.addr = state->config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) buf[0] = dspCodeInReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) while (pos != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) // work out how much to send this time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tx_size = len - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (tx_size > 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) tx_size = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) // send the chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) memcpy(buf + 1, mem + pos, tx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) fw_msg.len = tx_size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) printk(KERN_ERR "tda1004x: Error during firmware upload\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pos += tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dprintk("%s: fw_pos=0x%x\n", __func__, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* give the DSP a chance to settle 03/10/05 Hac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int tda1004x_check_upload_ok(struct tda1004x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 data1, data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) timeout = jiffies + 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) // check upload was OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int tda10045_fwupload(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* don't re-upload unless necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (tda1004x_check_upload_ok(state) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* request the firmware, this will block until someone uploads it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* set parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tda10045h_set_bandwidth(state, 8000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) printk(KERN_INFO "tda1004x: firmware upload complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* wait for DSP to initialise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* DSPREADY doesn't seem to work on the TDA10045H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return tda1004x_check_upload_ok(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void tda10046_init_plls(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int tda10046_clk53m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if ((state->config->if_freq == TDA10046_FREQ_045) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) (state->config->if_freq == TDA10046_FREQ_052))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tda10046_clk53m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tda10046_clk53m = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if(tda10046_clk53m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if(tda10046_clk53m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Note clock frequency is handled implicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) switch (state->config->if_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case TDA10046_FREQ_045:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case TDA10046_FREQ_052:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case TDA10046_FREQ_3617:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case TDA10046_FREQ_3613:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* let the PLLs settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msleep(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int tda10046_fwupload(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret, confc4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* reset + wake up chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (state->config->xtal_freq == TDA10046_XTAL_4M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) confc4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) confc4 = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* set GPIO 1 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (state->config->gpio_config != TDA10046_GPTRI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* let the clocks recover from sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* The PLLs need to be reprogrammed after sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tda10046_init_plls(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* don't re-upload unless necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (tda1004x_check_upload_ok(state) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) For i2c normal work, we need to slow down the bus speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) However, the slow down breaks the eeprom firmware load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) So, use normal speed for eeprom booting and then restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) i2c speed after that. Tested with MSI TV @nyware A/D board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) that comes with firmware version 29 inside their eeprom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) It should also be noticed that no other I2C transfer should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) be in course while booting from eeprom, otherwise, tda10046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goes into an instable state. So, proper locking are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) at the i2c bus master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Checks if eeprom firmware went without troubles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (tda1004x_check_upload_ok(state) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* eeprom firmware didn't work. Load one manually. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (state->config->request_firmware != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* request the firmware, this will block until someone uploads it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* remain compatible to old bug: try to load with tda10045 image name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) TDA10046_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return tda1004x_check_upload_ok(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int tda1004x_encode_fec(int fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) // convert known FEC values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) switch (fec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) // unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int tda1004x_decode_fec(int tdafec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) // convert known FEC values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) switch (tdafec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) // unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (len != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return tda1004x_write_byteI(state, buf[0], buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int tda10045_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (tda10045_fwupload(fe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) printk("tda1004x: firmware upload failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) // tda setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int tda10046_init(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (tda10046_fwupload(fe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) printk("tda1004x: firmware upload failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) // tda setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) switch (state->config->agc_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case TDA10046_AGC_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case TDA10046_AGC_IFO_AUTO_NEG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case TDA10046_AGC_IFO_AUTO_POS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case TDA10046_AGC_TDA827X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (state->config->ts_mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) state->config->invert_oclk << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int tda1004x_set_fe(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) // setup auto offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) // disable agc_conf[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) // set frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) // Hardcoded to use auto as much as possible on the TDA10045 as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) // is very unreliable if AUTO mode is _not_ used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) fe_params->code_rate_HP = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) fe_params->guard_interval = GUARD_INTERVAL_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) // Set standard params.. or put them to auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if ((fe_params->code_rate_HP == FEC_AUTO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (fe_params->code_rate_LP == FEC_AUTO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (fe_params->modulation == QAM_AUTO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (fe_params->hierarchy == HIERARCHY_AUTO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) // set HP FEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) // set LP FEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* set modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) switch (fe_params->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) // set hierarchy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) switch (fe_params->hierarchy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case HIERARCHY_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case HIERARCHY_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case HIERARCHY_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case HIERARCHY_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) // set bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) switch (state->demod_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case TDA1004X_DEMOD_TDA10045:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case TDA1004X_DEMOD_TDA10046:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) // set inversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) inversion = fe_params->inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) inversion = inversion ? INVERSION_OFF : INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) // set guard interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) switch (fe_params->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case GUARD_INTERVAL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) // set transmission mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) switch (fe_params->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case TRANSMISSION_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) // start the lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) switch (state->demod_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case TDA1004X_DEMOD_TDA10045:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case TDA1004X_DEMOD_TDA10046:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int tda1004x_get_fe(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct dtv_frontend_properties *fe_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Only update the properties cache if device is locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!(status & 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) // inversion status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) fe_params->inversion = INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) fe_params->inversion = INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) // bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) switch (state->demod_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case TDA1004X_DEMOD_TDA10045:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) case 0x14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) fe_params->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case 0xdb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) fe_params->bandwidth_hz = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case 0x4f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fe_params->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case TDA1004X_DEMOD_TDA10046:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case 0x5c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case 0x54:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) fe_params->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case 0x6a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) fe_params->bandwidth_hz = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case 0x7b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case 0x70:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) fe_params->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) // FEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fe_params->code_rate_HP =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) fe_params->code_rate_LP =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) fe_params->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fe_params->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) fe_params->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) // transmission mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) fe_params->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) fe_params->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) // guard interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) fe_params->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) fe_params->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) fe_params->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) fe_params->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) // hierarchy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) fe_params->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) fe_params->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) fe_params->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) fe_params->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int tda1004x_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) enum fe_status *fe_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int cber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) int vber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) // read status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) // decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) *fe_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (status & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *fe_status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (status & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) *fe_status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (status & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) // is getting anything valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!(*fe_status & FE_HAS_VITERBI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) // read the CBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (cber == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) cber |= (status << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) // The address 0x20 should be read to cope with a TDA10046 bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) tda1004x_read_byte(state, TDA1004X_CBER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (cber != 65535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) *fe_status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) // if we DO have some valid VITERBI output, but don't already have SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) // read the VBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (vber == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) vber |= (status << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) vber |= (status & 0x0f) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) // The CVBER_LUT should be read to cope with TDA10046 hardware bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) // if RS has passed some valid TS packets, then we must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) // getting some SYNC bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (vber < 16632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) *fe_status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) // success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) // determine the register to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) switch (state->demod_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case TDA1004X_DEMOD_TDA10045:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) reg = TDA10045H_S_AGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case TDA1004X_DEMOD_TDA10046:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) reg = TDA10046H_AGC_IF_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) // read it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) tmp = tda1004x_read_byte(state, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) *signal = (tmp << 8) | tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dprintk("%s: signal=0x%x\n", __func__, *signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) // read it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) tmp = tda1004x_read_byte(state, TDA1004X_SNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) tmp = 255 - tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) *snr = ((tmp << 8) | tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dprintk("%s: snr=0x%x\n", __func__, *snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) // read the UCBLOCKS and reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) tmp &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) while (counter++ < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (tmp2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) tmp2 &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if ((tmp2 < tmp) || (tmp2 == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (tmp != 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) *ucblocks = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) *ucblocks = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) // read it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) *ber = tmp << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *ber |= (tmp << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) // The address 0x20 should be read to cope with a TDA10046 bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) tda1004x_read_byte(state, TDA1004X_CBER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dprintk("%s: ber=0x%x\n", __func__, *ber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static int tda1004x_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int gpio_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) switch (state->demod_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case TDA1004X_DEMOD_TDA10045:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) case TDA1004X_DEMOD_TDA10046:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* set outputs to tristate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* invert GPIO 1 and 3 if desired*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) gpio_conf = state->config->gpio_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (gpio_conf >= TDA10046_GP00_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) (gpio_conf & 0x0f) ^ 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct tda1004x_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return tda1004x_enable_tuner_i2c(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return tda1004x_disable_tuner_i2c(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) fesettings->min_delay_ms = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* Drift compensation makes no sense for DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) fesettings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) fesettings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static void tda1004x_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct tda1004x_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static const struct dvb_frontend_ops tda10045_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .name = "Philips TDA10045H DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .frequency_min_hz = 51 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .frequency_stepsize_hz = 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .caps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .release = tda1004x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .init = tda10045_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .sleep = tda1004x_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .write = tda1004x_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .set_frontend = tda1004x_set_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .get_frontend = tda1004x_get_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .get_tune_settings = tda1004x_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .read_status = tda1004x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .read_ber = tda1004x_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .read_signal_strength = tda1004x_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .read_snr = tda1004x_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .read_ucblocks = tda1004x_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct tda1004x_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) printk(KERN_ERR "Can't allocate memory for tda10045 state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) state->demod_type = TDA1004X_DEMOD_TDA10045;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) id = tda1004x_read_byte(state, TDA1004X_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (id != 0x25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const struct dvb_frontend_ops tda10046_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .name = "Philips TDA10046H DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .frequency_min_hz = 51 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .frequency_stepsize_hz = 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .caps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .release = tda1004x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .init = tda10046_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .sleep = tda1004x_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .write = tda1004x_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .set_frontend = tda1004x_set_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .get_frontend = tda1004x_get_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .get_tune_settings = tda1004x_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .read_status = tda1004x_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .read_ber = tda1004x_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .read_signal_strength = tda1004x_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .read_snr = tda1004x_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .read_ucblocks = tda1004x_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct tda1004x_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) printk(KERN_ERR "Can't allocate memory for tda10046 state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) state->demod_type = TDA1004X_DEMOD_TDA10046;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) id = tda1004x_read_byte(state, TDA1004X_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (id != 0x46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) EXPORT_SYMBOL(tda10045_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) EXPORT_SYMBOL(tda10046_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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