^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) NXP TDA10048HN DVB OFDM demodulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "tda10048.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Register name definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TDA10048_IDENTITY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TDA10048_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TDA10048_DSP_CODE_CPT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TDA10048_DSP_CODE_IN 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TDA10048_IN_CONF1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TDA10048_IN_CONF2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TDA10048_IN_CONF3 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TDA10048_OUT_CONF1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TDA10048_OUT_CONF2 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TDA10048_OUT_CONF3 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TDA10048_AUTO 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TDA10048_SYNC_STATUS 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TDA10048_CONF_C4_1 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TDA10048_CONF_C4_2 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TDA10048_CODE_IN_RAM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TDA10048_CHANNEL_INFO1_R 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TDA10048_CHANNEL_INFO2_R 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TDA10048_CHANNEL_INFO1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TDA10048_CHANNEL_INFO2 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TDA10048_TIME_ERROR_R 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TDA10048_TIME_ERROR 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TDA10048_FREQ_ERROR_LSB_R 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TDA10048_FREQ_ERROR_MSB_R 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TDA10048_FREQ_ERROR_LSB 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TDA10048_FREQ_ERROR_MSB 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TDA10048_IT_SEL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TDA10048_IT_STAT 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TDA10048_DSP_AD_LSB 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TDA10048_DSP_AD_MSB 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TDA10048_DSP_REG_LSB 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TDA10048_DSP_REG_MSB 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TDA10048_CONF_TRISTATE1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TDA10048_CONF_TRISTATE2 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TDA10048_CONF_POLARITY 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TDA10048_GPIO_SP_DS0 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TDA10048_GPIO_SP_DS1 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TDA10048_GPIO_SP_DS2 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TDA10048_GPIO_SP_DS3 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TDA10048_GPIO_OUT_SEL 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TDA10048_GPIO_SELECT 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TDA10048_IC_MODE 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TDA10048_CONF_XO 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TDA10048_CONF_PLL1 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TDA10048_CONF_PLL2 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TDA10048_CONF_PLL3 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TDA10048_CONF_ADC 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TDA10048_CONF_ADC_2 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TDA10048_CONF_C1_1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TDA10048_CONF_C1_3 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TDA10048_AGC_CONF 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TDA10048_AGC_THRESHOLD_LSB 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TDA10048_AGC_THRESHOLD_MSB 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TDA10048_AGC_RENORM 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TDA10048_AGC_GAINS 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TDA10048_AGC_TUN_MIN 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TDA10048_AGC_TUN_MAX 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TDA10048_AGC_IF_MIN 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TDA10048_AGC_IF_MAX 0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TDA10048_AGC_TUN_LEVEL 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TDA10048_AGC_IF_LEVEL 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TDA10048_DIG_AGC_LEVEL 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TDA10048_FREQ_PHY2_LSB 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TDA10048_FREQ_PHY2_MSB 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TDA10048_TIME_INVWREF_LSB 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TDA10048_TIME_INVWREF_MSB 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TDA10048_TIME_WREF_LSB 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TDA10048_TIME_WREF_MID1 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TDA10048_TIME_WREF_MID2 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TDA10048_TIME_WREF_MSB 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TDA10048_NP_OUT 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TDA10048_CELL_ID_LSB 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TDA10048_CELL_ID_MSB 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TDA10048_EXTTPS_ODD 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TDA10048_EXTTPS_EVEN 0xAB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TDA10048_TPS_LENGTH 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TDA10048_FREE_REG_1 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TDA10048_FREE_REG_2 0xB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TDA10048_CONF_C3_1 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TDA10048_CVBER_CTRL 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TDA10048_CBER_NMAX_LSB 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TDA10048_CBER_NMAX_MSB 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TDA10048_CBER_LSB 0xC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TDA10048_CBER_MSB 0xC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TDA10048_VBER_LSB 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TDA10048_VBER_MID 0xC9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TDA10048_VBER_MSB 0xCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TDA10048_CVBER_LUT 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TDA10048_UNCOR_CTRL 0xCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TDA10048_UNCOR_CPT_LSB 0xCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TDA10048_UNCOR_CPT_MSB 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TDA10048_SOFT_IT_C3 0xD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TDA10048_CONF_TS2 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TDA10048_CONF_TS1 0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define dprintk(level, fmt, arg...)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) do { if (debug >= level)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct tda10048_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* We'll cache and update the attach config settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct tda10048_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int fwloaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 freq_if_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 xtal_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 pll_mfactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 pll_nfactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 pll_pfactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 sample_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct init_tab {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } init_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { TDA10048_CONF_PLL1, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { TDA10048_CONF_ADC_2, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { TDA10048_CONF_C4_1, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { TDA10048_CONF_PLL1, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { TDA10048_CONF_PLL2, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { TDA10048_CONF_PLL3, 0x43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { TDA10048_FREQ_PHY2_LSB, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { TDA10048_FREQ_PHY2_MSB, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { TDA10048_TIME_WREF_LSB, 0xbd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { TDA10048_TIME_WREF_MID1, 0xe4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { TDA10048_TIME_WREF_MID2, 0xa8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { TDA10048_TIME_WREF_MSB, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { TDA10048_TIME_INVWREF_LSB, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { TDA10048_TIME_INVWREF_MSB, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { TDA10048_CONF_C4_1, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { TDA10048_CONF_C1_1, 0xa8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { TDA10048_AGC_CONF, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { TDA10048_CONF_C1_3, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { TDA10048_AGC_TUN_MIN, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { TDA10048_AGC_TUN_MAX, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { TDA10048_AGC_IF_MIN, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { TDA10048_AGC_IF_MAX, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { TDA10048_CVBER_CTRL, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { TDA10048_AGC_GAINS, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { TDA10048_CONF_XO, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { TDA10048_CONF_TS1, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { TDA10048_IC_MODE, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { TDA10048_CONF_TS2, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { TDA10048_CONF_TRISTATE1, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { TDA10048_CONF_TRISTATE2, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { TDA10048_CONF_POLARITY, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { TDA10048_CONF_C4_2, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { TDA10048_CONF_ADC, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { TDA10048_CONF_ADC_2, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { TDA10048_CONF_ADC, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { TDA10048_CONF_ADC_2, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { TDA10048_CONF_C1_1, 0xa8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { TDA10048_UNCOR_CTRL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { TDA10048_CONF_C4_2, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct pll_tab {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 clk_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 if_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } pll_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { TDA10048_CLK_4000, TDA10048_IF_36130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { TDA10048_CLK_16000, TDA10048_IF_3300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { TDA10048_CLK_16000, TDA10048_IF_3500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { TDA10048_CLK_16000, TDA10048_IF_3800 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { TDA10048_CLK_16000, TDA10048_IF_4000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { TDA10048_CLK_16000, TDA10048_IF_4300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { TDA10048_CLK_16000, TDA10048_IF_4500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { TDA10048_CLK_16000, TDA10048_IF_5000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { TDA10048_CLK_16000, TDA10048_IF_36130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .addr = config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printk("%s: writereg error (ret == %i)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return (ret != 1) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .addr = config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .addr = config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .flags = I2C_M_RD, .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) printk(KERN_ERR "%s: readreg error (ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) const u8 *data, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) buf = kmalloc(len + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *buf = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) memcpy(buf + 1, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) msg.addr = config->demod_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) msg.len = len + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dprintk(2, "%s(): write len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __func__, msg.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) printk(KERN_ERR "%s(): writereg error err %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 if_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (sample_freq_hz == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (if_hz < (sample_freq_hz / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* PHY2 = (if2/fs) * 2^15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) t = if_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) t *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) t *= 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) do_div(t, sample_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) t += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) do_div(t, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* PHY2 = ((IF1-fs)/fs) * 2^15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) t = sample_freq_hz - if_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) t *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) t *= 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) do_div(t, sample_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) t += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) do_div(t, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) t = ~t + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u64 t, z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (sample_freq_hz == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* WREF = (B / (7 * fs)) * 2^31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) t = bw * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* avoid warning: this decimal constant is unsigned only in ISO C90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* t *= 2147483648 on 32bit platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) t *= (2048 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) t *= 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) z = 7 * sample_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) do_div(t, z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) t += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) do_div(t, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u64 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (sample_freq_hz == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* INVWREF = ((7 * fs) / B) * 2^5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) t = sample_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) t *= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) t *= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) t *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) do_div(t, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) t += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) do_div(t, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int tda10048_set_bandwidth(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dprintk(1, "%s(bw=%d)\n", __func__, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Bandwidth setting may need to be adjusted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tda10048_set_wref(fe, state->sample_freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) tda10048_set_invwref(fe, state->sample_freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) state->bandwidth = bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int tda10048_set_if(struct dvb_frontend *fe, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 if_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dprintk(1, "%s(bw = %d)\n", __func__, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* based on target bandwidth and clk we calculate pll factors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if_freq_khz = config->dtv6_if_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if_freq_khz = config->dtv7_if_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if_freq_khz = config->dtv8_if_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) printk(KERN_ERR "%s() no default\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (pll_tab[i].if_freq_khz == if_freq_khz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (i == ARRAY_SIZE(pll_tab)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) printk(KERN_ERR "%s() Incorrect attach settings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Calculate the sample frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) state->sample_freq /= (state->pll_nfactor + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) state->sample_freq /= (state->pll_pfactor + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dprintk(1, "- sample_freq = %d\n", state->sample_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Update the I/F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int tda10048_firmware_upload(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 wlen = config->fwbulkwritelen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) wlen = TDA10048_BULKWRITE_200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* request the firmware, this will block and timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TDA10048_DEFAULT_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) state->i2c->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) printk(KERN_INFO "%s: firmware read %zu bytes.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) printk(KERN_INFO "%s: firmware uploading\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Put the demod into host download mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) tda10048_writereg(state, TDA10048_CONF_C4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Boot the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) tda10048_writereg(state, TDA10048_CONF_C4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Prepare for download */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Download the firmware payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) while (pos < fw->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if ((fw->size - pos) > wlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) cnt = wlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cnt = fw->size - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &fw->data[pos], cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pos += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Wait up to 250ms for the DSP to boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (cnt = 0; cnt < 250 ; cnt += 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) printk(KERN_INFO "%s: firmware uploaded\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) state->fwloaded = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) printk(KERN_ERR "%s: firmware upload failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dprintk(1, "%s(%d)\n", __func__, inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (inversion == TDA10048_INVERSION_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tda10048_writereg(state, TDA10048_CONF_C1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tda10048_writereg(state, TDA10048_CONF_C1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Retrieve the demod settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int tda10048_get_tps(struct tda10048_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Make sure the TPS regs are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val = tda10048_readreg(state, TDA10048_OUT_CONF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch ((val & 0x60) >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) p->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) p->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) p->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) switch ((val & 0x18) >> 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) p->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) p->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) p->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) p->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) switch (val & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) p->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) p->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) p->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) p->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) p->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val = tda10048_readreg(state, TDA10048_OUT_CONF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) switch (val & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) p->code_rate_LP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) p->code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) p->code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) p->code_rate_LP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) p->code_rate_LP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val = tda10048_readreg(state, TDA10048_OUT_CONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) switch ((val & 0x0c) >> 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) p->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) p->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) p->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) p->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) switch (val & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) p->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) p->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dprintk(1, "%s(%d)\n", __func__, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (config->disable_gate_access)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return tda10048_writereg(state, TDA10048_CONF_C4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return tda10048_writereg(state, TDA10048_CONF_C4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dprintk(1, "%s(%d)\n", __func__, serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Ensure pins are out of tri-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (serial) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* TODO: Support manual tuning with specific params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int tda10048_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Update the I/F pll's if the bandwidth changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (p->bandwidth_hz != state->bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tda10048_set_if(fe, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tda10048_set_bandwidth(fe, p->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Enable demod TPS auto detection and begin acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) tda10048_writereg(state, TDA10048_AUTO, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* trigger cber and vber acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Establish sane defaults and load firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int tda10048_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) init_tab[4].data = (u8)(state->pll_mfactor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) init_tab[5].data = (u8)(state->pll_nfactor) | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Apply register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) for (i = 0; i < ARRAY_SIZE(init_tab); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (state->fwloaded == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = tda10048_firmware_upload(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Set either serial or parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) tda10048_output_mode(fe, config->output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Set inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tda10048_set_inversion(fe, config->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Establish default RF values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) tda10048_set_if(fe, 8000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) tda10048_set_bandwidth(fe, 8000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Ensure we leave the gate closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) tda10048_i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dprintk(1, "%s() status =0x%02x\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (reg & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (reg & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (reg & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static u32 cber_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 cber_nmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u64 cber_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* update cber on interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) tda10048_readreg(state, TDA10048_CBER_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) tda10048_readreg(state, TDA10048_CBER_NMAX_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) cber_tmp *= 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) cber_tmp *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cber_current = (u32)cber_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* retrigger cber acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* actual cber is (*ber)/1e8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) *ber = cber_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int tda10048_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u16 *signal_strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) *signal_strength = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) v = tda10048_readreg(state, TDA10048_NP_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (v > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) *signal_strength -= (v << 8) | v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* SNR lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static struct snr_tab {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } snr_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { 1, 246 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { 2, 215 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { 3, 198 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { 4, 185 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { 5, 176 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { 6, 168 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { 7, 161 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { 8, 155 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { 9, 150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) { 10, 146 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) { 11, 141 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) { 12, 138 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) { 13, 134 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) { 14, 131 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) { 15, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) { 16, 125 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) { 17, 122 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) { 18, 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) { 19, 118 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) { 20, 115 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) { 21, 113 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) { 22, 111 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { 23, 109 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) { 24, 107 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) { 25, 106 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { 26, 104 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { 27, 102 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) { 28, 101 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { 29, 99 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) { 30, 98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) { 31, 96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) { 32, 95 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) { 33, 94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) { 34, 92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) { 35, 91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { 36, 90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { 37, 89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { 38, 88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { 39, 86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { 40, 85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { 41, 84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { 42, 83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { 43, 82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { 44, 81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { 45, 80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { 46, 79 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { 47, 78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) { 48, 77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { 49, 76 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { 50, 76 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { 51, 75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { 52, 74 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) { 53, 73 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { 54, 72 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { 56, 71 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) { 57, 70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) { 58, 69 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) { 60, 68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) { 61, 67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) { 63, 66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) { 64, 65 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { 66, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { 67, 63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { 68, 62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) { 69, 62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) { 70, 61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { 72, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) { 74, 59 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) { 75, 58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) { 77, 57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { 79, 56 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { 81, 55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { 83, 54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) { 85, 53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { 87, 52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { 89, 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { 91, 50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { 93, 49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { 95, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { 97, 47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { 100, 46 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { 102, 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { 104, 44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { 107, 43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { 109, 42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { 112, 41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { 114, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { 117, 39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { 120, 38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { 123, 37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { 125, 36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { 128, 35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { 131, 34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { 134, 33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { 138, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { 141, 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { 144, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { 147, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { 151, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { 154, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { 158, 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { 162, 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { 165, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { 169, 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { 173, 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) { 177, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { 181, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) { 186, 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) { 190, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { 194, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { 199, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { 204, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { 208, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { 213, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { 218, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { 223, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { 229, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { 234, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { 239, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { 245, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) { 251, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) { 255, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int i, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) v = tda10048_readreg(state, TDA10048_NP_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (v <= snr_tab[i].val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) *snr = snr_tab[i].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* clear the uncorrected TS packets counter when saturated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (*ucblocks == 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static int tda10048_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) & 0x20 ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return tda10048_get_tps(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int tda10048_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct dvb_frontend_tune_settings *tune)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) tune->min_delay_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void tda10048_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void tda10048_establish_defaults(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct tda10048_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct tda10048_config *config = &state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Validate/default the config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (config->dtv6_if_freq_khz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) config->dtv6_if_freq_khz = TDA10048_IF_4300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) config->dtv6_if_freq_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (config->dtv7_if_freq_khz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) config->dtv7_if_freq_khz = TDA10048_IF_4300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) config->dtv7_if_freq_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (config->dtv8_if_freq_khz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) config->dtv8_if_freq_khz = TDA10048_IF_4300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) config->dtv8_if_freq_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (config->clk_freq_khz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) config->clk_freq_khz = TDA10048_CLK_16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) config->clk_freq_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const struct dvb_frontend_ops tda10048_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct tda10048_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* setup the state and clone the config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) memcpy(&state->config, config, sizeof(*config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) state->fwloaded = config->no_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) state->bandwidth = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* check if the demod is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) memcpy(&state->frontend.ops, &tda10048_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* set pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (config->set_pll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) state->pll_mfactor = config->pll_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) state->pll_nfactor = config->pll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) state->pll_pfactor = config->pll_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) state->pll_mfactor = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) state->pll_nfactor = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) state->pll_pfactor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Establish any defaults the the user didn't pass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) tda10048_establish_defaults(&state->frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Set the xtal and freq defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (tda10048_set_if(&state->frontend, 8000000) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* Default bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Leave the gate closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tda10048_i2c_gate_ctrl(&state->frontend, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) EXPORT_SYMBOL(tda10048_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static const struct dvb_frontend_ops tda10048_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .name = "NXP TDA10048HN DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .frequency_min_hz = 177 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .frequency_max_hz = 858 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .frequency_stepsize_hz = 166666,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .release = tda10048_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .init = tda10048_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .set_frontend = tda10048_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .get_frontend = tda10048_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .get_tune_settings = tda10048_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .read_status = tda10048_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .read_ber = tda10048_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .read_signal_strength = tda10048_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .read_snr = tda10048_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .read_ucblocks = tda10048_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) MODULE_PARM_DESC(debug, "Enable verbose debug messages");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MODULE_AUTHOR("Steven Toth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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