^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) TDA10023 - DVB-C decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) (as used in Philips CU1216-3 NIM and the Reelbox DVB-C tuner card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2005 Georg Acher, BayCom GmbH (acher at baycom dot de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (c) 2006 Hartmut Birr (e9hack at gmail dot com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Remotely based on tda10021.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Copyright (C) 2004 Markus Schulz <msc@antzsystem.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Support for TDA10021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "tda1002x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG0_INIT_VAL 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct tda10023_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const struct tda10023_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* clock settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 pll_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 pll_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 pll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define dprintk(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static u8 tda10023_readreg (struct tda10023_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 b0 [] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 b1 [] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = i2c_transfer (state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) printk(KERN_ERR "DVB: TDA10023(%d): %s: readreg error (reg == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) num, __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = i2c_transfer (state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) printk(KERN_ERR "DVB: TDA10023(%d): %s, writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) num, __func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return (ret != 1) ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (mask==0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return tda10023_writereg(state, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val=tda10023_readreg(state,reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val&=~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val|=(data&mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return tda10023_writereg(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void tda10023_writetab(struct tda10023_state* state, u8* tab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 r,m,v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) r=*tab++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) m=*tab++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) v=*tab++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (r==0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (m==0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) msleep(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tda10023_writebit(state,r,m,v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) //get access to tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int lock_tuner(struct tda10023_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 buf[2] = { 0x0f, 0xc0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if(i2c_transfer(state->i2c, &msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) printk("tda10023: lock tuner fails\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) //release access from tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int unlock_tuner(struct tda10023_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 buf[2] = { 0x0f, 0x40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if(i2c_transfer(state->i2c, &msg_post, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) printk("tda10023: unlock tuner fails\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg0 |= state->reg0 & 0x63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tda10023_writereg (state, 0x00, reg0 & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tda10023_writereg (state, 0x00, reg0 | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) state->reg0 = reg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) s32 BDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) s32 BDRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) s16 SFIL=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 NDEC = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* avoid floating point operations multiplying syscloc and divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) by 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 sysclk_x_10 = state->sysclk * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (sr < (u32)(sysclk_x_10/984)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) NDEC=3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SFIL=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else if (sr < (u32)(sysclk_x_10/640)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) NDEC=3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SFIL=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else if (sr < (u32)(sysclk_x_10/492)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) NDEC=2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SFIL=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else if (sr < (u32)(sysclk_x_10/320)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) NDEC=2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SFIL=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else if (sr < (u32)(sysclk_x_10/246)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) NDEC=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SFIL=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } else if (sr < (u32)(sysclk_x_10/160)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) NDEC=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SFIL=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else if (sr < (u32)(sysclk_x_10/123)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) NDEC=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SFIL=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BDRI = (state->sysclk)*16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BDRI>>=NDEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BDRI +=sr/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) BDRI /=sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (BDRI>255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) BDRI=255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u64 BDRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BDRX=1<<(24+NDEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BDRX*=sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) BDR=(s32)BDRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dprintk("Symbolrate %i, BDR %i BDRI %i, NDEC %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sr, BDR, BDRI, NDEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tda10023_writebit (state, 0x03, 0xc0, NDEC<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tda10023_writereg (state, 0x0a, BDR&255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tda10023_writereg (state, 0x0b, (BDR>>8)&255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tda10023_writereg (state, 0x0c, (BDR>>16)&31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tda10023_writereg (state, 0x0d, BDRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tda10023_writereg (state, 0x3d, (SFIL<<7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int tda10023_init (struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 tda10023_inittab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* reg mask val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* 000 */ 0x2a, 0xff, 0x02, /* PLL3, Bypass, Power Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 003 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* 006 */ 0x2a, 0xff, 0x03, /* PLL3, Bypass, Power Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* 009 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 012 */ 0x28, 0xff, (state->pll_m-1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* 015 */ 0x29, 0xff, ((state->pll_p-1)<<6)|(state->pll_n-1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* GPR FSAMPLING=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 018 */ 0x00, 0xff, REG0_INIT_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* 021 */ 0x2a, 0xff, 0x08, /* PLL3 PSACLK=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* 024 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* 027 */ 0x1f, 0xff, 0x00, /* RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* 030 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* 033 */ 0xe6, 0x0c, 0x04, /* RSCFG_IND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* 036 */ 0x10, 0xc0, 0x80, /* DECDVBCFG1 PBER=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* 039 */ 0x0e, 0xff, 0x82, /* GAIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* 042 */ 0x03, 0x08, 0x08, /* CLKCONF DYN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* 045 */ 0x2e, 0xbf, 0x30, /* AGCCONF2 TRIAGC=0,POSAGC=ENAGCIF=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PPWMTUN=0 PPWMIF=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 048 */ 0x01, 0xff, 0x30, /* AGCREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* 051 */ 0x1e, 0x84, 0x84, /* CONTROL SACLK_ON=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* 054 */ 0x1b, 0xff, 0xc8, /* ADC TWOS=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* 057 */ 0x3b, 0xff, 0xff, /* IFMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* 060 */ 0x3c, 0xff, 0x00, /* IFMIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* 063 */ 0x34, 0xff, 0x00, /* PWMREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* 066 */ 0x35, 0xff, 0xff, /* TUNMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* 069 */ 0x36, 0xff, 0x00, /* TUNMIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* 072 */ 0x06, 0xff, 0x7f, /* EQCONF1 POSI=7 ENADAPT=ENEQUAL=DFE=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* 075 */ 0x1c, 0x30, 0x30, /* EQCONF2 STEPALGO=SGNALGO=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* 078 */ 0x37, 0xff, 0xf6, /* DELTAF_LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* 081 */ 0x38, 0xff, 0xff, /* DELTAF_MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* 084 */ 0x02, 0xff, 0x93, /* AGCCONF1 IFS=1 KAGCIF=2 KAGCTUN=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* 087 */ 0x2d, 0xff, 0xf6, /* SWEEP SWPOS=1 SWDYN=7 SWSTEP=1 SWLEN=2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* 090 */ 0x04, 0x10, 0x00, /* SWRAMP=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* 093 */ 0x12, 0xff, TDA10023_OUTPUT_MODE_PARALLEL_B, /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) INTP1 POCLKP=1 FEL=1 MFS=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* 096 */ 0x2b, 0x01, 0xa1, /* INTS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* 099 */ 0x20, 0xff, 0x04, /* INTP2 SWAPP=? MSBFIRSTP=? INTPSEL=? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 102 */ 0x2c, 0xff, 0x0d, /* INTP/S TRIP=0 TRIS=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* 105 */ 0xc4, 0xff, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* 108 */ 0xc3, 0x30, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* 111 */ 0xb5, 0xff, 0x19, /* ERAGC_THD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* 114 */ 0x00, 0x03, 0x01, /* GPR, CLBS soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* 117 */ 0x00, 0x03, 0x03, /* GPR, CLBS soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* 120 */ 0xff, 0x64, 0x00, /* Sleep 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* 123 */ 0xff, 0xff, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dprintk("DVB: TDA10023(%d): init chip\n", fe->dvb->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* override default values if set in config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (state->config->deltaf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) tda10023_inittab[80] = (state->config->deltaf & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tda10023_inittab[83] = (state->config->deltaf >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (state->config->output_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tda10023_inittab[95] = state->config->output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tda10023_writetab(state, tda10023_inittab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct qam_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 qam, lockthr, mseth, aref, agcrefnyq, eragnyq_thd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int tda10023_set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 delsys = c->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned qam = c->modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bool is_annex_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct qam_params qam_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Modulation QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [QPSK] = { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [QAM_16] = { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [QAM_32] = { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [QAM_64] = { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [QAM_128] = { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [QAM_256] = { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) is_annex_c = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) is_annex_c = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * gcc optimizes the code below the same way as it would code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * "if (qam > 5) return -EINVAL;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Yet, the code is clearer, as it shows what QAM standards are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * supported by the driver, and avoids the usage of magic numbers on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) switch (qam) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case QPSK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case QAM_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case QAM_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) tda10023_set_symbolrate(state, c->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tda10023_writereg(state, 0x05, qam_params[qam].lockthr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tda10023_writereg(state, 0x08, qam_params[qam].mseth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tda10023_writereg(state, 0x09, qam_params[qam].aref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tda10023_writereg(state, 0xb4, qam_params[qam].agcrefnyq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tda10023_writereg(state, 0xb6, qam_params[qam].eragnyq_thd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tda10023_writereg(state, 0x04, (c->inversion ? 0x12 : 0x32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tda10023_writebit(state, 0x04, 0x60, (c->inversion ? 0 : 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tda10023_writebit(state, 0x04, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (is_annex_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tda10023_writebit(state, 0x3d, 0xfc, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tda10023_writebit(state, 0x3d, 0xfc, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tda10023_setup_reg0(state, qam_params[qam].qam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int tda10023_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) //0x11[1] == CARLOCK -> Carrier locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) //0x11[2] == FSYNC -> Frame synchronisation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) //0x11[3] == FEL -> Front End locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) //0x11[6] == NODVB -> DVB Mode Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sync = tda10023_readreg (state, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (sync & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *status |= FE_HAS_SIGNAL|FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (sync & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *status |= FE_HAS_SYNC|FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (sync & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int tda10023_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 a,b,c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) a=tda10023_readreg(state, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) b=tda10023_readreg(state, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) c=tda10023_readreg(state, 0x16)&0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tda10023_writebit (state, 0x10, 0xc0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *ber = a | (b<<8)| (c<<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int tda10023_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 ifgain=tda10023_readreg(state, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) // Max raw value is about 0xb0 -> Normalize to >0xf0 after 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (gain>0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) gain=gain+2*(gain-0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (gain>255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gain=255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *strength = (gain<<8)|gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int tda10023_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 quality = ~tda10023_readreg(state, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *snr = (quality << 8) | quality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int tda10023_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 a,b,c,d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) a= tda10023_readreg (state, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) b= tda10023_readreg (state, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) c= tda10023_readreg (state, 0x76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) d= tda10023_readreg (state, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *ucblocks = a | (b<<8)|(c<<16)|(d<<24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tda10023_writebit (state, 0x10, 0x20,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tda10023_writebit (state, 0x10, 0x20,0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tda10023_writebit (state, 0x13, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int tda10023_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int sync,inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) s8 afc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sync = tda10023_readreg(state, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) afc = tda10023_readreg(state, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) inv = tda10023_readreg(state, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (verbose) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* AFC only valid when carrier has been recovered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) state->frontend.dvb->num, afc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) -((s32)p->symbol_rate * afc) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) p->inversion = (inv&0x20?0:1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) p->fec_inner = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) p->frequency = ((p->frequency + 31250) / 62500) * 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (sync & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) p->frequency -= ((s32)p->symbol_rate * afc) >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int tda10023_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) tda10023_writereg (state, 0x1b, 0x02); /* pdown ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tda10023_writereg (state, 0x00, 0x80); /* standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int tda10023_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) lock_tuner(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unlock_tuner(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void tda10023_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct tda10023_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct dvb_frontend_ops tda10023_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct dvb_frontend *tda10023_attach(const struct tda10023_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct tda10023_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) state = kzalloc(sizeof(struct tda10023_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* wakeup if in standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tda10023_writereg (state, 0x00, 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) state->pwm = pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) state->reg0 = REG0_INIT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (state->config->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) state->xtal = state->config->xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) state->pll_m = state->config->pll_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) state->pll_p = state->config->pll_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) state->pll_n = state->config->pll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* set default values if not defined in config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) state->xtal = 28920000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) state->pll_m = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) state->pll_p = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) state->pll_n = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* calc sysclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) state->sysclk = (state->xtal * state->pll_m / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) (state->pll_n * state->pll_p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) state->frontend.ops.info.symbol_rate_min = (state->sysclk/2)/64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) state->frontend.ops.info.symbol_rate_max = (state->sysclk/2)/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dprintk("DVB: TDA10023 %s: xtal:%d pll_m:%d pll_p:%d pll_n:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) __func__, state->xtal, state->pll_m, state->pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) state->pll_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct dvb_frontend_ops tda10023_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = "Philips TDA10023 DVB-C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .frequency_min_hz = 47 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .symbol_rate_min = 0, /* set in tda10023_attach */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .symbol_rate_max = 0, /* set in tda10023_attach */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .caps = 0x400 | //FE_CAN_QAM_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) FE_CAN_QAM_128 | FE_CAN_QAM_256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) FE_CAN_FEC_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .release = tda10023_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .init = tda10023_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .sleep = tda10023_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .i2c_gate_ctrl = tda10023_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .set_frontend = tda10023_set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .get_frontend = tda10023_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .read_status = tda10023_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .read_ber = tda10023_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .read_signal_strength = tda10023_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .read_snr = tda10023_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .read_ucblocks = tda10023_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MODULE_AUTHOR("Georg Acher, Hartmut Birr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) EXPORT_SYMBOL(tda10023_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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