Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Toshiba TC90522 Demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * NOTICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This driver is incomplete and lacks init/config of the chips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * as the necessary info is not disclosed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * It assumes that users of this driver (such as a PCI bridge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * DTV receiver cards) properly init and configure the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * via I2C *before* calling this driver's init() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Currently, PT3 driver is the only one that uses this driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * and contains init/config code in its firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Thus some part of the code might be dependent on PT3 specific config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "tc90522.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TC90522_I2C_THRU_REG 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct tc90522_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct tc90522_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct dvb_frontend fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct i2c_adapter tuner_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	bool lna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct reg_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	msg.addr = state->i2c_client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		msg.buf = (u8 *)&regs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		ret = i2c_transfer(state->i2c_client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			.addr = state->i2c_client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			.buf = &reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			.addr = state->i2c_client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			.buf = val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			.len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret == ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	else if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static struct tc90522_state *cfg_to_state(struct tc90522_config *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return container_of(c, struct tc90522_state, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int tc90522s_set_tsid(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct reg_val set_tsid[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		{ 0x8f, 00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		{ 0x90, 00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int tc90522t_set_layers(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct reg_val rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u8 laysel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	rv.reg = 0x71;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	rv.val = laysel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return reg_write(fe->demodulator_priv, &rv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* frontend ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int tc90522s_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret = reg_read(state, 0xc3, &reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (reg & 0x80) /* input level under min ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	*status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (reg & 0x60) /* carrier? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	*status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (reg & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (reg_read(state, 0xc5, &reg, 1) < 0 || !(reg & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	*status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int tc90522t_read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ret = reg_read(state, 0x96, &reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (reg & 0xe0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				| FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ret = reg_read(state, 0x80, &reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (reg & 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (reg & 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	*status |= FE_HAS_SYNC | FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (reg & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	*status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const enum fe_code_rate fec_conv_sat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	FEC_NONE, /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	FEC_1_2, /* for BPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	FEC_2_3, /* for 8PSK. (trellis code) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int tc90522s_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				 struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct dtv_fe_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u8 val[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u32 cndat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	c->delivery_system = SYS_ISDBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	c->symbol_rate = 28860000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	layers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ret = reg_read(state, 0xe6, val, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		c->stream_id = val[0] << 8 | val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		/* high/single layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		v = (val[2] & 0x70) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		c->modulation = (v == 7) ? PSK_8 : QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		c->fec_inner = fec_conv_sat[v];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		c->layer[0].fec = c->fec_inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		c->layer[0].modulation = c->modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		c->layer[0].segment_count = val[3] & 0x3f; /* slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		/* low layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		v = (val[2] & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		c->layer[1].fec = fec_conv_sat[v];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		if (v == 0)  /* no low layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			c->layer[1].segment_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			c->layer[1].segment_count = val[4] & 0x3f; /* slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		 * actually, BPSK if v==1, but not defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		 * enum fe_modulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		c->layer[1].modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		layers = (v > 0) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	stats = &c->strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	stats->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* let the connected tuner set RSSI property cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (fe->ops.tuner_ops.get_rf_strength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		u16 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	stats = &c->cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	stats->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	cndat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ret = reg_read(state, 0xbc, val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		cndat = val[0] << 8 | val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (cndat >= 3000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		u32 p, p4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		s64 cn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		cndat -= 3000;  /* cndat: 4.12 fixed point float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		 * cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		 *                 + 88977 * P^2 - 89565 * P + 58857
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		 *  (P = sqrt(cndat) / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		/* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed  point float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		/* cn = cnr << 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		p = int_sqrt(cndat << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		p4 = cndat * cndat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		cn = div64_s64(-16346LL * p4 * p, 10) >> 35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		cn += (14341LL * p4) >> 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		cn -= (50259LL * cndat * p) >> 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		cn += (88977LL * cndat) >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		cn -= (89565LL * p) >> 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		cn += 58857  << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		stats->stat[0].svalue = cn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		stats->stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* per-layer post viterbi BER (or PER? config dependent?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	stats = &c->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	memset(stats, 0, sizeof(*stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	stats->len = layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = reg_read(state, 0xeb, val, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		for (i = 0; i < layers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		for (i = 0; i < layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			stats->stat[i].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			stats->stat[i].uvalue = val[i * 5] << 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				| val[i * 5 + 1] << 8 | val[i * 5 + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	stats = &c->post_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	memset(stats, 0, sizeof(*stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	stats->len = layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		for (i = 0; i < layers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		for (i = 0; i < layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			stats->stat[i].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			stats->stat[i].uvalue =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				val[i * 5 + 3] << 8 | val[i * 5 + 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			stats->stat[i].uvalue *= 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const enum fe_transmit_mode tm_conv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	TRANSMISSION_MODE_2K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	TRANSMISSION_MODE_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	TRANSMISSION_MODE_8K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const enum fe_code_rate fec_conv_ter[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const enum fe_modulation mod_conv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int tc90522t_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				 struct dtv_frontend_properties *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct dtv_fe_stats *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	int layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	u8 val[15], mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	u32 cndat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	c->delivery_system = SYS_ISDBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	c->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = reg_read(state, 0xb0, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		mode = (val[0] & 0xc0) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		c->transmission_mode = tm_conv[mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		c->guard_interval = (val[0] & 0x30) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ret = reg_read(state, 0xb2, val, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	layers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		c->isdbt_partial_reception = val[0] & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		/* layer A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		v = (val[2] & 0x78) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		if (v == 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			c->layer[0].segment_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			c->layer[0].segment_count = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			c->layer[0].interleaving = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		/* layer B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		v = (val[3] & 0x03) << 2 | (val[4] & 0xc0) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		if (v == 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			c->layer[1].segment_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			c->layer[1].segment_count = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			c->layer[1].modulation = mod_conv[(val[2] & 0x07)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			c->layer[1].interleaving = (val[3] & 0x1c) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		/* layer C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		v = (val[5] & 0x1e) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		if (v == 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			c->layer[2].segment_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			layers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			c->layer[2].segment_count = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			c->layer[2].interleaving = (val[5] & 0xe0) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	/* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	stats = &c->strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	stats->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	/* let the connected tuner set RSSI property cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (fe->ops.tuner_ops.get_rf_strength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		u16 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	stats = &c->cnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	stats->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	cndat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	ret = reg_read(state, 0x8b, val, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		cndat = val[0] << 16 | val[1] << 8 | val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (cndat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		u32 p, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		s64 cn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		 * cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		 * (P = 10log10(5505024/cndat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		/* cn = cnr << 3 (61.3 fixed point float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		/* p = 10log10(5505024/cndat) << 24  (8.24 fixed point float)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		p = intlog10(5505024) - intlog10(cndat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		p *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		cn = 24772;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		cn += div64_s64(43827LL * p, 10) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		tmp = p >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		cn += div64_s64(3184LL * tmp * tmp, 10) >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		tmp = p >> 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		tmp = p >> 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		stats->stat[0].svalue = cn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		stats->stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	/* per-layer post viterbi BER (or PER? config dependent?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	stats = &c->post_bit_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	memset(stats, 0, sizeof(*stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	stats->len = layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	ret = reg_read(state, 0x9d, val, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		for (i = 0; i < layers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 			stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		for (i = 0; i < layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			stats->stat[i].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			stats->stat[i].uvalue = val[i * 3] << 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 				| val[i * 3 + 1] << 8 | val[i * 3 + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	stats = &c->post_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	memset(stats, 0, sizeof(*stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	stats->len = layers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		for (i = 0; i < layers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		for (i = 0; i < layers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 			stats->stat[i].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			stats->stat[i].uvalue =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 				val[9 + i * 2] << 8 | val[9 + i * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			stats->stat[i].uvalue *= 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct reg_val reset_sat = { 0x03, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct reg_val reset_ter = { 0x01, 0x40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int tc90522_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		ret = fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (fe->ops.delsys[0] == SYS_ISDBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		ret = tc90522s_set_tsid(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 			goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		ret = reg_write(state, &reset_sat, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		ret = tc90522t_set_layers(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 			goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		ret = reg_write(state, &reset_ter, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 			__func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int tc90522_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	struct dvb_frontend_tune_settings *settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (fe->ops.delsys[0] == SYS_ISDBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		settings->min_delay_ms = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		settings->step_size = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		settings->max_drift = settings->step_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		settings->min_delay_ms = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		settings->step_size = 142857;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		settings->max_drift = settings->step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	struct reg_val agc_sat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		{ 0x0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		{ 0x10, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		{ 0x11, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		{ 0x03, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	struct reg_val agc_ter[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		{ 0x25, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		{ 0x23, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		{ 0x01, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	struct reg_val *rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	if (fe->ops.delsys[0] == SYS_ISDBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		agc_sat[0].val = on ? 0xff : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		agc_sat[1].val |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		agc_sat[1].val |= on ? 0x01 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		agc_sat[2].val |= on ? 0x40 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		rv = agc_sat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		num = ARRAY_SIZE(agc_sat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		agc_ter[0].val = on ? 0x40 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		agc_ter[1].val |= on ? 0x00 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		rv = agc_ter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		num = ARRAY_SIZE(agc_ter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	return reg_write(state, rv, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct reg_val sleep_sat = { 0x17, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct reg_val sleep_ter = { 0x03, 0x90 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int tc90522_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	if (fe->ops.delsys[0] == SYS_ISDBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		ret = reg_write(state, &sleep_sat, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		ret = reg_write(state, &sleep_ter, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		if (ret == 0 && fe->ops.set_lna &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		    fe->dtv_property_cache.lna == LNA_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 			fe->dtv_property_cache.lna = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 			ret = fe->ops.set_lna(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 			fe->dtv_property_cache.lna = LNA_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		dev_warn(&state->tuner_i2c.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			"(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 			__func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct reg_val wakeup_sat = { 0x17, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct reg_val wakeup_ter = { 0x03, 0x80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int tc90522_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	 * Because the init sequence is not public,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	 * the parent device/driver should have init'ed the device before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	 * just wake up the device here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	if (fe->ops.delsys[0] == SYS_ISDBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 		ret = reg_write(state, &wakeup_sat, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 		ret = reg_write(state, &wakeup_ter, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		if (ret == 0 && fe->ops.set_lna &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 		    fe->dtv_property_cache.lna == LNA_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 			fe->dtv_property_cache.lna = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 			ret = fe->ops.set_lna(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 			fe->dtv_property_cache.lna = LNA_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 		dev_warn(&state->tuner_i2c.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 			"(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 			__func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	/* prefer 'all-layers' to 'none' as a default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	if (fe->dtv_property_cache.isdbt_layer_enabled == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		fe->dtv_property_cache.isdbt_layer_enabled = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	return tc90522_set_if_agc(fe, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)  * tuner I2C adapter functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	struct i2c_msg *new_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	int ret, rd_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	u8 wbuf[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	u8 *p, *bufend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	if (num <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	rd_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 		if (msgs[i].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 			rd_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	new_msgs = kmalloc_array(num + rd_num, sizeof(*new_msgs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	if (!new_msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	state = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	p = wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	bufend = wbuf + sizeof(wbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	for (i = 0, j = 0; i < num; i++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 		new_msgs[j].addr = state->i2c_client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		new_msgs[j].flags = msgs[i].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 		if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 			new_msgs[j].flags &= ~I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 			if (p + 2 > bufend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 			p[0] = TC90522_I2C_THRU_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 			p[1] = msgs[i].addr << 1 | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 			new_msgs[j].buf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 			new_msgs[j].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 			p += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 			j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 			new_msgs[j].addr = state->i2c_client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 			new_msgs[j].flags = msgs[i].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 			new_msgs[j].buf = msgs[i].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 			new_msgs[j].len = msgs[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 		if (p + msgs[i].len + 2 > bufend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 		p[0] = TC90522_I2C_THRU_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 		p[1] = msgs[i].addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 		memcpy(p + 2, msgs[i].buf, msgs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 		new_msgs[j].buf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 		new_msgs[j].len = msgs[i].len + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 		p += new_msgs[j].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 	if (i < num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	} else if (!state->cfg.split_tuner_read_i2c || rd_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 		ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 		 * Split transactions at each I2C_M_RD message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 		 * Some of the parent device require this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 		 * such as Friio (see. dvb-usb-gl861).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 		int from, to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 		from = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 			int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 			to = from + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 			while (to < j && !(new_msgs[to].flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 				to++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 			r = i2c_transfer(state->i2c_client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 					 &new_msgs[from], to - from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 			ret = (r <= 0) ? r : ret + r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 			from = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 		} while (from < j && ret > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	if (ret >= 0 && ret < j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	kfree(new_msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 	return (ret == j) ? num : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static u32 tc90522_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 	return I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const struct i2c_algorithm tc90522_tuner_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 	.master_xfer   = &tc90522_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	.functionality = &tc90522_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)  * I2C driver functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct dvb_frontend_ops tc90522_ops_sat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	.delsys = { SYS_ISDBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 		.name = "Toshiba TC90522 ISDB-S module",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 		.frequency_min_hz =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 		.frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 		.caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 			FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 			FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	.init = tc90522_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	.sleep = tc90522_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	.set_frontend = tc90522_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	.get_tune_settings = tc90522_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	.get_frontend = tc90522s_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	.read_status = tc90522s_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const struct dvb_frontend_ops tc90522_ops_ter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	.delsys = { SYS_ISDBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 		.name = "Toshiba TC90522 ISDB-T module",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 		.frequency_min_hz = 470 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 		.frequency_max_hz = 770 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 		.frequency_stepsize_hz = 142857,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 		.caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 			FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 			FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 			FE_CAN_QPSK     | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 			FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 			FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 			FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	.init = tc90522_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 	.sleep = tc90522_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	.set_frontend = tc90522_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 	.get_tune_settings = tc90522_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 	.get_frontend = tc90522t_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	.read_status = tc90522t_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int tc90522_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	struct tc90522_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	const struct dvb_frontend_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 	state->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 	cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	memcpy(&state->cfg, cfg, sizeof(state->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 	cfg->fe = state->cfg.fe = &state->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	ops =  id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 	memcpy(&state->fe.ops, ops, sizeof(*ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 	state->fe.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 	adap = &state->tuner_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 	adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 	adap->algo = &tc90522_tuner_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 	adap->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	strscpy(adap->name, "tc90522_sub", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	i2c_set_adapdata(adap, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 	ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 		goto free_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 	cfg->tuner_i2c = state->cfg.tuner_i2c = adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 	i2c_set_clientdata(client, &state->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 	dev_info(&client->dev, "Toshiba TC90522 attached.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) free_state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int tc90522_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 	struct tc90522_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 	state = cfg_to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 	i2c_del_adapter(&state->tuner_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const struct i2c_device_id tc90522_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 	{ TC90522_I2C_DEV_SAT, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 	{ TC90522_I2C_DEV_TER, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_DEVICE_TABLE(i2c, tc90522_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static struct i2c_driver tc90522_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 		.name	= "tc90522",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 	.probe		= tc90522_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 	.remove		= tc90522_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 	.id_table	= tc90522_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) module_i2c_driver(tc90522_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_DESCRIPTION("Toshiba TC90522 frontend");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MODULE_AUTHOR("Akihiro TSUKADA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_LICENSE("GPL");