Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	STV6110(A) Silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	Copyright (C) Manu Abraham <abraham.manu@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	Copyright (C) ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __STV6110x_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __STV6110x_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STV6110x_CTRL1				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STV6110x_OFFST_CTRL1_K			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STV6110x_WIDTH_CTRL1_K			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STV6110x_OFFST_CTRL1_LPT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STV6110x_WIDTH_CTRL1_LPT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STV6110x_OFFST_CTRL1_RX			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STV6110x_WIDTH_CTRL1_RX			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STV6110x_OFFST_CTRL1_SYN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STV6110x_WIDTH_CTRL1_SYN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STV6110x_CTRL2				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STV6110x_OFFST_CTRL2_CO_DIV		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STV6110x_WIDTH_CTRL2_CO_DIV		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STV6110x_OFFST_CTRL2_RSVD		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STV6110x_WIDTH_CTRL2_RSVD		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STV6110x_OFFST_CTRL2_REFOUT_SEL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STV6110x_WIDTH_CTRL2_REFOUT_SEL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STV6110x_OFFST_CTRL2_BBGAIN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STV6110x_WIDTH_CTRL2_BBGAIN		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STV6110x_TNG0				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STV6110x_OFFST_TNG0_N_DIV_7_0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STV6110x_WIDTH_TNG0_N_DIV_7_0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STV6110x_TNG1				0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STV6110x_OFFST_TNG1_R_DIV		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STV6110x_WIDTH_TNG1_R_DIV		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STV6110x_OFFST_TNG1_PRESC32_ON		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STV6110x_WIDTH_TNG1_PRESC32_ON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STV6110x_OFFST_TNG1_DIV4SEL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STV6110x_WIDTH_TNG1_DIV4SEL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STV6110x_OFFST_TNG1_N_DIV_11_8		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STV6110x_WIDTH_TNG1_N_DIV_11_8		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STV6110x_CTRL3				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STV6110x_OFFST_CTRL3_DCLOOP_OFF		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STV6110x_WIDTH_CTRL3_DCLOOP_OFF		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STV6110x_OFFST_CTRL3_RCCLK_OFF		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STV6110x_WIDTH_CTRL3_RCCLK_OFF		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STV6110x_OFFST_CTRL3_ICP		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STV6110x_WIDTH_CTRL3_ICP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STV6110x_OFFST_CTRL3_CF			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STV6110x_WIDTH_CTRL3_CF			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STV6110x_STAT1				0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STV6110x_OFFST_STAT1_CALVCO_STRT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STV6110x_WIDTH_STAT1_CALVCO_STRT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STV6110x_OFFST_STAT1_CALRC_STRT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STV6110x_WIDTH_STAT1_CALRC_STRT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STV6110x_OFFST_STAT1_LOCK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STV6110x_WIDTH_STAT1_LOCK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STV6110x_STAT2				0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STV6110x_STAT3				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* __STV6110x_REG_H */