Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * stv6110.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Driver for ST STV6110 satellite tuner IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2009 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "stv6110.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Max transfer size done by I2C transfer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX_XFER_SIZE  64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) struct stv6110_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	int i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8 clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u8 gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u8 regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			printk(KERN_DEBUG args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static s32 abssub(s32 a, s32 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (a > b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		return a - b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return b - a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void stv6110_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int stv6110_write_regs(struct dvb_frontend *fe, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 							int start, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u8 cmdbuf[MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.addr	= priv->i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.buf	= cmdbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.len	= len + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (1 + len > sizeof(cmdbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		       "%s: i2c wr: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		       KBUILD_MODNAME, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (start + len > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	memcpy(&cmdbuf[1], buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	cmdbuf[0] = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	rc = i2c_transfer(priv->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (rc != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		dprintk("%s: i2c error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int stv6110_read_regs(struct dvb_frontend *fe, u8 regs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 							int start, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u8 reg[] = { start };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			.addr	= priv->i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			.buf	= reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			.len	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			.addr	= priv->i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			.flags	= I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			.buf	= regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			.len	= len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	rc = i2c_transfer(priv->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (rc != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		dprintk("%s: i2c error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	memcpy(&priv->regs[start], regs, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int stv6110_read_reg(struct dvb_frontend *fe, int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 buf[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	stv6110_read_regs(fe, buf, start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int stv6110_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8 reg[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	stv6110_write_regs(fe, reg, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static u32 carrier_width(u32 symbol_rate, enum fe_rolloff rolloff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 rlf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	switch (rolloff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	case ROLLOFF_20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		rlf = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	case ROLLOFF_25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		rlf = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		rlf = 35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return symbol_rate  + ((symbol_rate * rlf) / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int stv6110_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 r8, ret = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if ((bandwidth / 2) > 36000000) /*BW/2 max=31+5=36 mhz for r8=31*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		r8 = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	else if ((bandwidth / 2) < 5000000) /* BW/2 min=5Mhz for F=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		r8 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	else /*if 5 < BW/2 < 36*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		r8 = (bandwidth / 2) / 1000000 - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* ctrl3, RCCLKOFF = 0 Activate the calibration Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* ctrl3, CF = r8 Set the LPF value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	priv->regs[RSTV6110_CTRL3] &= ~((1 << 6) | 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	priv->regs[RSTV6110_CTRL3] |= (r8 & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL3], RSTV6110_CTRL3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* stat1, CALRCSTRT = 1 Start LPF auto calibration*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	priv->regs[RSTV6110_STAT1] |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	stv6110_write_regs(fe, &priv->regs[RSTV6110_STAT1], RSTV6110_STAT1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* Wait for CALRCSTRT == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	while ((i < 10) && (ret != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		ret = ((stv6110_read_reg(fe, RSTV6110_STAT1)) & 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		mdelay(1);	/* wait for LPF auto calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* RCCLKOFF = 1 calibration done, deactivate the calibration Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	priv->regs[RSTV6110_CTRL3] |= (1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL3], RSTV6110_CTRL3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int stv6110_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8 buf0[] = { 0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	memcpy(priv->regs, buf0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* K = (Reference / 1000000) - 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	priv->regs[RSTV6110_CTRL1] &= ~(0x1f << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	priv->regs[RSTV6110_CTRL1] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* divisor value for the output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	priv->regs[RSTV6110_CTRL2] &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	priv->regs[RSTV6110_CTRL2] |= (priv->clk_div << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL1], RSTV6110_CTRL1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	stv6110_set_bandwidth(fe, 72000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int stv6110_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u32 nbsteps, divider, psd2, freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u8 regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	stv6110_read_regs(fe, regs, 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/*N*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	divider += priv->regs[RSTV6110_TUNING1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*R*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	nbsteps  = (priv->regs[RSTV6110_TUNING2] >> 6) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*p*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	psd2  = (priv->regs[RSTV6110_TUNING2] >> 4) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	freq = divider * (priv->mclk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	freq /= (1 << (nbsteps + psd2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	freq /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	*frequency = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u8 ret = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u32 divider, ref, p, presc, i, result_freq, vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	s32 p_calc, p_calc_opt = 1000, r_div, r_div_opt = 0, p_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 						frequency, priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* K = (Reference / 1000000) - 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	priv->regs[RSTV6110_CTRL1] &= ~(0x1f << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	priv->regs[RSTV6110_CTRL1] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* BB_GAIN = db/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	priv->regs[RSTV6110_CTRL2] &= ~0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	priv->regs[RSTV6110_CTRL2] |= (priv->gain & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (frequency <= 1023000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		presc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	} else if (frequency <= 1300000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		presc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	} else if (frequency <= 2046000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		presc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		presc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* DIV4SEL = p*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	priv->regs[RSTV6110_TUNING2] &= ~(1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	priv->regs[RSTV6110_TUNING2] |= (p << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* PRESC32ON = presc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	priv->regs[RSTV6110_TUNING2] &= ~(1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	priv->regs[RSTV6110_TUNING2] |= (presc << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	p_val = (int)(1 << (p + 1)) * 10;/* P = 2 or P = 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	for (r_div = 0; r_div <= 3; r_div++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		p_calc = (priv->mclk / 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		p_calc /= (1 << (r_div + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if ((abssub(p_calc, p_val)) < (abssub(p_calc_opt, p_val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			r_div_opt = r_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		p_calc_opt = (priv->mclk / 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		p_calc_opt /= (1 << (r_div_opt + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ref = priv->mclk / ((1 << (r_div_opt + 1))  * (1 << (p + 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	divider = (((frequency * 1000) + (ref >> 1)) / ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* RDIV = r_div_opt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	priv->regs[RSTV6110_TUNING2] &= ~(3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	priv->regs[RSTV6110_TUNING2] |= (((r_div_opt) & 3) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* NDIV_MSB = MSB(divider) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	priv->regs[RSTV6110_TUNING2] &= ~0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* NDIV_LSB, LSB(divider) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	priv->regs[RSTV6110_TUNING1] = (divider & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	/* CALVCOSTRT = 1 VCO Auto Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	priv->regs[RSTV6110_STAT1] |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 						RSTV6110_CTRL1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/* Wait for CALVCOSTRT == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	while ((i < 10) && (ret != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		ret = ((stv6110_read_reg(fe, RSTV6110_STAT1)) & 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		msleep(1); /* wait for VCO auto calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ret = stv6110_read_reg(fe, RSTV6110_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	stv6110_get_frequency(fe, &result_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	dprintk("%s, stat1=%x, lo_freq=%d kHz, vco_frec=%d kHz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 						ret, result_freq, vco_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int stv6110_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	u32 bandwidth = carrier_width(c->symbol_rate, c->rolloff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	stv6110_set_frequency(fe, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	stv6110_set_bandwidth(fe, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int stv6110_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct stv6110_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	u8 r8 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u8 regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	stv6110_read_regs(fe, regs, 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	/* CF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	r8 = priv->regs[RSTV6110_CTRL3] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	*bandwidth = (r8 + 5) * 2000000;/* x2 for ZIF tuner BW/2 = F+5 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct dvb_tuner_ops stv6110_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.name = "ST STV6110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.frequency_min_hz  =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.frequency_max_hz  = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.frequency_step_hz =    1 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.init = stv6110_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.release = stv6110_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.sleep = stv6110_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.set_params = stv6110_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.get_frequency = stv6110_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.set_frequency = stv6110_set_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.get_bandwidth = stv6110_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.set_bandwidth = stv6110_set_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 					const struct stv6110_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 					struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	struct stv6110_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	u8 reg0[] = { 0x00, 0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			.addr = config->i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			.buf = reg0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			.len = 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* divisor value for the output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	reg0[2] &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	reg0[2] |= (config->clk_div << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ret = i2c_transfer(i2c, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	priv = kzalloc(sizeof(struct stv6110_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	priv->i2c_address = config->i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	priv->mclk = config->mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	priv->clk_div = config->clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	priv->gain = config->gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	memcpy(&priv->regs, &reg0[1], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	memcpy(&fe->ops.tuner_ops, &stv6110_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	printk(KERN_INFO "STV6110 attached on addr=%x!\n", priv->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) EXPORT_SYMBOL(stv6110_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_DESCRIPTION("ST STV6110 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_AUTHOR("Igor M. Liplianin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MODULE_LICENSE("GPL");