^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the ST STV0910 DVB-S/S2 demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Marcus Metzler <mocm@metzlerbros.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * developed for Digital Devices GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * version 2 only, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "stv0910.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "stv0910_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EXT_CLOCK 30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TUNING_DELAY 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BER_SRC_S 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BER_SRC_S2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static LIST_HEAD(stvlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum dvbs2_mod_cod {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DVBS2_32APSK_9_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum fe_stv0910_mod_cod {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FE_32APSK_910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline u32 muldiv32(u32 a, u32 b, u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u64 tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tmp64 = (u64)a * (u64)b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) do_div(tmp64, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return (u32)tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct stv_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct list_head stvlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mutex i2c_lock; /* shared I2C access protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct mutex reg_lock; /* shared register write protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 extclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct stv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct stv_base *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct dvb_frontend fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 regoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 i2crpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 tscfgh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 tsgeneral;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 tsspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 single;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long tune_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) s32 search_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 demod_lock_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum receive_mode receive_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 demod_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 fec_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 first_time_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 demod_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 last_viterbi_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum fe_code_rate puncture_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum fe_stv0910_mod_cod mod_cod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum dvbs2_fectype fectype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 pilots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum fe_stv0910_roll_off feroll_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int is_standard_broadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int is_vcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 cur_scrambling_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 last_bernumerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 last_berdenominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 berscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 vth[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct sinit_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct slookup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) s16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int write_reg(struct stv *state, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct i2c_adapter *adap = state->base->i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 data[3] = {reg >> 8, reg & 0xff, val};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .buf = data, .len = 3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (i2c_transfer(adap, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) state->base->adr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 reg, u8 *val, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 msg[2] = {reg >> 8, reg & 0xff};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .buf = msg, .len = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {.addr = adr, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .buf = val, .len = count } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (i2c_transfer(adapter, msgs, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) adr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int read_reg(struct stv *state, u16 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return i2c_read_regs16(state->base->i2c, state->base->adr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return i2c_read_regs16(state->base->i2c, state->base->adr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg, val, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mutex_lock(&state->base->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) status = read_reg(state, reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mutex_unlock(&state->base->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int write_field(struct stv *state, u32 field, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 shift, mask, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) status = read_reg(state, field >> 16, &old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mask = field & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) shift = (field >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) new = ((val << shift) & mask) | (old & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (new == old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return write_reg(state, field >> 16, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SET_FIELD(_reg, _val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) write_field(state, state->nr ? FSTV0910_P2_##_reg : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FSTV0910_P1_##_reg, _val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SET_REG(_reg, _val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) RSTV0910_P1_##_reg, _val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GET_REG(_reg, _val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RSTV0910_P1_##_reg, _val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct slookup s1_sn_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0, 9242 }, /* C/N= 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 5, 9105 }, /* C/N= 0.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 10, 8950 }, /* C/N= 1.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 15, 8780 }, /* C/N= 1.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 20, 8566 }, /* C/N= 2.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 25, 8366 }, /* C/N= 2.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 30, 8146 }, /* C/N= 3.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 35, 7908 }, /* C/N= 3.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 40, 7666 }, /* C/N= 4.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 45, 7405 }, /* C/N= 4.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 50, 7136 }, /* C/N= 5.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 55, 6861 }, /* C/N= 5.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 60, 6576 }, /* C/N= 6.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 65, 6330 }, /* C/N= 6.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 70, 6048 }, /* C/N= 7.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 75, 5768 }, /* C/N= 7.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 80, 5492 }, /* C/N= 8.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 85, 5224 }, /* C/N= 8.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 90, 4959 }, /* C/N= 9.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 95, 4709 }, /* C/N= 9.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 100, 4467 }, /* C/N=10.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 105, 4236 }, /* C/N=10.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 110, 4013 }, /* C/N=11.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 115, 3800 }, /* C/N=11.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 120, 3598 }, /* C/N=12.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 125, 3406 }, /* C/N=12.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 130, 3225 }, /* C/N=13.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 135, 3052 }, /* C/N=13.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 140, 2889 }, /* C/N=14.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 145, 2733 }, /* C/N=14.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 150, 2587 }, /* C/N=15.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 160, 2318 }, /* C/N=16.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 170, 2077 }, /* C/N=17.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 180, 1862 }, /* C/N=18.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 190, 1670 }, /* C/N=19.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 200, 1499 }, /* C/N=20.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 210, 1347 }, /* C/N=21.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 220, 1213 }, /* C/N=22.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 230, 1095 }, /* C/N=23.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 240, 992 }, /* C/N=24.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 250, 900 }, /* C/N=25.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 260, 826 }, /* C/N=26.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 270, 758 }, /* C/N=27.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 280, 702 }, /* C/N=28.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 290, 653 }, /* C/N=29.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 300, 613 }, /* C/N=30.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 310, 579 }, /* C/N=31.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 320, 550 }, /* C/N=32.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 330, 526 }, /* C/N=33.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 350, 490 }, /* C/N=33.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 400, 445 }, /* C/N=40.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 450, 430 }, /* C/N=45.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 500, 426 }, /* C/N=50.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 510, 425 } /* C/N=51.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct slookup s2_sn_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { -30, 13950 }, /* C/N=-2.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { -25, 13580 }, /* C/N=-2.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { -20, 13150 }, /* C/N=-2.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { -15, 12760 }, /* C/N=-1.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { -10, 12345 }, /* C/N=-1.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { -5, 11900 }, /* C/N=-0.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 0, 11520 }, /* C/N= 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 5, 11080 }, /* C/N= 0.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 10, 10630 }, /* C/N= 1.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 15, 10210 }, /* C/N= 1.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 20, 9790 }, /* C/N= 2.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { 25, 9390 }, /* C/N= 2.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 30, 8970 }, /* C/N= 3.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { 35, 8575 }, /* C/N= 3.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 40, 8180 }, /* C/N= 4.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 45, 7800 }, /* C/N= 4.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 50, 7430 }, /* C/N= 5.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 55, 7080 }, /* C/N= 5.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 60, 6720 }, /* C/N= 6.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { 65, 6320 }, /* C/N= 6.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 70, 6060 }, /* C/N= 7.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 75, 5760 }, /* C/N= 7.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 80, 5480 }, /* C/N= 8.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 85, 5200 }, /* C/N= 8.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 90, 4930 }, /* C/N= 9.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 95, 4680 }, /* C/N= 9.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 100, 4425 }, /* C/N=10.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 105, 4210 }, /* C/N=10.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 110, 3980 }, /* C/N=11.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 115, 3765 }, /* C/N=11.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 120, 3570 }, /* C/N=12.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 125, 3315 }, /* C/N=12.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 130, 3140 }, /* C/N=13.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 135, 2980 }, /* C/N=13.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 140, 2820 }, /* C/N=14.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 145, 2670 }, /* C/N=14.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 150, 2535 }, /* C/N=15.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 160, 2270 }, /* C/N=16.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 170, 2035 }, /* C/N=17.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 180, 1825 }, /* C/N=18.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 190, 1650 }, /* C/N=19.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 200, 1485 }, /* C/N=20.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 210, 1340 }, /* C/N=21.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 220, 1212 }, /* C/N=22.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 230, 1100 }, /* C/N=23.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 240, 1000 }, /* C/N=24.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 250, 910 }, /* C/N=25.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 260, 836 }, /* C/N=26.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 270, 772 }, /* C/N=27.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 280, 718 }, /* C/N=28.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 290, 671 }, /* C/N=29.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 300, 635 }, /* C/N=30.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 310, 602 }, /* C/N=31.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 320, 575 }, /* C/N=32.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 330, 550 }, /* C/N=33.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 350, 517 }, /* C/N=35.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 400, 480 }, /* C/N=40.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 450, 466 }, /* C/N=45.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 500, 464 }, /* C/N=50.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 510, 463 }, /* C/N=51.0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct slookup padc_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0, 118000 }, /* PADC= +0dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { -100, 93600 }, /* PADC= -1dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { -200, 74500 }, /* PADC= -2dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { -300, 59100 }, /* PADC= -3dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { -400, 47000 }, /* PADC= -4dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { -500, 37300 }, /* PADC= -5dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { -600, 29650 }, /* PADC= -6dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { -700, 23520 }, /* PADC= -7dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { -900, 14850 }, /* PADC= -9dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { -1100, 9380 }, /* PADC=-11dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { -1300, 5910 }, /* PADC=-13dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { -1500, 3730 }, /* PADC=-15dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { -1700, 2354 }, /* PADC=-17dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { -1900, 1485 }, /* PADC=-19dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { -2000, 1179 }, /* PADC=-20dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { -2100, 1000 }, /* PADC=-21dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const u8 s2car_loop[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * 20MPon 20MPoff 30MPon 30MPoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* FE_QPSK_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* FE_QPSK_13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* FE_QPSK_25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* FE_QPSK_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* FE_QPSK_35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* FE_QPSK_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* FE_QPSK_34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* FE_QPSK_45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* FE_QPSK_56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* FE_QPSK_89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* FE_QPSK_910 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* FE_8PSK_35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* FE_8PSK_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* FE_8PSK_34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* FE_8PSK_56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* FE_8PSK_89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* FE_8PSK_910 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /**********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) **********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * 20MPoff 30MPon 30MPoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* FE_16APSK_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* FE_16APSK_34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* FE_16APSK_45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* FE_16APSK_56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* FE_16APSK_89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* FE_16APSK_910 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* FE_32APSK_34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* FE_32APSK_45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* FE_32APSK_56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* FE_32APSK_89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* FE_32APSK_910 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static u8 get_optim_cloop(struct stv *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) enum fe_stv0910_mod_cod mod_cod, u32 pilots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (mod_cod >= FE_32APSK_910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) else if (mod_cod >= FE_QPSK_14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (state->symbol_rate <= 3000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) i += 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) else if (state->symbol_rate <= 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) i += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) else if (state->symbol_rate <= 15000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else if (state->symbol_rate <= 25000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) i += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!pilots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) i += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return s2car_loop[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u8 symb_freq0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 symb_freq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 symb_freq2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 symb_freq3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 tim_offs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 tim_offs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 tim_offs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) s32 timing_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *p_symbol_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!state->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ((u32)symb_freq1 << 8) | (u32)symb_freq0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (u32)tim_offs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if ((timing_offset & (1 << 23)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) timing_offset |= 0xFF000000; /* Sign extent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *p_symbol_rate = symbol_rate + timing_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int get_signal_parameters(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!state->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) state->pilots = (tmp & 0x01) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } else if (state->receive_mode == RCVMODE_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) state->puncture_rate = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (tmp & 0x1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case 0x0d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) state->puncture_rate = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) state->puncture_rate = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case 0x15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) state->puncture_rate = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case 0x18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) state->puncture_rate = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case 0x1a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) state->puncture_rate = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) state->is_vcm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) state->is_standard_broadcast = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) state->feroll_off = FE_SAT_35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int tracking_optimization(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) tmp &= ~0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) switch (state->receive_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case RCVMODE_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) tmp |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case RCVMODE_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) tmp |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tmp |= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Disable Reed-Solomon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) write_shared_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (state->fectype == DVBS2_64K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 aclc = get_optim_cloop(state, state->mod_cod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) state->pilots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (state->mod_cod <= FE_QPSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) write_reg(state, RSTV0910_P2_ACLC2S2Q +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) state->regoff, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } else if (state->mod_cod <= FE_8PSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) write_reg(state, RSTV0910_P2_ACLC2S2Q +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) state->regoff, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) write_reg(state, RSTV0910_P2_ACLC2S28 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) state->regoff, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else if (state->mod_cod <= FE_16APSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) write_reg(state, RSTV0910_P2_ACLC2S2Q +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) state->regoff, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) write_reg(state, RSTV0910_P2_ACLC2S216A +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) state->regoff, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else if (state->mod_cod <= FE_32APSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) write_reg(state, RSTV0910_P2_ACLC2S2Q +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) state->regoff, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) write_reg(state, RSTV0910_P2_ACLC2S232A +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) state->regoff, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static s32 table_lookup(const struct slookup *table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int table_size, u32 reg_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) s32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int imin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int imax = table_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) s32 reg_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Assumes Table[0].RegValue > Table[imax].RegValue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (reg_value >= table[0].reg_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) value = table[0].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) } else if (reg_value <= table[imax].reg_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) value = table[imax].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) while ((imax - imin) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) i = (imax + imin) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if ((table[imin].reg_value >= reg_value) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (reg_value >= table[i].reg_value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) imax = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) imin = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) reg_diff = table[imax].reg_value - table[imin].reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) value = table[imin].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (reg_diff != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) value += ((s32)(reg_value - table[imin].reg_value) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (s32)(table[imax].value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) - table[imin].value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) / (reg_diff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 data0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int n_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const struct slookup *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *signal_to_noise = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!state->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) &data1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &data0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) n_lookup = ARRAY_SIZE(s2_sn_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) lookup = s2_sn_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &data1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &data0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) n_lookup = ARRAY_SIZE(s1_sn_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) lookup = s1_sn_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) data = (((u16)data1) << 8) | (u16)data0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *signal_to_noise = table_lookup(lookup, n_lookup, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 *berdenominator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 regs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int status = read_regs(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) RSTV0910_P2_ERRCNT12 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) regs, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if ((regs[0] & 0x80) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) state->last_berdenominator = 1ULL << ((state->berscale * 2) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 10 + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ((u32)regs[1] << 8) | regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (state->last_bernumerator < 256 && state->berscale < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) state->berscale += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 0x20 | state->berscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) } else if (state->last_bernumerator > 1024 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) state->berscale > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) state->berscale -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) state->regoff, 0x20 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) state->berscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *bernumerator = state->last_bernumerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *berdenominator = state->last_berdenominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const u32 nbch[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { 0, 0}, /* DUMMY_PLF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {16200, 3240}, /* QPSK_1_4, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {21600, 5400}, /* QPSK_1_3, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {25920, 6480}, /* QPSK_2_5, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {32400, 7200}, /* QPSK_1_2, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {38880, 9720}, /* QPSK_3_5, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {43200, 10800}, /* QPSK_2_3, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {48600, 11880}, /* QPSK_3_4, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {51840, 12600}, /* QPSK_4_5, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {54000, 13320}, /* QPSK_5_6, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {57600, 14400}, /* QPSK_8_9, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {58320, 16000}, /* QPSK_9_10, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {43200, 9720}, /* 8PSK_3_5, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {48600, 10800}, /* 8PSK_2_3, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {51840, 11880}, /* 8PSK_3_4, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {54000, 13320}, /* 8PSK_5_6, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {57600, 14400}, /* 8PSK_8_9, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {58320, 16000}, /* 8PSK_9_10, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {43200, 10800}, /* 16APSK_2_3, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {48600, 11880}, /* 16APSK_3_4, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {51840, 12600}, /* 16APSK_4_5, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {54000, 13320}, /* 16APSK_5_6, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {57600, 14400}, /* 16APSK_8_9, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {58320, 16000}, /* 16APSK_9_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {48600, 11880}, /* 32APSK_3_4, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {51840, 12600}, /* 32APSK_4_5, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {54000, 13320}, /* 32APSK_5_6, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {57600, 14400}, /* 32APSK_8_9, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {58320, 16000}, /* 32APSK_9_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (mod_cod >= DVBS2_QPSK_1_4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return nbch[mod_cod][fectype];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 64800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u32 *berdenominator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 regs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regs, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if ((regs[0] & 0x80) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) state->last_berdenominator =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) state->fectype) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) (state->berscale * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ((u32)regs[1] << 8) | regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (state->last_bernumerator < 256 && state->berscale < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) state->berscale += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 0x20 | state->berscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else if (state->last_bernumerator > 1024 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) state->berscale > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) state->berscale -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 0x20 | state->berscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *bernumerator = state->last_bernumerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *berdenominator = state->last_berdenominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 *berdenominator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *bernumerator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *berdenominator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) switch (state->receive_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case RCVMODE_DVBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return get_bit_error_rate_s(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) bernumerator, berdenominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case RCVMODE_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return get_bit_error_rate_s2(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) bernumerator, berdenominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int set_mclock(struct stv *state, u32 master_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 idf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 odf = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 quartz = state->base->extclk / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 fphi = master_clock / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 ndiv = (fphi * odf * idf) / quartz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 cp = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (ndiv >= 7 && ndiv <= 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) cp = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) else if (ndiv >= 72 && ndiv <= 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) cp = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) else if (ndiv >= 80 && ndiv <= 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) cp = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) else if (ndiv >= 88 && ndiv <= 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) cp = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) else if (ndiv >= 96 && ndiv <= 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) cp = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) else if (ndiv >= 104 && ndiv <= 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) cp = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else if (ndiv >= 112 && ndiv <= 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) cp = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) else if (ndiv >= 120 && ndiv <= 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) cp = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else if (ndiv >= 128 && ndiv <= 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) cp = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else if (ndiv >= 136 && ndiv <= 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) cp = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) else if (ndiv >= 144 && ndiv <= 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cp = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else if (ndiv >= 152 && ndiv <= 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) cp = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) else if (ndiv >= 160 && ndiv <= 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) cp = 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) else if (ndiv >= 168 && ndiv <= 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) cp = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else if (ndiv >= 176 && ndiv <= 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cp = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else if (ndiv >= 184 && ndiv <= 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) cp = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) else if (ndiv >= 192 && ndiv <= 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) cp = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else if (ndiv >= 200 && ndiv <= 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) cp = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) else if (ndiv >= 208 && ndiv <= 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) cp = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) else if (ndiv >= 216 && ndiv <= 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) cp = 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else if (ndiv >= 224 && ndiv <= 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) cp = 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) write_reg(state, RSTV0910_NCOARSE2, odf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) write_reg(state, RSTV0910_NCOARSE1, ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) fvco = (quartz * 2 * ndiv) / idf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) state->base->mclk = fvco / (2 * odf) * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int stop(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (state->started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) state->tscfgh | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tmp &= ~0x01; /* release reset DVBS2 packet delin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Blind optim*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Stop the demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) state->started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) state->receive_mode = RCVMODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static void set_pls(struct stv *state, u32 pls_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (pls_code == state->cur_scrambling_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* PLROOT2 bit 2 = gold code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) pls_code & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) (pls_code >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) 0x04 | ((pls_code >> 16) & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) state->cur_scrambling_code = pls_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static void set_isi(struct stv *state, u32 isi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (isi == NO_STREAM_ID_FILTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (isi == 0x80000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) SET_FIELD(FORCE_CONTINUOUS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SET_FIELD(TSOUT_NOSYNC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SET_FIELD(FILTER_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) isi & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SET_FIELD(ALGOSWRST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SET_FIELD(ALGOSWRST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static void set_stream_modes(struct stv *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) set_isi(state, p->stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) set_pls(state, p->scrambling_sequence_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int init_search_param(struct stv *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) SET_FIELD(FORCE_CONTINUOUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) SET_FIELD(FRAME_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SET_FIELD(FILTER_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SET_FIELD(TSOUT_NOSYNC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) SET_FIELD(TSFIFO_EMBINDVB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SET_FIELD(TSDEL_SYNCBYTE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SET_REG(UPLCCST0, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SET_FIELD(TSINS_TOKEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SET_FIELD(HYSTERESIS_THRESHOLD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SET_FIELD(ISIOBS_MODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) set_stream_modes(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) val = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) val = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) val = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) val = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) val = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case FEC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int set_vth_default(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) state->vth[0] = 0xd7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) state->vth[1] = 0x85;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) state->vth[2] = 0x58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) state->vth[3] = 0x3a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) state->vth[4] = 0x34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) state->vth[5] = 0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int set_vth(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const struct slookup vthlookup_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {250, 8780}, /* C/N= 1.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {100, 7405}, /* C/N= 4.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {40, 6330}, /* C/N= 6.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {12, 5224}, /* C/N= 8.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {5, 4236} /* C/N=10.5dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u8 tmp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int status = read_regs(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) RSTV0910_P2_NNOSDATAT1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) tmp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u16 reg_value = (tmp[0] << 8) | tmp[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) for (i = 0; i < 6; i += 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (state->vth[i] > vth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) state->vth[i] = vth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static int start(struct stv *state, struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) s32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) u8 reg_dmdcfgmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u16 symb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) state->receive_mode = RCVMODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) state->demod_lock_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Demod Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (state->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) init_search_param(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) state->demod_timeout = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) state->fec_timeout = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) state->demod_timeout = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) state->fec_timeout = 1300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) state->demod_timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) state->fec_timeout = 650;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) state->demod_timeout = 700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) state->fec_timeout = 350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) state->demod_timeout = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) state->fec_timeout = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) } else { /* SR >=20Msps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) state->demod_timeout = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) state->fec_timeout = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* Set the Init Symbol rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ((symb >> 8) & 0x7F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) state->demod_bits |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* FE_STV0910_SetSearchStandard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) reg_dmdcfgmd |= 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) write_shared_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Disable DSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) enable_puncture_rate(state, FEC_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * Reset CAR3, bug DVBS2->DVBS1 lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * Note: The bit is only pulsed -> no lock on shared register needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) write_reg(state, RSTV0910_TSTRES0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) set_vth_default(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Reset demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (p->symbol_rate <= 5000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) freq = (state->search_range / 2000) + 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) freq = (state->search_range / 2000) + 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) freq = (freq << 16) / (state->base->mclk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) (freq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* CFR Low Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) freq = -freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) (freq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* init the demod frequency offset to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Trigger acq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) state->demod_lock_time += TUNING_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) state->started = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static int init_diseqc(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u16 offs = state->nr ? 0x40 : 0; /* Address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Disable receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int probe(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) state->receive_mode = RCVMODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) state->started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (read_reg(state, RSTV0910_MID, &id) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (id != 0x51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* Configure the I2C repeater to off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* Configure the I2C repeater to off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Set the I2C to oversampling ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (state->single)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) write_reg(state, RSTV0910_TSTRES0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) set_mclock(state, 135000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* TS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Reset stream merger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) init_diseqc(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static int gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u8 i2crpt = state->i2crpt & ~0x86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * mutex_lock note: Concurrent I2C gate bus accesses must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * prevented (STV0910 = dual demod on a single IC with a single I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * gate/bus, and two tuners attached), similar to most (if not all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * other I2C host interfaces/buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * enable=1 (open I2C gate) will grab the lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * enable=0 (close I2C gate) releases the lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mutex_lock(&state->base->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) i2crpt |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) i2crpt |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) RSTV0910_P1_I2CRPT, i2crpt) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* don't hold the I2C bus lock on failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) mutex_unlock(&state->base->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_err(&state->base->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) "%s() write_reg failure (enable=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) __func__, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) state->i2crpt = i2crpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) mutex_unlock(&state->base->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static void release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) state->base->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (state->base->count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) list_del(&state->base->stvlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) kfree(state->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int set_parameters(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (fe->ops.tuner_ops.set_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) state->symbol_rate = p->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) stat = start(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static int manage_matype_info(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (!state->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u8 bbheader[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) bbheader, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) state->feroll_off =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) state->is_vcm = (bbheader[0] & 0x10) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) } else if (state->receive_mode == RCVMODE_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) state->is_vcm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) state->is_standard_broadcast = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) state->feroll_off = FE_SAT_35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int read_snr(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) s32 snrval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (!get_signal_to_noise(state, &snrval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static int read_ber(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 n, d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) get_bit_error_rate(state, &n, &d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) p->pre_bit_error.stat[0].uvalue = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) p->pre_bit_count.stat[0].uvalue = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static void read_signal_strength(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) u8 reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) u16 agc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) s32 padc, power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) agc = (((u32)reg[0]) << 8) | reg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) for (i = 0; i < 5; i += 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) power += (u32)reg[0] * (u32)reg[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) + (u32)reg[1] * (u32)reg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) power /= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) p->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) p->strength.stat[0].svalue = (padc - agc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static int read_status(struct dvb_frontend *fe, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) u8 dmd_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) u8 dstatus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) enum receive_mode cur_receive_mode = RCVMODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u32 feclock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (dmd_state & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (dstatus & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) cur_receive_mode = (dmd_state & 0x20) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) RCVMODE_DVBS : RCVMODE_DVBS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (cur_receive_mode == RCVMODE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) set_vth(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* reset signal statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) *status |= (FE_HAS_SIGNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) | FE_HAS_CARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) | FE_HAS_VITERBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) | FE_HAS_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (state->receive_mode == RCVMODE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) state->receive_mode = cur_receive_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) state->demod_lock_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) state->first_time_lock = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) get_signal_parameters(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) tracking_optimization(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) state->tscfgh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) state->tscfgh | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) state->tscfgh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (dmd_state & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u8 pdelstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) read_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) RSTV0910_P2_PDELSTATUS1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) &pdelstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) feclock = (pdelstatus & 0x02) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u8 vstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) read_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) RSTV0910_P2_VSTATUSVIT + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) &vstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) feclock = (vstatus & 0x08) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (feclock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (state->first_time_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) state->first_time_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) manage_matype_info(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * FSTV0910_P2_MANUALSX_ROLLOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * FSTV0910_P2_MANUALS2_ROLLOFF = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) state->demod_bits &= ~0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) RSTV0910_P2_DEMOD + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) state->demod_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) read_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) RSTV0910_P2_PDELCTRL2 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* reset DVBS2 packet delinator error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) tmp |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) RSTV0910_P2_PDELCTRL2 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* reset DVBS2 packet delinator error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) tmp &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) RSTV0910_P2_PDELCTRL2 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) state->berscale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) state->last_bernumerator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) state->last_berdenominator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* force to PRE BCH Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) RSTV0910_P2_ERRCTRL1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) BER_SRC_S2 | state->berscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) state->berscale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) state->last_bernumerator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) state->last_berdenominator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* force to PRE RS Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) RSTV0910_P2_ERRCTRL1 + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) BER_SRC_S | state->berscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Reset the Total packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * Reset the packet Error counter2 (and Set it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * infinite error count mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) set_vth_default(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (state->receive_mode == RCVMODE_DVBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) enable_puncture_rate(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) state->puncture_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* Use highest signaled ModCod for quality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (state->is_vcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) enum fe_stv0910_mod_cod mod_cod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (mod_cod > state->mod_cod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) state->mod_cod = mod_cod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* read signal statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* read signal strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) read_signal_strength(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* read carrier/noise on FE_HAS_CARRIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (*status & FE_HAS_CARRIER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) read_snr(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* read ber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (*status & FE_HAS_VITERBI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) read_ber(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) u32 symbolrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (state->receive_mode == RCVMODE_DVBS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) u32 mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) const enum fe_modulation modcod2mod[0x20] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) QPSK, QPSK, QPSK, QPSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) QPSK, QPSK, QPSK, QPSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) QPSK, QPSK, QPSK, QPSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) PSK_8, PSK_8, PSK_8, PSK_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) PSK_8, PSK_8, APSK_16, APSK_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) APSK_16, APSK_16, APSK_16, APSK_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) APSK_32, APSK_32, APSK_32, APSK_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) APSK_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) const enum fe_code_rate modcod2fec[0x20] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) FEC_9_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) mc = ((tmp & 0x7c) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) p->modulation = modcod2mod[mc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) p->fec_inner = modcod2fec[mc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) } else if (state->receive_mode == RCVMODE_DVBS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) switch (tmp & 0x1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case 0x0d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) p->fec_inner = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) case 0x12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) p->fec_inner = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) case 0x15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) p->fec_inner = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case 0x18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) p->fec_inner = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case 0x1a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) p->fec_inner = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) p->fec_inner = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) p->rolloff = ROLLOFF_35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (state->receive_mode != RCVMODE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) get_cur_symbol_rate(state, &symbolrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) p->symbol_rate = symbolrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int tune(struct dvb_frontend *fe, bool re_tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) unsigned int mode_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) unsigned int *delay, enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (re_tune) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) r = set_parameters(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) state->tune_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) r = read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (*status & FE_HAS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) *delay = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return DVBFE_ALGO_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) u16 offs = state->nr ? 0x40 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static int wait_dis(struct stv *state, u8 flag, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) u16 offs = state->nr ? 0x40 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if ((stat & flag) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static int send_master_cmd(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct dvb_diseqc_master_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) SET_FIELD(DISEQC_MODE, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) SET_FIELD(DIS_PRECHARGE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) for (i = 0; i < cmd->msg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) wait_dis(state, 0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) SET_REG(DISTXFIFO, cmd->msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) SET_FIELD(DIS_PRECHARGE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) wait_dis(state, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (burst == SEC_MINI_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) SET_FIELD(DISEQC_MODE, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) value = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) SET_FIELD(DISEQC_MODE, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) value = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) SET_FIELD(DIS_PRECHARGE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) wait_dis(state, 0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) SET_REG(DISTXFIFO, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) SET_FIELD(DIS_PRECHARGE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) wait_dis(state, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static int sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) struct stv *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static const struct dvb_frontend_ops stv0910_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .name = "ST STV0910",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .symbol_rate_min = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .symbol_rate_max = 70000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) FE_CAN_2G_MODULATION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) FE_CAN_MULTISTREAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .sleep = sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .release = release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .i2c_gate_ctrl = gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .set_frontend = set_parameters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .get_frontend_algo = get_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .get_frontend = get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .tune = tune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .read_status = read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .set_tone = set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .diseqc_send_master_cmd = send_master_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .diseqc_send_burst = send_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct stv_base *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) list_for_each_entry(p, &stvlist, stvlist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (p->i2c == i2c && p->adr == adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static void stv0910_init_stats(struct stv *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) p->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) p->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) p->pre_bit_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) p->pre_bit_count.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) struct stv0910_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct stv *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) struct stv_base *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /* use safe tsspeed value if unspecified through stv0910_cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) state->nr = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) state->regoff = state->nr ? 0 : 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) state->search_range = 16000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) state->receive_mode = RCVMODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) state->cur_scrambling_code = (~0U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) state->single = cfg->single ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) base = match_base(i2c, cfg->adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) base->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) state->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) base = kzalloc(sizeof(*base), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) base->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) base->adr = cfg->adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) base->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) base->extclk = cfg->clk ? cfg->clk : 30000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) mutex_init(&base->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) mutex_init(&base->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) state->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (probe(state) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) cfg->adr, dev_name(&i2c->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) kfree(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) list_add(&base->stvlist, &stvlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) state->fe.ops = stv0910_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) state->fe.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) state->nr = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) stv0910_init_stats(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return &state->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) EXPORT_SYMBOL_GPL(stv0910_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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