^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * stv0900_sw.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for ST STV0900 satellite demodulator IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) ST Microelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "stv0900.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "stv0900_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "stv0900_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) s32 shiftx(s32 x, int demod, s32 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) if (demod == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) return x - shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int stv0900_check_signal_presence(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) s32 carr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) agc2_integr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) max_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int no_signal = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) | stv0900_read_reg(intp, CFR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) carr_offset = ge2comp(carr_offset, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) | stv0900_read_reg(intp, AGC2I0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) max_carrier = intp->srch_range[demod] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) max_carrier += (max_carrier / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) max_carrier = 65536 * (max_carrier / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) max_carrier /= intp->mclk / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (max_carrier > 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) max_carrier = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if ((agc2_integr > 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) || (carr_offset > (2 * max_carrier))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) || (carr_offset < (-2 * max_carrier)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) no_signal = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return no_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) s32 *frequency_inc, s32 *sw_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) s32 *steps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) s32 timeout, freq_inc, max_steps, srate, max_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum fe_stv0900_search_standard standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) srate = intp->symbol_rate[demod];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) max_carrier = intp->srch_range[demod] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) max_carrier += max_carrier / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) standard = intp->srch_standard[demod];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) max_carrier = 65536 * (max_carrier / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) max_carrier /= intp->mclk / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (max_carrier > 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) max_carrier = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) freq_inc = srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) freq_inc /= intp->mclk >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) freq_inc = freq_inc << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) switch (standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case STV0900_SEARCH_DVBS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case STV0900_SEARCH_DSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) freq_inc *= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) timeout = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case STV0900_SEARCH_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) freq_inc *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) timeout = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case STV0900_AUTO_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) freq_inc *= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) timeout = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) freq_inc /= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((freq_inc > max_carrier) || (freq_inc < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) freq_inc = max_carrier / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) timeout *= 27500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (srate > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) timeout /= srate / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if ((timeout > 100) || (timeout < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) max_steps = (max_carrier / freq_inc) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if ((max_steps > 100) || (max_steps < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) max_steps = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) freq_inc = max_carrier / max_steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *frequency_inc = freq_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *sw_timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *steps = max_steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s32 FreqIncr, s32 Timeout, int zigzag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) s32 MaxStep, enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int no_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) lock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) s32 stepCpt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) freqOffset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) max_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) max_carrier = intp->srch_range[demod] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) max_carrier += (max_carrier / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) max_carrier = 65536 * (max_carrier / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) max_carrier /= intp->mclk / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (max_carrier > 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) max_carrier = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (zigzag == TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) freqOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) freqOffset = -max_carrier + FreqIncr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) stepCpt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) stv0900_write_reg(intp, DMDISTATE, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) stv0900_write_reg(intp, DMDISTATE, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) stv0900_write_bits(intp, ALGOSWRST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (intp->chip_id == 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) stv0900_write_bits(intp, RST_HWARE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (zigzag == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (freqOffset >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) freqOffset = -freqOffset - 2 * FreqIncr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) freqOffset = -freqOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) freqOffset += + 2 * FreqIncr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) stepCpt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) lock = stv0900_get_demod_lock(intp, demod, Timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) no_signal = stv0900_check_signal_presence(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } while ((lock == FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) && (no_signal == FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) && ((freqOffset - FreqIncr) < max_carrier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) && ((freqOffset + FreqIncr) > -max_carrier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) && (stepCpt < MaxStep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) stv0900_write_bits(intp, ALGOSWRST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int stv0900_sw_algo(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int lock = FALSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) no_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) zigzag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) s32 s2fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) fqc_inc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sft_stp_tout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) trial_cntr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) max_steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &max_steps, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) switch (intp->srch_standard[demod]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case STV0900_SEARCH_DVBS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case STV0900_SEARCH_DSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (intp->chip_id >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) stv0900_write_reg(intp, CARFREQ, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stv0900_write_reg(intp, CARFREQ, 0xef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) stv0900_write_reg(intp, DMDCFGMD, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) zigzag = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case STV0900_SEARCH_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (intp->chip_id >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) stv0900_write_reg(intp, CORRELABS, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) stv0900_write_reg(intp, CORRELABS, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) stv0900_write_reg(intp, DMDCFGMD, 0x89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) zigzag = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case STV0900_AUTO_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) stv0900_write_reg(intp, CARFREQ, 0x3b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) stv0900_write_reg(intp, CORRELABS, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) stv0900_write_reg(intp, CARFREQ, 0xef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) stv0900_write_reg(intp, CORRELABS, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) stv0900_write_reg(intp, DMDCFGMD, 0xc9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) zigzag = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) trial_cntr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) lock = stv0900_search_carr_sw_loop(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fqc_inc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sft_stp_tout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) zigzag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) max_steps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) no_signal = stv0900_check_signal_presence(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) trial_cntr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if ((lock == TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) || (no_signal == TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) || (trial_cntr == 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) stv0900_write_reg(intp, CARFREQ, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) stv0900_write_reg(intp, CORRELABS, 0x9e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) stv0900_write_reg(intp, CARFREQ, 0xed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) stv0900_write_reg(intp, CORRELABS, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if ((stv0900_get_bits(intp, HEADER_MODE) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) STV0900_DVBS2_FOUND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (lock == TRUE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) msleep(sft_stp_tout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (s2fw < 0xd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) msleep(sft_stp_tout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) s2fw = stv0900_get_bits(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FLYWHEEL_CPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (s2fw < 0xd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) lock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (trial_cntr < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (intp->chip_id >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) stv0900_write_reg(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CORRELABS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) stv0900_write_reg(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) CORRELABS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) stv0900_write_reg(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DMDCFGMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0x89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } while ((lock == FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) && (trial_cntr < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) && (no_signal == FALSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) s32 rem1, rem2, intval1, intval2, srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (stv0900_get_bits(intp, SYMB_FREQ0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) srate, stv0900_get_bits(intp, SYMB_FREQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) stv0900_get_bits(intp, SYMB_FREQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) stv0900_get_bits(intp, SYMB_FREQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) stv0900_get_bits(intp, SYMB_FREQ3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) intval1 = (mclk) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) intval2 = (srate) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rem1 = (mclk) % 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rem2 = (srate) % 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) srate = (intval1 * intval2) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ((intval1 * rem2) >> 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ((intval2 * rem1) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 mclk, u32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 symb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) srate, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (srate > 60000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) symb = srate << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) symb /= (mclk >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } else if (srate > 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) symb = srate << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) symb /= (mclk >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) symb = srate << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) symb /= (mclk >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 mclk, u32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 symb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) srate = 105 * (srate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (srate > 60000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) symb = srate << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) symb /= (mclk >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else if (srate > 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) symb = srate << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) symb /= (mclk >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) symb = srate << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) symb /= (mclk >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (symb < 0x7fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) stv0900_write_reg(intp, SFRUP1, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 mclk, u32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 symb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) srate = 95 * (srate / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (srate > 60000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) symb = srate << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) symb /= (mclk >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else if (srate > 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) symb = srate << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) symb /= (mclk >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) symb = srate << 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) symb /= (mclk >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) s32 timingoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (stv0900_read_reg(intp, TMGREG2 + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) timingoffset = ge2comp(timingoffset, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (timingoffset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) timingoffset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) timingoffset /= 320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return timingoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) s32 rolloff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (intp->chip_id == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else if (intp->chip_id <= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) else /* cut 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 rolloff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (ro) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case STV0900_20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rolloff = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case STV0900_25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) rolloff = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case STV0900_35:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rolloff = 35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return srate + (srate * rolloff) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int stv0900_check_timing_lock(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int timingLock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) s32 i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) timingcpt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 car_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tmg_th_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tmg_th_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) car_freq = stv0900_read_reg(intp, CARFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) stv0900_write_reg(intp, TMGTHRISE, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) stv0900_write_reg(intp, TMGTHFALL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) stv0900_write_reg(intp, RTC, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) stv0900_write_reg(intp, RTCS2, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) stv0900_write_reg(intp, CARFREQ, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) stv0900_write_reg(intp, CFRINIT1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) stv0900_write_reg(intp, CFRINIT0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) stv0900_write_reg(intp, AGC2REF, 0x65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) stv0900_write_reg(intp, DMDISTATE, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) msleep(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) timingcpt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (timingcpt >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) timingLock = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) stv0900_write_reg(intp, AGC2REF, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) stv0900_write_reg(intp, RTC, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) stv0900_write_reg(intp, RTCS2, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) stv0900_write_reg(intp, CARFREQ, car_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return timingLock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) s32 demod_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int lock = FALSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) d = demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) s32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) search_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) locktimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) currier_step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) nb_steps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) current_step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tuner_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) srate = intp->symbol_rate[d];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) search_range = intp->srch_range[d];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (srate >= 10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) locktimeout = demod_timeout / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) locktimeout = demod_timeout / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) lock = stv0900_get_demod_lock(intp, d, locktimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (lock != FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (srate >= 10000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (stv0900_check_timing_lock(intp, d) == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) stv0900_write_reg(intp, DMDISTATE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) stv0900_write_reg(intp, DMDISTATE, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) lock = stv0900_get_demod_lock(intp, d, demod_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) lock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (intp->chip_id <= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (srate <= 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) currier_step = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) else if (srate <= 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) currier_step = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else if (srate <= 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) currier_step = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else if (srate <= 10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) currier_step = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) currier_step = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (srate >= 2000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) timeout = (demod_timeout / 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (timeout > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) timeout = (demod_timeout / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*cut 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) currier_step = srate / 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) timeout = (demod_timeout * 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) nb_steps = ((search_range / 1000) / currier_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if ((nb_steps % 2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) nb_steps += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (nb_steps <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) nb_steps = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else if (nb_steps > 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) nb_steps = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) current_step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) direction = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (intp->chip_id <= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tuner_freq = intp->freq[d];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) intp->rolloff) + intp->symbol_rate[d];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) tuner_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) while ((current_step <= nb_steps) && (lock == FALSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (direction > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) tuner_freq += (current_step * currier_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) tuner_freq -= (current_step * currier_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (intp->chip_id <= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (intp->tuner_type[d] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) stv0900_set_tuner_auto(intp, tuner_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) intp->bw[d], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) stv0900_write_reg(intp, DMDISTATE, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) stv0900_write_reg(intp, CFRINIT1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) stv0900_write_reg(intp, CFRINIT0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) stv0900_write_reg(intp, DMDISTATE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) stv0900_write_reg(intp, DMDISTATE, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) stv0900_write_reg(intp, DMDISTATE, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) freq = (tuner_freq * 65536) / (intp->mclk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) stv0900_write_reg(intp, DMDISTATE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) stv0900_write_reg(intp, DMDISTATE, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) lock = stv0900_get_demod_lock(intp, d, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) direction *= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) current_step++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) s32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) enum fe_stv0900_search_algo algo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) switch (algo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case STV0900_BLIND_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (srate <= 1500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (*demod_timeout) = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) (*fec_timeout) = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else if (srate <= 5000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) (*demod_timeout) = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (*fec_timeout) = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (*demod_timeout) = 700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) (*fec_timeout) = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case STV0900_COLD_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case STV0900_WARM_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (srate <= 1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (*demod_timeout) = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (*fec_timeout) = 1700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } else if (srate <= 2000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (*demod_timeout) = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) (*fec_timeout) = 1100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } else if (srate <= 5000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) (*demod_timeout) = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (*fec_timeout) = 550;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } else if (srate <= 10000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (*demod_timeout) = 700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (*fec_timeout) = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else if (srate <= 20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (*demod_timeout) = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (*fec_timeout) = 130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (*demod_timeout) = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) (*fec_timeout) = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (algo == STV0900_WARM_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) (*demod_timeout) /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) s32 vth_reg = VTH12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) stv0900_write_reg(intp, vth_reg++, 0xd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) stv0900_write_reg(intp, vth_reg++, 0x7d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) stv0900_write_reg(intp, vth_reg++, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) stv0900_write_reg(intp, vth_reg++, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) stv0900_write_reg(intp, vth_reg++, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) stv0900_write_reg(intp, vth_reg++, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) enum fe_stv0900_search_standard standard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) enum fe_stv0900_fec fec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dprintk("%s: ViterbiStandard = ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) switch (standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case STV0900_AUTO_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dprintk("Auto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) stv0900_write_reg(intp, FECM, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) stv0900_write_reg(intp, PRVIT, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case STV0900_SEARCH_DVBS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dprintk("DVBS1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) stv0900_write_reg(intp, FECM, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) switch (fec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case STV0900_FEC_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) stv0900_write_reg(intp, PRVIT, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case STV0900_FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) stv0900_write_reg(intp, PRVIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case STV0900_FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) stv0900_write_reg(intp, PRVIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case STV0900_FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) stv0900_write_reg(intp, PRVIT, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case STV0900_FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) stv0900_write_reg(intp, PRVIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case STV0900_FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) stv0900_write_reg(intp, PRVIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case STV0900_SEARCH_DSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dprintk("DSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) stv0900_write_reg(intp, FECM, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) switch (fec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case STV0900_FEC_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) stv0900_write_reg(intp, PRVIT, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case STV0900_FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) stv0900_write_reg(intp, PRVIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case STV0900_FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) stv0900_write_reg(intp, PRVIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case STV0900_FEC_6_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) stv0900_write_reg(intp, PRVIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) enum fe_stv0900_fec prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) switch (rate_fld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) prate = STV0900_FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case 18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) prate = STV0900_FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case 21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) prate = STV0900_FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) prate = STV0900_FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) prate = STV0900_FEC_6_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 26:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) prate = STV0900_FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) prate = STV0900_FEC_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) enum fe_stv0900_demod_num demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (intp->chip_id >= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (srate >= 15000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) stv0900_write_reg(intp, ACLC, 0x2b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) stv0900_write_reg(intp, BCLC, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } else if ((srate >= 7000000) && (15000000 > srate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) stv0900_write_reg(intp, ACLC, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) stv0900_write_reg(intp, BCLC, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) } else if (srate < 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) stv0900_write_reg(intp, ACLC, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) stv0900_write_reg(intp, BCLC, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) } else { /*cut 2.0 and 1.x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) stv0900_write_reg(intp, ACLC, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) stv0900_write_reg(intp, BCLC, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void stv0900_track_optimization(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) s32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pilots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) aclc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) freq1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) freq0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) i = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) timed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) timef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) blind_tun_sw = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) enum fe_stv0900_modcode foundModcod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) srate += stv0900_get_timing_offst(intp, srate, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) switch (intp->result[demod].standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case STV0900_DVBS1_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case STV0900_DSS_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dprintk("%s: found DVB-S or DSS\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) stv0900_write_bits(intp, DVBS1_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) stv0900_write_bits(intp, DVBS2_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (intp->chip_id < 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) stv0900_write_reg(intp, ERRCTRL1, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) stv0900_write_reg(intp, GAUSSR0, 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) stv0900_write_reg(intp, CCIR0, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) stv0900_write_reg(intp, GAUSSR0, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) stv0900_write_reg(intp, CCIR0, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) stv0900_write_reg(intp, ERRCTRL1, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case STV0900_DVBS2_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dprintk("%s: found DVB-S2\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) stv0900_write_bits(intp, DVBS1_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) stv0900_write_bits(intp, DVBS2_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) stv0900_write_reg(intp, ACLC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) stv0900_write_reg(intp, BCLC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) aclc = stv0900_get_optim_carr_loop(srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) foundModcod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pilots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) intp->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (foundModcod <= STV0900_QPSK_910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) stv0900_write_reg(intp, ACLC2S2Q, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) else if (foundModcod <= STV0900_8PSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) stv0900_write_reg(intp, ACLC2S28, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if ((intp->demod_mode == STV0900_SINGLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) (foundModcod > STV0900_8PSK_910)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (foundModcod <= STV0900_16APSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) stv0900_write_reg(intp, ACLC2S216A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else if (foundModcod <= STV0900_32APSK_910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) stv0900_write_reg(intp, ACLC2S232A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) modulation = intp->result[demod].modulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) aclc = stv0900_get_optim_short_carr_loop(srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) modulation, intp->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (modulation == STV0900_QPSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) stv0900_write_reg(intp, ACLC2S2Q, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) else if (modulation == STV0900_8PSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) stv0900_write_reg(intp, ACLC2S28, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } else if (modulation == STV0900_16APSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) stv0900_write_reg(intp, ACLC2S216A, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) } else if (modulation == STV0900_32APSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) stv0900_write_reg(intp, ACLC2S232A, aclc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (intp->chip_id <= 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (intp->demod_mode != STV0900_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) stv0900_activate_s2_modcod(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) stv0900_write_reg(intp, ERRCTRL1, 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case STV0900_UNKNOWN_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dprintk("%s: found unknown standard\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) stv0900_write_bits(intp, DVBS1_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) stv0900_write_bits(intp, DVBS2_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) freq1 = stv0900_read_reg(intp, CFR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) freq0 = stv0900_read_reg(intp, CFR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) stv0900_write_reg(intp, SFRSTEP, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) stv0900_write_bits(intp, SCAN_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) stv0900_write_reg(intp, TMGCFG2, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) blind_tun_sw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) (intp->srch_standard[demod] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) STV0900_SEARCH_DSS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) (intp->srch_standard[demod] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) STV0900_AUTO_SEARCH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) stv0900_write_reg(intp, VAVSRVIT, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) stv0900_write_reg(intp, VITSCALE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (intp->chip_id < 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) stv0900_write_reg(intp, CARHDR, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (intp->chip_id == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) stv0900_write_reg(intp, CORRELEXP, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) stv0900_write_reg(intp, AGC2REF, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if ((intp->chip_id >= 0x20) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) (blind_tun_sw == 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) (intp->symbol_rate[demod] < 10000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) stv0900_write_reg(intp, CFRINIT1, freq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) stv0900_write_reg(intp, CFRINIT0, freq0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) intp->bw[demod] = stv0900_carrier_width(srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) intp->rolloff) + 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (intp->srch_algo[demod] != STV0900_WARM_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (intp->tuner_type[demod] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) stv0900_set_tuner_auto(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) intp->freq[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) intp->bw[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) stv0900_set_bandwidth(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) intp->bw[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) (intp->symbol_rate[demod] < 10000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) stv0900_get_lock_timeout(&timed, &timef, srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) STV0900_WARM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) stv0900_write_reg(intp, DMDISTATE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) stv0900_write_reg(intp, CFRINIT1, freq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) stv0900_write_reg(intp, CFRINIT0, freq0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) stv0900_write_reg(intp, DMDISTATE, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) while ((stv0900_get_demod_lock(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) timed / 2) == FALSE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) (i <= 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) stv0900_write_reg(intp, DMDISTATE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) stv0900_write_reg(intp, CFRINIT1, freq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) stv0900_write_reg(intp, CFRINIT0, freq0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) stv0900_write_reg(intp, DMDISTATE, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (intp->chip_id >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) stv0900_write_reg(intp, CARFREQ, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) (intp->result[demod].standard == STV0900_DSS_STANDARD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) stv0900_set_viterbi_tracq(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int stv0900_get_fec_lock(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) enum fe_stv0900_demod_num demod, s32 time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) s32 timer = 0, lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) enum fe_stv0900_search_state dmd_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dmd_state = stv0900_get_bits(intp, HEADER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) while ((timer < time_out) && (lock == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) switch (dmd_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) case STV0900_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case STV0900_PLH_DETECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case STV0900_DVBS2_FOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) case STV0900_DVBS_FOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) lock = stv0900_get_bits(intp, LOCKEDVIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (lock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) timer += 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int stv0900_wait_for_lock(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) enum fe_stv0900_demod_num demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) s32 dmd_timeout, s32 fec_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) s32 timer = 0, lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dprintk("%s: Timer = %d, time_out = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) __func__, timer, fec_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) while ((timer < fec_timeout) && (lock == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) timer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dprintk("%s: DEMOD LOCK OK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dprintk("%s: DEMOD LOCK FAIL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) enum fe_stv0900_tracking_standard fnd_standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) switch (hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) fnd_standard = STV0900_DVBS2_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (stv0900_get_bits(intp, DSS_DVB) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) fnd_standard = STV0900_DSS_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fnd_standard = STV0900_DVBS1_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) fnd_standard = STV0900_UNKNOWN_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dprintk("%s: standard %d\n", __func__, fnd_standard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return fnd_standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) s32 derot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) rem1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) rem2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) intval1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) intval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (stv0900_get_bits(intp, CAR_FREQ0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) derot = ge2comp(derot, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) intval1 = mclk >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) intval2 = derot >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) rem1 = mclk % 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) rem2 = derot % 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) derot = (intval1 * intval2) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ((intval1 * rem2) >> 12) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ((intval2 * rem1) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return derot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct dvb_frontend_ops *frontend_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct dvb_tuner_ops *tuner_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u32 freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) frontend_ops = &fe->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) tuner_ops = &frontend_ops->tuner_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (tuner_ops->get_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if ((tuner_ops->get_frequency(fe, &freq)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dprintk("%s: Invalid parameter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dprintk("%s: Frequency=%d\n", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct stv0900_signal_info *result = &intp->result[demod];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) s32 offsetFreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) srate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int i = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) d = demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u8 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) timing = stv0900_read_reg(intp, TMGREG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) stv0900_write_reg(intp, SFRSTEP, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) timing = stv0900_read_reg(intp, TMGREG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) i += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) result->standard = stv0900_get_standard(fe, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (intp->tuner_type[demod] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) result->frequency = stv0900_get_freq_auto(intp, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) result->frequency = stv0900_get_tuner_freq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) result->frequency += offsetFreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) result->symbol_rate += srate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) result->fec = stv0900_get_vit_fec(intp, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) switch (result->standard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) case STV0900_DVBS2_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (result->modcode <= STV0900_QPSK_910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) result->modulation = STV0900_QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) else if (result->modcode <= STV0900_8PSK_910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) result->modulation = STV0900_8PSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) else if (result->modcode <= STV0900_16APSK_910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) result->modulation = STV0900_16APSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) else if (result->modcode <= STV0900_32APSK_910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) result->modulation = STV0900_32APSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) result->modulation = STV0900_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) case STV0900_DVBS1_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) case STV0900_DSS_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) result->spectrum = stv0900_get_bits(intp, IQINV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) result->modulation = STV0900_QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) (intp->symbol_rate[d] < 10000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) offsetFreq = result->frequency - intp->freq[d];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (intp->tuner_type[demod] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) intp->freq[d] = stv0900_get_freq_auto(intp, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) intp->freq[d] = stv0900_get_tuner_freq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) range = STV0900_RANGEOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) else if (abs(offsetFreq) <=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) (stv0900_carrier_width(result->symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) result->rolloff) / 2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) range = STV0900_RANGEOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) } else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) range = STV0900_RANGEOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dprintk("%s: range %d\n", __func__, range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) s32 srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) demod_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) fec_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) freq1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) freq0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) intp->result[demod].locked = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) srate += stv0900_get_timing_offst(intp, srate, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) srate, STV0900_WARM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) freq1 = stv0900_read_reg(intp, CFR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) freq0 = stv0900_read_reg(intp, CFR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) stv0900_write_bits(intp, SPECINV_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) STV0900_IQ_FORCE_SWAPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) stv0900_write_reg(intp, DMDISTATE, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) stv0900_write_reg(intp, CFRINIT1, freq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) stv0900_write_reg(intp, CFRINIT0, freq0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) stv0900_write_reg(intp, DMDISTATE, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (stv0900_wait_for_lock(intp, demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) demod_timeout, fec_timeout) == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) intp->result[demod].locked = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) signal_type = stv0900_get_signal_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) stv0900_track_optimization(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) stv0900_write_bits(intp, SPECINV_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) STV0900_IQ_FORCE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) stv0900_write_reg(intp, DMDISTATE, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) stv0900_write_reg(intp, CFRINIT1, freq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) stv0900_write_reg(intp, CFRINIT0, freq0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) stv0900_write_reg(intp, DMDISTATE, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (stv0900_wait_for_lock(intp, demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) demod_timeout, fec_timeout) == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) intp->result[demod].locked = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) signal_type = stv0900_get_signal_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) stv0900_track_optimization(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) intp->result[demod].locked = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return signal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) u32 minagc2level = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) agc2level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) init_freq, freq_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) s32 i, j, nb_steps, direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) stv0900_write_reg(intp, AGC2REF, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) stv0900_write_bits(intp, SCAN_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) stv0900_write_bits(intp, AUTO_GUP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) stv0900_write_bits(intp, AUTO_GLOW, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) stv0900_write_reg(intp, DMDT0M, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) nb_steps = -1 + (intp->srch_range[demod] / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) nb_steps /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) nb_steps = (2 * nb_steps) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (nb_steps < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) nb_steps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) direction = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) freq_step = (1000000 << 8) / (intp->mclk >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) init_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) for (i = 0; i < nb_steps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (direction > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) init_freq = init_freq + (freq_step * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) init_freq = init_freq - (freq_step * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) direction *= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) stv0900_write_reg(intp, DMDISTATE, 0x5C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) stv0900_write_reg(intp, DMDISTATE, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) agc2level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) for (j = 0; j < 10; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) | stv0900_read_reg(intp, AGC2I0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) agc2level /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (agc2level < minagc2level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) minagc2level = agc2level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return (u16)minagc2level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int timing_lck = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) s32 i, timingcpt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) direction = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) nb_steps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) current_step = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) tuner_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) u32 agc2_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) coarse_srate = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) agc2_integr = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) currier_step = 1200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (intp->chip_id >= 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) agc2_th = 0x2e00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) agc2_th = 0x1f00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) stv0900_write_reg(intp, TMGCFG, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) stv0900_write_reg(intp, TMGTHRISE, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) stv0900_write_reg(intp, TMGTHFALL, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) stv0900_write_bits(intp, SCAN_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) stv0900_write_reg(intp, SFRUP1, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) stv0900_write_reg(intp, SFRUP0, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) stv0900_write_reg(intp, SFRLOW1, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) stv0900_write_reg(intp, SFRLOW0, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) stv0900_write_reg(intp, DMDT0M, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) stv0900_write_reg(intp, AGC2REF, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (intp->chip_id >= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) stv0900_write_reg(intp, CARFREQ, 0x99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) stv0900_write_reg(intp, SFRSTEP, 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) } else if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) stv0900_write_reg(intp, CARFREQ, 0x6a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) stv0900_write_reg(intp, SFRSTEP, 0x95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) stv0900_write_reg(intp, CARFREQ, 0xed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) stv0900_write_reg(intp, SFRSTEP, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (intp->symbol_rate[demod] <= 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) currier_step = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) else if (intp->symbol_rate[demod] <= 5000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) currier_step = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) else if (intp->symbol_rate[demod] <= 12000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) currier_step = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) currier_step = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) nb_steps /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) nb_steps = (2 * nb_steps) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (nb_steps < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) nb_steps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) else if (nb_steps > 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) nb_steps = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) currier_step = (intp->srch_range[demod] / 1000) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) current_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) direction = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) tuner_freq = intp->freq[demod];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) while ((timing_lck == FALSE) && (current_step < nb_steps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) stv0900_write_reg(intp, DMDISTATE, 0x5f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) stv0900_write_bits(intp, DEMOD_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) timingcpt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) stv0900_read_reg(intp, AGC2I0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) agc2_integr /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) current_step++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) direction *= -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) tuner_freq, agc2_integr, coarse_srate, timingcpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if ((timingcpt >= 5) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) (agc2_integr < agc2_th) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) (coarse_srate < 55000000) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) (coarse_srate > 850000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) timing_lck = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) else if (current_step < nb_steps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (direction > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) tuner_freq += (current_step * currier_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) tuner_freq -= (current_step * currier_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (intp->tuner_type[demod] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) stv0900_set_tuner_auto(intp, tuner_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) intp->bw[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) stv0900_set_tuner(fe, tuner_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) intp->bw[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (timing_lck == FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) coarse_srate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return coarse_srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) u32 coarse_srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) coarse_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) symb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) symbmax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) symbmin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) symbcomp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (coarse_srate > 3000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) symbmax = 13 * (coarse_srate / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) symbmax = (symbmax / 1000) * 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) symbmax /= (intp->mclk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) symbmin = 10 * (coarse_srate / 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) symbmin = (symbmin / 1000)*65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) symbmin /= (intp->mclk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) symb = (coarse_srate / 1000) * 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) symb /= (intp->mclk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) symbmax = 13 * (coarse_srate / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) symbmax = (symbmax / 100) * 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) symbmax /= (intp->mclk / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) symbmin = 10 * (coarse_srate / 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) symbmin = (symbmin / 100) * 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) symbmin /= (intp->mclk / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) symb = (coarse_srate / 100) * 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) symb /= (intp->mclk / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) symbcomp = 13 * (coarse_srate / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) | stv0900_read_reg(intp, CFR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (symbcomp < intp->symbol_rate[demod])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) coarse_srate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) stv0900_write_reg(intp, DMDISTATE, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) stv0900_write_reg(intp, TMGCFG2, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) stv0900_write_reg(intp, TMGTHRISE, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) stv0900_write_reg(intp, TMGTHFALL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) stv0900_write_reg(intp, TMGCFG, 0xd2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) stv0900_write_reg(intp, AGC2REF, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (intp->chip_id >= 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) stv0900_write_reg(intp, CARFREQ, 0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) else if (intp->chip_id >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) stv0900_write_reg(intp, CARFREQ, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) stv0900_write_reg(intp, CARFREQ, 0xed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) stv0900_write_reg(intp, DMDT0M, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) stv0900_write_reg(intp, DMDISTATE, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return coarse_srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static int stv0900_blind_search_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u8 k_ref_tmg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) k_ref_tmg_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) k_ref_tmg_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) u32 coarse_srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) agc2_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) int lock = FALSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) coarse_fail = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) s32 demod_timeout = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) fec_timeout = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) fail_cpt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) agc2_overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) u16 agc2_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) u8 dstatus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (intp->chip_id < 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) k_ref_tmg_max = 233;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) k_ref_tmg_min = 143;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) k_ref_tmg_max = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) k_ref_tmg_min = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (intp->chip_id <= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (agc2_int > agc2_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) return FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (intp->chip_id == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) stv0900_write_reg(intp, CORRELEXP, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (intp->chip_id < 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) stv0900_write_reg(intp, CARHDR, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) stv0900_write_reg(intp, CARHDR, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (intp->chip_id <= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) stv0900_write_reg(intp, CARCFG, 0xc4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) stv0900_write_reg(intp, CARCFG, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) stv0900_write_reg(intp, RTCS2, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) stv0900_write_reg(intp, EQUALCFG, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) stv0900_write_reg(intp, FFECFG, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) stv0900_write_reg(intp, VITSCALE, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) stv0900_write_reg(intp, VAVSRVIT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) k_ref_tmg = k_ref_tmg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (stv0900_search_srate_coarse(fe) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) coarse_srate = stv0900_search_srate_fine(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (coarse_srate != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) stv0900_get_lock_timeout(&demod_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) &fec_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) coarse_srate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) STV0900_BLIND_SEARCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) lock = stv0900_get_demod_lock(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) demod_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) lock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) fail_cpt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) agc2_overflow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) | stv0900_read_reg(intp, AGC2I0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (agc2_int >= 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) agc2_overflow++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) dstatus2 = stv0900_read_reg(intp, DSTATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (((dstatus2 & 0x1) == 0x1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ((dstatus2 >> 7) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) fail_cpt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if ((fail_cpt > 7) || (agc2_overflow > 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) coarse_fail = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) lock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) k_ref_tmg -= 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) } while ((k_ref_tmg >= k_ref_tmg_min) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) (lock == FALSE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) (coarse_fail == FALSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) s32 vth_reg = VTH12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) stv0900_write_reg(intp, vth_reg++, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) stv0900_write_reg(intp, vth_reg++, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) stv0900_write_reg(intp, vth_reg++, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) stv0900_write_reg(intp, vth_reg++, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) stv0900_write_reg(intp, vth_reg++, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) stv0900_write_reg(intp, vth_reg++, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static void stv0900_set_search_standard(struct stv0900_internal *intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) enum fe_stv0900_demod_num demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) switch (intp->srch_standard[demod]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) case STV0900_SEARCH_DVBS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) dprintk("Search Standard = DVBS1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) case STV0900_SEARCH_DSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) dprintk("Search Standard = DSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) case STV0900_SEARCH_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dprintk("Search Standard = DVBS2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) case STV0900_AUTO_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dprintk("Search Standard = AUTO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) switch (intp->srch_standard[demod]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) case STV0900_SEARCH_DVBS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) case STV0900_SEARCH_DSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) stv0900_write_bits(intp, DVBS1_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) stv0900_write_bits(intp, DVBS2_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) stv0900_write_bits(intp, STOP_CLKVIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) stv0900_set_dvbs1_track_car_loop(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) intp->symbol_rate[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) stv0900_write_reg(intp, CAR2CFG, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) stv0900_set_viterbi_acq(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) stv0900_set_viterbi_standard(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) intp->srch_standard[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) intp->fec[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) case STV0900_SEARCH_DVBS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) stv0900_write_bits(intp, DVBS1_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) stv0900_write_bits(intp, DVBS2_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) stv0900_write_bits(intp, STOP_CLKVIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) stv0900_write_reg(intp, ACLC, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) stv0900_write_reg(intp, BCLC, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) stv0900_write_reg(intp, CAR2CFG, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) stv0900_write_reg(intp, CAR2CFG, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (intp->demod_mode != STV0900_SINGLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (intp->chip_id <= 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) stv0900_stop_all_s2_modcod(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) stv0900_activate_s2_modcod(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) stv0900_activate_s2_modcod_single(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) stv0900_set_viterbi_tracq(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case STV0900_AUTO_SEARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) stv0900_write_bits(intp, DVBS1_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) stv0900_write_bits(intp, DVBS2_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) stv0900_write_bits(intp, STOP_CLKVIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) stv0900_write_reg(intp, ACLC, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) stv0900_write_reg(intp, BCLC, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) stv0900_set_dvbs1_track_car_loop(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) intp->symbol_rate[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) stv0900_write_reg(intp, CAR2CFG, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) stv0900_write_reg(intp, CAR2CFG, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (intp->demod_mode != STV0900_SINGLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (intp->chip_id <= 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) stv0900_stop_all_s2_modcod(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) stv0900_activate_s2_modcod(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) stv0900_activate_s2_modcod_single(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) stv0900_set_viterbi_tracq(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) stv0900_set_viterbi_standard(intp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) intp->srch_standard[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) intp->fec[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct stv0900_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct stv0900_internal *intp = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) enum fe_stv0900_demod_num demod = state->demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) s32 demod_timeout = 500, fec_timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) s32 aq_power, agc1_power, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) int lock = FALSE, low_sr = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) enum fe_stv0900_search_algo algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) int no_signal = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dprintk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) algo = intp->srch_algo[demod];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) stv0900_write_bits(intp, RST_HWARE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) stv0900_write_reg(intp, DMDISTATE, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (intp->symbol_rate[demod] > 5000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) stv0900_write_reg(intp, CORRELABS, 0x9e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) stv0900_write_reg(intp, CORRELABS, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) stv0900_write_reg(intp, CORRELABS, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) intp->symbol_rate[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) intp->srch_algo[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) intp->bw[demod] = 2 * 36000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) stv0900_write_reg(intp, TMGCFG2, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) stv0900_write_reg(intp, CORRELMANT, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) stv0900_write_reg(intp, DMDT0M, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) stv0900_write_reg(intp, TMGCFG, 0xd2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (intp->symbol_rate[demod] < 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) stv0900_write_reg(intp, CORRELMANT, 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) stv0900_write_reg(intp, CORRELMANT, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) stv0900_write_reg(intp, AGC2REF, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) intp->bw[demod] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) stv0900_carrier_width(intp->symbol_rate[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) intp->rolloff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) stv0900_write_reg(intp, KREFTMG, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (intp->srch_algo[demod] == STV0900_COLD_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) intp->bw[demod] += 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) intp->bw[demod] *= 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) intp->bw[demod] /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) } else if (intp->srch_algo[demod] == STV0900_WARM_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) intp->bw[demod] += 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) stv0900_write_reg(intp, KREFTMG, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) intp->bw[demod] += 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) intp->bw[demod] *= 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) intp->bw[demod] /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) stv0900_write_reg(intp, TMGCFG2, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) stv0900_set_symbol_rate(intp, intp->mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) intp->symbol_rate[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) stv0900_set_max_symbol_rate(intp, intp->mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) intp->symbol_rate[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) stv0900_set_min_symbol_rate(intp, intp->mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) intp->symbol_rate[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (intp->symbol_rate[demod] >= 10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) low_sr = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) low_sr = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (intp->tuner_type[demod] == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) stv0900_set_tuner_auto(intp, intp->freq[demod],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) intp->bw[demod], demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) stv0900_get_bits(intp, AGCIQ_VALUE0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) aq_power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (agc1_power == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) aq_power += (stv0900_get_bits(intp, POWER_I) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) stv0900_get_bits(intp, POWER_Q)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) aq_power /= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) intp->result[demod].locked = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) signal_type = STV0900_NOAGC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) stv0900_write_bits(intp, SPECINV_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) intp->srch_iq_inv[demod]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (intp->chip_id <= 0x20) /*cut 2.0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) else /*cut 3.0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) stv0900_set_search_standard(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) stv0900_start_search(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (signal_type == STV0900_NOAGC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return signal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (intp->chip_id == 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) stv0900_write_bits(intp, RST_HWARE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (algo == STV0900_BLIND_SEARCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) lock = stv0900_blind_search_algo(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) else if (algo == STV0900_COLD_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) else if (algo == STV0900_WARM_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (low_sr == FALSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (stv0900_check_timing_lock(intp, demod) == TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) lock = stv0900_sw_algo(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (lock == TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) signal_type = stv0900_get_signal_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) stv0900_track_optimization(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (intp->chip_id <= 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if ((stv0900_get_standard(fe, 0) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) STV0900_DVBS1_STANDARD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) (stv0900_get_standard(fe, 1) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) STV0900_DVBS1_STANDARD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) stv0900_write_bits(intp, RST_HWARE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) } else if (intp->chip_id >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) stv0900_write_bits(intp, RST_HWARE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) stv0900_write_bits(intp, RST_HWARE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (stv0900_wait_for_lock(intp, demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) fec_timeout, fec_timeout) == TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) lock = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) intp->result[demod].locked = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (intp->result[demod].standard ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) STV0900_DVBS2_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) stv0900_set_dvbs2_rolloff(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) stv0900_write_reg(intp, ERRCTRL1, 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) stv0900_write_reg(intp, ERRCTRL1, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) stv0900_write_reg(intp, FBERCPT4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) stv0900_write_reg(intp, ERRCTRL2, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) lock = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) signal_type = STV0900_NODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) no_signal = stv0900_check_signal_presence(intp, demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) intp->result[demod].locked = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return signal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (intp->chip_id > 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) intp->result[demod].locked = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return signal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) signal_type = stv0900_dvbs1_acq_workaround(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return signal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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