Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    3)  * stv0900_reg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    5)  * Driver for ST STV0900 satellite demodulator IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    7)  * Copyright (C) ST Microelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    8)  * Copyright (C) 2009 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300    9)  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   12) #ifndef STV0900_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   13) #define STV0900_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   15) extern s32 shiftx(s32 x, int demod, s32 shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   17) #define REGx(x) shiftx(x, demod, 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   18) #define FLDx(x) shiftx(x, demod, 0x2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   20) /*MID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   21) #define R0900_MID 0xf100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   22) #define F0900_MCHIP_IDENT 0xf10000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   23) #define F0900_MRELEASE 0xf100000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   25) /*DACR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   26) #define R0900_DACR1 0xf113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   27) #define F0900_DAC_MODE 0xf11300e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   28) #define F0900_DAC_VALUE1 0xf113000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   30) /*DACR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   31) #define R0900_DACR2 0xf114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   32) #define F0900_DAC_VALUE0 0xf11400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   34) /*OUTCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   35) #define R0900_OUTCFG 0xf11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   36) #define F0900_OUTSERRS1_HZ 0xf11c0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   37) #define F0900_OUTSERRS2_HZ 0xf11c0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   38) #define F0900_OUTSERRS3_HZ 0xf11c0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   39) #define F0900_OUTPARRS3_HZ 0xf11c0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   41) /*IRQSTATUS3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   42) #define R0900_IRQSTATUS3 0xf120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   43) #define F0900_SPLL_LOCK 0xf1200020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   44) #define F0900_SSTREAM_LCK_3 0xf1200010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   45) #define F0900_SSTREAM_LCK_2 0xf1200008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   46) #define F0900_SSTREAM_LCK_1 0xf1200004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   47) #define F0900_SDVBS1_PRF_2 0xf1200002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   48) #define F0900_SDVBS1_PRF_1 0xf1200001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   50) /*IRQSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   51) #define R0900_IRQSTATUS2 0xf121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   52) #define F0900_SSPY_ENDSIM_3 0xf1210080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   53) #define F0900_SSPY_ENDSIM_2 0xf1210040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   54) #define F0900_SSPY_ENDSIM_1 0xf1210020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   55) #define F0900_SPKTDEL_ERROR_2 0xf1210010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   56) #define F0900_SPKTDEL_LOCKB_2 0xf1210008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   57) #define F0900_SPKTDEL_LOCK_2 0xf1210004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   58) #define F0900_SPKTDEL_ERROR_1 0xf1210002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   59) #define F0900_SPKTDEL_LOCKB_1 0xf1210001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   61) /*IRQSTATUS1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   62) #define R0900_IRQSTATUS1 0xf122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   63) #define F0900_SPKTDEL_LOCK_1 0xf1220080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   64) #define F0900_SDEMOD_LOCKB_2 0xf1220004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   65) #define F0900_SDEMOD_LOCK_2 0xf1220002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   66) #define F0900_SDEMOD_IRQ_2 0xf1220001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   68) /*IRQSTATUS0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   69) #define R0900_IRQSTATUS0 0xf123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   70) #define F0900_SDEMOD_LOCKB_1 0xf1230080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   71) #define F0900_SDEMOD_LOCK_1 0xf1230040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   72) #define F0900_SDEMOD_IRQ_1 0xf1230020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   73) #define F0900_SBCH_ERRFLAG 0xf1230010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   74) #define F0900_SDISEQC2RX_IRQ 0xf1230008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   75) #define F0900_SDISEQC2TX_IRQ 0xf1230004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   76) #define F0900_SDISEQC1RX_IRQ 0xf1230002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   77) #define F0900_SDISEQC1TX_IRQ 0xf1230001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   79) /*IRQMASK3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   80) #define R0900_IRQMASK3 0xf124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   81) #define F0900_MPLL_LOCK 0xf1240020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   82) #define F0900_MSTREAM_LCK_3 0xf1240010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   83) #define F0900_MSTREAM_LCK_2 0xf1240008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   84) #define F0900_MSTREAM_LCK_1 0xf1240004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   85) #define F0900_MDVBS1_PRF_2 0xf1240002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   86) #define F0900_MDVBS1_PRF_1 0xf1240001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   88) /*IRQMASK2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   89) #define R0900_IRQMASK2 0xf125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   90) #define F0900_MSPY_ENDSIM_3 0xf1250080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   91) #define F0900_MSPY_ENDSIM_2 0xf1250040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   92) #define F0900_MSPY_ENDSIM_1 0xf1250020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   93) #define F0900_MPKTDEL_ERROR_2 0xf1250010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   94) #define F0900_MPKTDEL_LOCKB_2 0xf1250008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   95) #define F0900_MPKTDEL_LOCK_2 0xf1250004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   96) #define F0900_MPKTDEL_ERROR_1 0xf1250002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   97) #define F0900_MPKTDEL_LOCKB_1 0xf1250001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   99) /*IRQMASK1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  100) #define R0900_IRQMASK1 0xf126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  101) #define F0900_MPKTDEL_LOCK_1 0xf1260080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  102) #define F0900_MEXTPINB2 0xf1260040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  103) #define F0900_MEXTPIN2 0xf1260020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  104) #define F0900_MEXTPINB1 0xf1260010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  105) #define F0900_MEXTPIN1 0xf1260008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  106) #define F0900_MDEMOD_LOCKB_2 0xf1260004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  107) #define F0900_MDEMOD_LOCK_2 0xf1260002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  108) #define F0900_MDEMOD_IRQ_2 0xf1260001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  110) /*IRQMASK0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  111) #define R0900_IRQMASK0 0xf127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  112) #define F0900_MDEMOD_LOCKB_1 0xf1270080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  113) #define F0900_MDEMOD_LOCK_1 0xf1270040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  114) #define F0900_MDEMOD_IRQ_1 0xf1270020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  115) #define F0900_MBCH_ERRFLAG 0xf1270010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  116) #define F0900_MDISEQC2RX_IRQ 0xf1270008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  117) #define F0900_MDISEQC2TX_IRQ 0xf1270004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  118) #define F0900_MDISEQC1RX_IRQ 0xf1270002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  119) #define F0900_MDISEQC1TX_IRQ 0xf1270001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  121) /*I2CCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  122) #define R0900_I2CCFG 0xf129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  123) #define F0900_I2C_FASTMODE 0xf1290008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  124) #define F0900_I2CADDR_INC 0xf1290003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  126) /*P1_I2CRPT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  127) #define R0900_P1_I2CRPT 0xf12a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  128) #define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  129) #define F0900_P1_I2CT_ON 0xf12a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  130) #define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  131) #define F0900_P1_ENARPT_LEVEL 0xf12a0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  132) #define F0900_P1_SCLT_DELAY 0xf12a0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  133) #define F0900_P1_STOP_ENABLE 0xf12a0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  134) #define F0900_P1_STOP_SDAT2SDA 0xf12a0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  136) /*P2_I2CRPT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  137) #define R0900_P2_I2CRPT 0xf12b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  138) #define F0900_P2_I2CT_ON 0xf12b0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  139) #define F0900_P2_ENARPT_LEVEL 0xf12b0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  140) #define F0900_P2_SCLT_DELAY 0xf12b0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  141) #define F0900_P2_STOP_ENABLE 0xf12b0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  142) #define F0900_P2_STOP_SDAT2SDA 0xf12b0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  144) /*IOPVALUE6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  145) #define R0900_IOPVALUE6 0xf138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  146) #define F0900_VSCL 0xf1380004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  147) #define F0900_VSDA 0xf1380002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  148) #define F0900_VDATA3_0 0xf1380001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  150) /*IOPVALUE5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  151) #define R0900_IOPVALUE5 0xf139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  152) #define F0900_VDATA3_1 0xf1390080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  153) #define F0900_VDATA3_2 0xf1390040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  154) #define F0900_VDATA3_3 0xf1390020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  155) #define F0900_VDATA3_4 0xf1390010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  156) #define F0900_VDATA3_5 0xf1390008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  157) #define F0900_VDATA3_6 0xf1390004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  158) #define F0900_VDATA3_7 0xf1390002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  159) #define F0900_VCLKOUT3 0xf1390001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  161) /*IOPVALUE4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  162) #define R0900_IOPVALUE4 0xf13a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  163) #define F0900_VSTROUT3 0xf13a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  164) #define F0900_VDPN3 0xf13a0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  165) #define F0900_VERROR3 0xf13a0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  166) #define F0900_VDATA2_7 0xf13a0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  167) #define F0900_VCLKOUT2 0xf13a0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  168) #define F0900_VSTROUT2 0xf13a0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  169) #define F0900_VDPN2 0xf13a0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  170) #define F0900_VERROR2 0xf13a0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  172) /*IOPVALUE3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  173) #define R0900_IOPVALUE3 0xf13b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  174) #define F0900_VDATA1_7 0xf13b0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  175) #define F0900_VCLKOUT1 0xf13b0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  176) #define F0900_VSTROUT1 0xf13b0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  177) #define F0900_VDPN1 0xf13b0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  178) #define F0900_VERROR1 0xf13b0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  179) #define F0900_VCLKOUT27 0xf13b0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  180) #define F0900_VDISEQCOUT2 0xf13b0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  181) #define F0900_VSCLT2 0xf13b0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  183) /*IOPVALUE2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  184) #define R0900_IOPVALUE2 0xf13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  185) #define F0900_VSDAT2 0xf13c0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  186) #define F0900_VAGCRF2 0xf13c0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  187) #define F0900_VDISEQCOUT1 0xf13c0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  188) #define F0900_VSCLT1 0xf13c0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  189) #define F0900_VSDAT1 0xf13c0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  190) #define F0900_VAGCRF1 0xf13c0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  191) #define F0900_VDIRCLK 0xf13c0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  192) #define F0900_VSTDBY 0xf13c0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  194) /*IOPVALUE1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  195) #define R0900_IOPVALUE1 0xf13d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  196) #define F0900_VCS1 0xf13d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  197) #define F0900_VCS0 0xf13d0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  198) #define F0900_VGPIO13 0xf13d0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  199) #define F0900_VGPIO12 0xf13d0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  200) #define F0900_VGPIO11 0xf13d0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  201) #define F0900_VGPIO10 0xf13d0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  202) #define F0900_VGPIO9 0xf13d0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  203) #define F0900_VGPIO8 0xf13d0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  205) /*IOPVALUE0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  206) #define R0900_IOPVALUE0 0xf13e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  207) #define F0900_VGPIO7 0xf13e0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  208) #define F0900_VGPIO6 0xf13e0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  209) #define F0900_VGPIO5 0xf13e0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  210) #define F0900_VGPIO4 0xf13e0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  211) #define F0900_VGPIO3 0xf13e0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  212) #define F0900_VGPIO2 0xf13e0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  213) #define F0900_VGPIO1 0xf13e0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  214) #define F0900_VCLKI2 0xf13e0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  216) /*CLKI2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  217) #define R0900_CLKI2CFG 0xf140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  218) #define F0900_CLKI2_OPD 0xf1400080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  219) #define F0900_CLKI2_CONFIG 0xf140007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  220) #define F0900_CLKI2_XOR 0xf1400001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  222) /*GPIO1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  223) #define R0900_GPIO1CFG 0xf141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  224) #define F0900_GPIO1_OPD 0xf1410080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  225) #define F0900_GPIO1_CONFIG 0xf141007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  226) #define F0900_GPIO1_XOR 0xf1410001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  228) /*GPIO2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  229) #define R0900_GPIO2CFG 0xf142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  230) #define F0900_GPIO2_OPD 0xf1420080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  231) #define F0900_GPIO2_CONFIG 0xf142007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  232) #define F0900_GPIO2_XOR 0xf1420001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  234) /*GPIO3CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  235) #define R0900_GPIO3CFG 0xf143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  236) #define F0900_GPIO3_OPD 0xf1430080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  237) #define F0900_GPIO3_CONFIG 0xf143007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  238) #define F0900_GPIO3_XOR 0xf1430001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  240) /*GPIO4CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  241) #define R0900_GPIO4CFG 0xf144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  242) #define F0900_GPIO4_OPD 0xf1440080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  243) #define F0900_GPIO4_CONFIG 0xf144007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  244) #define F0900_GPIO4_XOR 0xf1440001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  246) /*GPIO5CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  247) #define R0900_GPIO5CFG 0xf145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  248) #define F0900_GPIO5_OPD 0xf1450080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  249) #define F0900_GPIO5_CONFIG 0xf145007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  250) #define F0900_GPIO5_XOR 0xf1450001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  252) /*GPIO6CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  253) #define R0900_GPIO6CFG 0xf146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  254) #define F0900_GPIO6_OPD 0xf1460080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  255) #define F0900_GPIO6_CONFIG 0xf146007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  256) #define F0900_GPIO6_XOR 0xf1460001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  258) /*GPIO7CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  259) #define R0900_GPIO7CFG 0xf147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  260) #define F0900_GPIO7_OPD 0xf1470080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  261) #define F0900_GPIO7_CONFIG 0xf147007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  262) #define F0900_GPIO7_XOR 0xf1470001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  264) /*GPIO8CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  265) #define R0900_GPIO8CFG 0xf148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  266) #define F0900_GPIO8_OPD 0xf1480080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  267) #define F0900_GPIO8_CONFIG 0xf148007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  268) #define F0900_GPIO8_XOR 0xf1480001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  270) /*GPIO9CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  271) #define R0900_GPIO9CFG 0xf149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  272) #define F0900_GPIO9_OPD 0xf1490080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  273) #define F0900_GPIO9_CONFIG 0xf149007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  274) #define F0900_GPIO9_XOR 0xf1490001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  276) /*GPIO10CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  277) #define R0900_GPIO10CFG 0xf14a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  278) #define F0900_GPIO10_OPD 0xf14a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  279) #define F0900_GPIO10_CONFIG 0xf14a007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  280) #define F0900_GPIO10_XOR 0xf14a0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  282) /*GPIO11CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  283) #define R0900_GPIO11CFG 0xf14b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  284) #define F0900_GPIO11_OPD 0xf14b0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  285) #define F0900_GPIO11_CONFIG 0xf14b007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  286) #define F0900_GPIO11_XOR 0xf14b0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  288) /*GPIO12CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  289) #define R0900_GPIO12CFG 0xf14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  290) #define F0900_GPIO12_OPD 0xf14c0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  291) #define F0900_GPIO12_CONFIG 0xf14c007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  292) #define F0900_GPIO12_XOR 0xf14c0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  294) /*GPIO13CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  295) #define R0900_GPIO13CFG 0xf14d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  296) #define F0900_GPIO13_OPD 0xf14d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  297) #define F0900_GPIO13_CONFIG 0xf14d007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  298) #define F0900_GPIO13_XOR 0xf14d0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  300) /*CS0CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  301) #define R0900_CS0CFG 0xf14e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  302) #define F0900_CS0_OPD 0xf14e0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  303) #define F0900_CS0_CONFIG 0xf14e007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  304) #define F0900_CS0_XOR 0xf14e0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  306) /*CS1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  307) #define R0900_CS1CFG 0xf14f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  308) #define F0900_CS1_OPD 0xf14f0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  309) #define F0900_CS1_CONFIG 0xf14f007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  310) #define F0900_CS1_XOR 0xf14f0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  312) /*STDBYCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  313) #define R0900_STDBYCFG 0xf150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  314) #define F0900_STDBY_OPD 0xf1500080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  315) #define F0900_STDBY_CONFIG 0xf150007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  316) #define F0900_STBDY_XOR 0xf1500001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  318) /*DIRCLKCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  319) #define R0900_DIRCLKCFG 0xf151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  320) #define F0900_DIRCLK_OPD 0xf1510080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  321) #define F0900_DIRCLK_CONFIG 0xf151007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  322) #define F0900_DIRCLK_XOR 0xf1510001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  324) /*AGCRF1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  325) #define R0900_AGCRF1CFG 0xf152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  326) #define F0900_AGCRF1_OPD 0xf1520080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  327) #define F0900_AGCRF1_CONFIG 0xf152007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  328) #define F0900_AGCRF1_XOR 0xf1520001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  330) /*SDAT1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  331) #define R0900_SDAT1CFG 0xf153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  332) #define F0900_SDAT1_OPD 0xf1530080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  333) #define F0900_SDAT1_CONFIG 0xf153007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  334) #define F0900_SDAT1_XOR 0xf1530001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  336) /*SCLT1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  337) #define R0900_SCLT1CFG 0xf154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  338) #define F0900_SCLT1_OPD 0xf1540080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  339) #define F0900_SCLT1_CONFIG 0xf154007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  340) #define F0900_SCLT1_XOR 0xf1540001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  342) /*DISEQCO1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  343) #define R0900_DISEQCO1CFG 0xf155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  344) #define F0900_DISEQCO1_OPD 0xf1550080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  345) #define F0900_DISEQCO1_CONFIG 0xf155007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  346) #define F0900_DISEQC1_XOR 0xf1550001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  348) /*AGCRF2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  349) #define R0900_AGCRF2CFG 0xf156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  350) #define F0900_AGCRF2_OPD 0xf1560080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  351) #define F0900_AGCRF2_CONFIG 0xf156007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  352) #define F0900_AGCRF2_XOR 0xf1560001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  354) /*SDAT2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  355) #define R0900_SDAT2CFG 0xf157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  356) #define F0900_SDAT2_OPD 0xf1570080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  357) #define F0900_SDAT2_CONFIG 0xf157007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  358) #define F0900_SDAT2_XOR 0xf1570001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  360) /*SCLT2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  361) #define R0900_SCLT2CFG 0xf158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  362) #define F0900_SCLT2_OPD 0xf1580080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  363) #define F0900_SCLT2_CONFIG 0xf158007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  364) #define F0900_SCLT2_XOR 0xf1580001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  366) /*DISEQCO2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  367) #define R0900_DISEQCO2CFG 0xf159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  368) #define F0900_DISEQCO2_OPD 0xf1590080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  369) #define F0900_DISEQCO2_CONFIG 0xf159007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  370) #define F0900_DISEQC2_XOR 0xf1590001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  372) /*CLKOUT27CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  373) #define R0900_CLKOUT27CFG 0xf15a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  374) #define F0900_CLKOUT27_OPD 0xf15a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  375) #define F0900_CLKOUT27_CONFIG 0xf15a007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  376) #define F0900_CLKOUT27_XOR 0xf15a0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  378) /*ERROR1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  379) #define R0900_ERROR1CFG 0xf15b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  380) #define F0900_ERROR1_OPD 0xf15b0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  381) #define F0900_ERROR1_CONFIG 0xf15b007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  382) #define F0900_ERROR1_XOR 0xf15b0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  384) /*DPN1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  385) #define R0900_DPN1CFG 0xf15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  386) #define F0900_DPN1_OPD 0xf15c0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  387) #define F0900_DPN1_CONFIG 0xf15c007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  388) #define F0900_DPN1_XOR 0xf15c0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  390) /*STROUT1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  391) #define R0900_STROUT1CFG 0xf15d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  392) #define F0900_STROUT1_OPD 0xf15d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  393) #define F0900_STROUT1_CONFIG 0xf15d007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  394) #define F0900_STROUT1_XOR 0xf15d0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  396) /*CLKOUT1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  397) #define R0900_CLKOUT1CFG 0xf15e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  398) #define F0900_CLKOUT1_OPD 0xf15e0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  399) #define F0900_CLKOUT1_CONFIG 0xf15e007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  400) #define F0900_CLKOUT1_XOR 0xf15e0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  402) /*DATA71CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  403) #define R0900_DATA71CFG 0xf15f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  404) #define F0900_DATA71_OPD 0xf15f0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  405) #define F0900_DATA71_CONFIG 0xf15f007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  406) #define F0900_DATA71_XOR 0xf15f0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  408) /*ERROR2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  409) #define R0900_ERROR2CFG 0xf160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  410) #define F0900_ERROR2_OPD 0xf1600080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  411) #define F0900_ERROR2_CONFIG 0xf160007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  412) #define F0900_ERROR2_XOR 0xf1600001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  414) /*DPN2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  415) #define R0900_DPN2CFG 0xf161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  416) #define F0900_DPN2_OPD 0xf1610080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  417) #define F0900_DPN2_CONFIG 0xf161007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  418) #define F0900_DPN2_XOR 0xf1610001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  420) /*STROUT2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  421) #define R0900_STROUT2CFG 0xf162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  422) #define F0900_STROUT2_OPD 0xf1620080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  423) #define F0900_STROUT2_CONFIG 0xf162007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  424) #define F0900_STROUT2_XOR 0xf1620001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  426) /*CLKOUT2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  427) #define R0900_CLKOUT2CFG 0xf163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  428) #define F0900_CLKOUT2_OPD 0xf1630080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  429) #define F0900_CLKOUT2_CONFIG 0xf163007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  430) #define F0900_CLKOUT2_XOR 0xf1630001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  432) /*DATA72CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  433) #define R0900_DATA72CFG 0xf164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  434) #define F0900_DATA72_OPD 0xf1640080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  435) #define F0900_DATA72_CONFIG 0xf164007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  436) #define F0900_DATA72_XOR 0xf1640001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  438) /*ERROR3CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  439) #define R0900_ERROR3CFG 0xf165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  440) #define F0900_ERROR3_OPD 0xf1650080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  441) #define F0900_ERROR3_CONFIG 0xf165007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  442) #define F0900_ERROR3_XOR 0xf1650001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  444) /*DPN3CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  445) #define R0900_DPN3CFG 0xf166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  446) #define F0900_DPN3_OPD 0xf1660080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  447) #define F0900_DPN3_CONFIG 0xf166007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  448) #define F0900_DPN3_XOR 0xf1660001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  450) /*STROUT3CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  451) #define R0900_STROUT3CFG 0xf167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  452) #define F0900_STROUT3_OPD 0xf1670080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  453) #define F0900_STROUT3_CONFIG 0xf167007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  454) #define F0900_STROUT3_XOR 0xf1670001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  456) /*CLKOUT3CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  457) #define R0900_CLKOUT3CFG 0xf168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  458) #define F0900_CLKOUT3_OPD 0xf1680080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  459) #define F0900_CLKOUT3_CONFIG 0xf168007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  460) #define F0900_CLKOUT3_XOR 0xf1680001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  462) /*DATA73CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  463) #define R0900_DATA73CFG 0xf169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  464) #define F0900_DATA73_OPD 0xf1690080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  465) #define F0900_DATA73_CONFIG 0xf169007e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  466) #define F0900_DATA73_XOR 0xf1690001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  468) /*STRSTATUS1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  469) #define R0900_STRSTATUS1 0xf16a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  470) #define F0900_STRSTATUS_SEL2 0xf16a00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  471) #define F0900_STRSTATUS_SEL1 0xf16a000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  473) /*STRSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  474) #define R0900_STRSTATUS2 0xf16b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  475) #define F0900_STRSTATUS_SEL4 0xf16b00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  476) #define F0900_STRSTATUS_SEL3 0xf16b000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  478) /*STRSTATUS3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  479) #define R0900_STRSTATUS3 0xf16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  480) #define F0900_STRSTATUS_SEL6 0xf16c00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  481) #define F0900_STRSTATUS_SEL5 0xf16c000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  483) /*FSKTFC2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  484) #define R0900_FSKTFC2 0xf170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  485) #define F0900_FSKT_KMOD 0xf17000fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  486) #define F0900_FSKT_CAR2 0xf1700003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  488) /*FSKTFC1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  489) #define R0900_FSKTFC1 0xf171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  490) #define F0900_FSKT_CAR1 0xf17100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  492) /*FSKTFC0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  493) #define R0900_FSKTFC0 0xf172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  494) #define F0900_FSKT_CAR0 0xf17200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  496) /*FSKTDELTAF1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  497) #define R0900_FSKTDELTAF1 0xf173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  498) #define F0900_FSKT_DELTAF1 0xf173000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  500) /*FSKTDELTAF0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  501) #define R0900_FSKTDELTAF0 0xf174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  502) #define F0900_FSKT_DELTAF0 0xf17400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  504) /*FSKTCTRL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  505) #define R0900_FSKTCTRL 0xf175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  506) #define F0900_FSKT_EN_SGN 0xf1750040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  507) #define F0900_FSKT_MOD_SGN 0xf1750020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  508) #define F0900_FSKT_MOD_EN 0xf175001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  509) #define F0900_FSKT_DACMODE 0xf1750003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  511) /*FSKRFC2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  512) #define R0900_FSKRFC2 0xf176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  513) #define F0900_FSKR_DETSGN 0xf1760040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  514) #define F0900_FSKR_OUTSGN 0xf1760020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  515) #define F0900_FSKR_KAGC 0xf176001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  516) #define F0900_FSKR_CAR2 0xf1760003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  518) /*FSKRFC1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  519) #define R0900_FSKRFC1 0xf177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  520) #define F0900_FSKR_CAR1 0xf17700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  522) /*FSKRFC0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  523) #define R0900_FSKRFC0 0xf178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  524) #define F0900_FSKR_CAR0 0xf17800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  526) /*FSKRK1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  527) #define R0900_FSKRK1 0xf179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  528) #define F0900_FSKR_K1_EXP 0xf17900e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  529) #define F0900_FSKR_K1_MANT 0xf179001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  531) /*FSKRK2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  532) #define R0900_FSKRK2 0xf17a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  533) #define F0900_FSKR_K2_EXP 0xf17a00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  534) #define F0900_FSKR_K2_MANT 0xf17a001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  536) /*FSKRAGCR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  537) #define R0900_FSKRAGCR 0xf17b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  538) #define F0900_FSKR_OUTCTL 0xf17b00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  539) #define F0900_FSKR_AGC_REF 0xf17b003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  541) /*FSKRAGC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  542) #define R0900_FSKRAGC 0xf17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  543) #define F0900_FSKR_AGC_ACCU 0xf17c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  545) /*FSKRALPHA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  546) #define R0900_FSKRALPHA 0xf17d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  547) #define F0900_FSKR_ALPHA_EXP 0xf17d001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  548) #define F0900_FSKR_ALPHA_M 0xf17d0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  550) /*FSKRPLTH1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  551) #define R0900_FSKRPLTH1 0xf17e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  552) #define F0900_FSKR_BETA 0xf17e00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  553) #define F0900_FSKR_PLL_TRESH1 0xf17e000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  555) /*FSKRPLTH0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  556) #define R0900_FSKRPLTH0 0xf17f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  557) #define F0900_FSKR_PLL_TRESH0 0xf17f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  559) /*FSKRDF1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  560) #define R0900_FSKRDF1 0xf180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  561) #define F0900_FSKR_OUT 0xf1800080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  562) #define F0900_FSKR_DELTAF1 0xf180001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  564) /*FSKRDF0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  565) #define R0900_FSKRDF0 0xf181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  566) #define F0900_FSKR_DELTAF0 0xf18100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  568) /*FSKRSTEPP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  569) #define R0900_FSKRSTEPP 0xf182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  570) #define F0900_FSKR_STEP_PLUS 0xf18200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  572) /*FSKRSTEPM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  573) #define R0900_FSKRSTEPM 0xf183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  574) #define F0900_FSKR_STEP_MINUS 0xf18300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  576) /*FSKRDET1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  577) #define R0900_FSKRDET1 0xf184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  578) #define F0900_FSKR_DETECT 0xf1840080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  579) #define F0900_FSKR_CARDET_ACCU1 0xf184000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  581) /*FSKRDET0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  582) #define R0900_FSKRDET0 0xf185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  583) #define F0900_FSKR_CARDET_ACCU0 0xf18500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  584) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  585) /*FSKRDTH1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  586) #define R0900_FSKRDTH1 0xf186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  587) #define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  588) #define F0900_FSKR_CARDET_THRESH1 0xf186000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  590) /*FSKRDTH0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  591) #define R0900_FSKRDTH0 0xf187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  592) #define F0900_FSKR_CARDET_THRESH0 0xf18700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  594) /*FSKRLOSS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  595) #define R0900_FSKRLOSS 0xf188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  596) #define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  598) /*P2_DISTXCTL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  599) #define R0900_P2_DISTXCTL 0xf190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  600) #define F0900_P2_TIM_OFF 0xf1900080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  601) #define F0900_P2_DISEQC_RESET 0xf1900040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  602) #define F0900_P2_TIM_CMD 0xf1900030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  603) #define F0900_P2_DIS_PRECHARGE 0xf1900008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  604) #define F0900_P2_DISTX_MODE 0xf1900007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  606) /*P2_DISRXCTL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  607) #define R0900_P2_DISRXCTL 0xf191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  608) #define F0900_P2_RECEIVER_ON 0xf1910080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  609) #define F0900_P2_IGNO_SHORT22K 0xf1910040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  610) #define F0900_P2_ONECHIP_TRX 0xf1910020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  611) #define F0900_P2_EXT_ENVELOP 0xf1910010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  612) #define F0900_P2_PIN_SELECT0 0xf191000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  613) #define F0900_P2_IRQ_RXEND 0xf1910002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  614) #define F0900_P2_IRQ_4NBYTES 0xf1910001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  616) /*P2_DISRX_ST0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  617) #define R0900_P2_DISRX_ST0 0xf194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  618) #define F0900_P2_RX_END 0xf1940080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  619) #define F0900_P2_RX_ACTIVE 0xf1940040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  620) #define F0900_P2_SHORT_22KHZ 0xf1940020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  621) #define F0900_P2_CONT_TONE 0xf1940010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  622) #define F0900_P2_FIFO_4BREADY 0xf1940008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  623) #define F0900_P2_FIFO_EMPTY 0xf1940004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  624) #define F0900_P2_ABORT_DISRX 0xf1940001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  626) /*P2_DISRX_ST1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  627) #define R0900_P2_DISRX_ST1 0xf195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  628) #define F0900_P2_RX_FAIL 0xf1950080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  629) #define F0900_P2_FIFO_PARITYFAIL 0xf1950040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  630) #define F0900_P2_RX_NONBYTE 0xf1950020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  631) #define F0900_P2_FIFO_OVERFLOW 0xf1950010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  632) #define F0900_P2_FIFO_BYTENBR 0xf195000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  634) /*P2_DISRXDATA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  635) #define R0900_P2_DISRXDATA 0xf196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  636) #define F0900_P2_DISRX_DATA 0xf19600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  638) /*P2_DISTXDATA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  639) #define R0900_P2_DISTXDATA 0xf197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  640) #define F0900_P2_DISEQC_FIFO 0xf19700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  641) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  642) /*P2_DISTXSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  643) #define R0900_P2_DISTXSTATUS 0xf198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  644) #define F0900_P2_TX_FAIL 0xf1980080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  645) #define F0900_P2_FIFO_FULL 0xf1980040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  646) #define F0900_P2_TX_IDLE 0xf1980020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  647) #define F0900_P2_GAP_BURST 0xf1980010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  648) #define F0900_P2_TXFIFO_BYTES 0xf198000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  649) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  650) /*P2_F22TX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  651) #define R0900_P2_F22TX 0xf199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  652) #define F0900_P2_F22_REG 0xf19900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  654) /*P2_F22RX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  655) #define R0900_P2_F22RX 0xf19a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  656) #define F0900_P2_F22RX_REG 0xf19a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  657) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  658) /*P2_ACRPRESC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  659) #define R0900_P2_ACRPRESC 0xf19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  660) #define F0900_P2_ACR_PRESC 0xf19c0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  661) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  662) /*P2_ACRDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  663) #define R0900_P2_ACRDIV 0xf19d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  664) #define F0900_P2_ACR_DIV 0xf19d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  665) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  666) /*P1_DISTXCTL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  667) #define R0900_P1_DISTXCTL 0xf1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  668) #define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  669) #define F0900_P1_TIM_OFF 0xf1a00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  670) #define F0900_P1_DISEQC_RESET 0xf1a00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  671) #define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  672) #define F0900_P1_TIM_CMD 0xf1a00030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  673) #define F0900_P1_DIS_PRECHARGE 0xf1a00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  674) #define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  675) #define F0900_P1_DISTX_MODE 0xf1a00007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  676) #define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  678) /*P1_DISRXCTL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  679) #define R0900_P1_DISRXCTL 0xf1a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  680) #define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  681) #define F0900_P1_RECEIVER_ON 0xf1a10080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  682) #define F0900_P1_IGNO_SHORT22K 0xf1a10040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  683) #define F0900_P1_ONECHIP_TRX 0xf1a10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  684) #define F0900_P1_EXT_ENVELOP 0xf1a10010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  685) #define F0900_P1_PIN_SELECT0 0xf1a1000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  686) #define F0900_P1_IRQ_RXEND 0xf1a10002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  687) #define F0900_P1_IRQ_4NBYTES 0xf1a10001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  688) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  689) /*P1_DISRX_ST0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  690) #define R0900_P1_DISRX_ST0 0xf1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  691) #define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  692) #define F0900_P1_RX_END 0xf1a40080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  693) #define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  694) #define F0900_P1_RX_ACTIVE 0xf1a40040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  695) #define F0900_P1_SHORT_22KHZ 0xf1a40020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  696) #define F0900_P1_CONT_TONE 0xf1a40010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  697) #define F0900_P1_FIFO_4BREADY 0xf1a40008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  698) #define F0900_P1_FIFO_EMPTY 0xf1a40004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  699) #define F0900_P1_ABORT_DISRX 0xf1a40001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  700) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  701) /*P1_DISRX_ST1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  702) #define R0900_P1_DISRX_ST1 0xf1a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  703) #define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  704) #define F0900_P1_RX_FAIL 0xf1a50080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  705) #define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  706) #define F0900_P1_RX_NONBYTE 0xf1a50020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  707) #define F0900_P1_FIFO_OVERFLOW 0xf1a50010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  708) #define F0900_P1_FIFO_BYTENBR 0xf1a5000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  709) #define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  710) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  711) /*P1_DISRXDATA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  712) #define R0900_P1_DISRXDATA 0xf1a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  713) #define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  714) #define F0900_P1_DISRX_DATA 0xf1a600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  715) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  716) /*P1_DISTXDATA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  717) #define R0900_P1_DISTXDATA 0xf1a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  718) #define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  719) #define F0900_P1_DISEQC_FIFO 0xf1a700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  720) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  721) /*P1_DISTXSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  722) #define R0900_P1_DISTXSTATUS 0xf1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  723) #define F0900_P1_TX_FAIL 0xf1a80080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  724) #define F0900_P1_FIFO_FULL 0xf1a80040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  725) #define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  726) #define F0900_P1_TX_IDLE 0xf1a80020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  727) #define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  728) #define F0900_P1_GAP_BURST 0xf1a80010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  729) #define F0900_P1_TXFIFO_BYTES 0xf1a8000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  730) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  731) /*P1_F22TX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  732) #define R0900_P1_F22TX 0xf1a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  733) #define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  734) #define F0900_P1_F22_REG 0xf1a900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  735) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  736) /*P1_F22RX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  737) #define R0900_P1_F22RX 0xf1aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  738) #define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  739) #define F0900_P1_F22RX_REG 0xf1aa00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  740) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  741) /*P1_ACRPRESC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  742) #define R0900_P1_ACRPRESC 0xf1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  743) #define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  744) #define F0900_P1_ACR_PRESC 0xf1ac0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  745) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  746) /*P1_ACRDIV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  747) #define R0900_P1_ACRDIV 0xf1ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  748) #define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  749) #define F0900_P1_ACR_DIV 0xf1ad00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  750) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  751) /*NCOARSE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  752) #define R0900_NCOARSE 0xf1b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  753) #define F0900_M_DIV 0xf1b300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  754) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  755) /*SYNTCTRL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  756) #define R0900_SYNTCTRL 0xf1b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  757) #define F0900_STANDBY 0xf1b60080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  758) #define F0900_BYPASSPLLCORE 0xf1b60040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  759) #define F0900_SELX1RATIO 0xf1b60020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  760) #define F0900_STOP_PLL 0xf1b60008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  761) #define F0900_BYPASSPLLFSK 0xf1b60004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  762) #define F0900_SELOSCI 0xf1b60002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  763) #define F0900_BYPASSPLLADC 0xf1b60001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  764) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  765) /*FILTCTRL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  766) #define R0900_FILTCTRL 0xf1b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  767) #define F0900_INV_CLK135 0xf1b70080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  768) #define F0900_SEL_FSKCKDIV 0xf1b70004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  769) #define F0900_INV_CLKFSK 0xf1b70002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  770) #define F0900_BYPASS_APPLI 0xf1b70001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  772) /*PLLSTAT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  773) #define R0900_PLLSTAT 0xf1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  774) #define F0900_PLLLOCK 0xf1b80001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  775) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  776) /*STOPCLK1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  777) #define R0900_STOPCLK1 0xf1c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  778) #define F0900_STOP_CLKPKDT2 0xf1c20040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  779) #define F0900_STOP_CLKPKDT1 0xf1c20020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  780) #define F0900_STOP_CLKFEC 0xf1c20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  781) #define F0900_STOP_CLKADCI2 0xf1c20008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  782) #define F0900_INV_CLKADCI2 0xf1c20004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  783) #define F0900_STOP_CLKADCI1 0xf1c20002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  784) #define F0900_INV_CLKADCI1 0xf1c20001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  785) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  786) /*STOPCLK2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  787) #define R0900_STOPCLK2 0xf1c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  788) #define F0900_STOP_CLKSAMP2 0xf1c30010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  789) #define F0900_STOP_CLKSAMP1 0xf1c30008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  790) #define F0900_STOP_CLKVIT2 0xf1c30004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  791) #define F0900_STOP_CLKVIT1 0xf1c30002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  792) #define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  793) #define F0900_STOP_CLKTS 0xf1c30001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  794) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  795) /*TSTTNR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  796) #define R0900_TSTTNR0 0xf1df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  797) #define F0900_SEL_FSK 0xf1df0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  798) #define F0900_FSK_PON 0xf1df0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  799) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  800) /*TSTTNR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  801) #define R0900_TSTTNR1 0xf1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  802) #define F0900_ADC1_PON 0xf1e00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  803) #define F0900_ADC1_INMODE 0xf1e00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  804) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  805) /*TSTTNR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  806) #define R0900_TSTTNR2 0xf1e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  807) #define F0900_DISEQC1_PON 0xf1e10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  808) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  809) /*TSTTNR3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  810) #define R0900_TSTTNR3 0xf1e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  811) #define F0900_ADC2_PON 0xf1e20002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  812) #define F0900_ADC2_INMODE 0xf1e20001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  814) /*TSTTNR4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  815) #define R0900_TSTTNR4 0xf1e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  816) #define F0900_DISEQC2_PON 0xf1e30020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  817) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  818) /*P2_IQCONST*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  819) #define R0900_P2_IQCONST 0xf200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  820) #define F0900_P2_CONSTEL_SELECT 0xf2000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  821) #define F0900_P2_IQSYMB_SEL 0xf200001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  822) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  823) /*P2_NOSCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  824) #define R0900_P2_NOSCFG 0xf201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  825) #define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  826) #define F0900_P2_NOSPLH_BETA 0xf2010018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  827) #define F0900_P2_NOSDATA_BETA 0xf2010007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  828) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  829) /*P2_ISYMB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  830) #define R0900_P2_ISYMB 0xf202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  831) #define F0900_P2_I_SYMBOL 0xf20201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  832) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  833) /*P2_QSYMB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  834) #define R0900_P2_QSYMB 0xf203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  835) #define F0900_P2_Q_SYMBOL 0xf20301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  836) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  837) /*P2_AGC1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  838) #define R0900_P2_AGC1CFG 0xf204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  839) #define F0900_P2_DC_FROZEN 0xf2040080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  840) #define F0900_P2_DC_CORRECT 0xf2040040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  841) #define F0900_P2_AMM_FROZEN 0xf2040020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  842) #define F0900_P2_AMM_CORRECT 0xf2040010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  843) #define F0900_P2_QUAD_FROZEN 0xf2040008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  844) #define F0900_P2_QUAD_CORRECT 0xf2040004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  845) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  846) /*P2_AGC1CN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  847) #define R0900_P2_AGC1CN 0xf206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  848) #define F0900_P2_AGC1_LOCKED 0xf2060080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  849) #define F0900_P2_AGC1_MINPOWER 0xf2060010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  850) #define F0900_P2_AGCOUT_FAST 0xf2060008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  851) #define F0900_P2_AGCIQ_BETA 0xf2060007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  852) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  853) /*P2_AGC1REF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  854) #define R0900_P2_AGC1REF 0xf207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  855) #define F0900_P2_AGCIQ_REF 0xf20700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  856) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  857) /*P2_IDCCOMP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  858) #define R0900_P2_IDCCOMP 0xf208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  859) #define F0900_P2_IAVERAGE_ADJ 0xf20801ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  860) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  861) /*P2_QDCCOMP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  862) #define R0900_P2_QDCCOMP 0xf209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  863) #define F0900_P2_QAVERAGE_ADJ 0xf20901ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  864) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  865) /*P2_POWERI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  866) #define R0900_P2_POWERI 0xf20a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  867) #define F0900_P2_POWER_I 0xf20a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  868) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  869) /*P2_POWERQ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  870) #define R0900_P2_POWERQ 0xf20b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  871) #define F0900_P2_POWER_Q 0xf20b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  872) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  873) /*P2_AGC1AMM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  874) #define R0900_P2_AGC1AMM 0xf20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  875) #define F0900_P2_AMM_VALUE 0xf20c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  876) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  877) /*P2_AGC1QUAD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  878) #define R0900_P2_AGC1QUAD 0xf20d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  879) #define F0900_P2_QUAD_VALUE 0xf20d01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  880) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  881) /*P2_AGCIQIN1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  882) #define R0900_P2_AGCIQIN1 0xf20e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  883) #define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  884) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  885) /*P2_AGCIQIN0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  886) #define R0900_P2_AGCIQIN0 0xf20f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  887) #define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  888) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  889) /*P2_DEMOD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  890) #define R0900_P2_DEMOD 0xf210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  891) #define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  892) #define F0900_P2_SPECINV_CONTROL 0xf2100030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  893) #define F0900_P2_FORCE_ENASAMP 0xf2100008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  894) #define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  895) #define F0900_P2_ROLLOFF_CONTROL 0xf2100003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  896) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  897) /*P2_DMDMODCOD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  898) #define R0900_P2_DMDMODCOD 0xf211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  899) #define F0900_P2_MANUAL_MODCOD 0xf2110080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  900) #define F0900_P2_DEMOD_MODCOD 0xf211007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  901) #define F0900_P2_DEMOD_TYPE 0xf2110003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  902) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  903) /*P2_DSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  904) #define R0900_P2_DSTATUS 0xf212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  905) #define F0900_P2_CAR_LOCK 0xf2120080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  906) #define F0900_P2_TMGLOCK_QUALITY 0xf2120060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  907) #define F0900_P2_LOCK_DEFINITIF 0xf2120008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  908) #define F0900_P2_OVADC_DETECT 0xf2120001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  909) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  910) /*P2_DSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  911) #define R0900_P2_DSTATUS2 0xf213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  912) #define F0900_P2_DEMOD_DELOCK 0xf2130080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  913) #define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  914) #define F0900_P2_AGC2_OVERFLOW 0xf2130004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  915) #define F0900_P2_CFR_OVERFLOW 0xf2130002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  916) #define F0900_P2_GAMMA_OVERUNDER 0xf2130001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  917) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  918) /*P2_DMDCFGMD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  919) #define R0900_P2_DMDCFGMD 0xf214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  920) #define F0900_P2_DVBS2_ENABLE 0xf2140080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  921) #define F0900_P2_DVBS1_ENABLE 0xf2140040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  922) #define F0900_P2_SCAN_ENABLE 0xf2140010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  923) #define F0900_P2_CFR_AUTOSCAN 0xf2140008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  924) #define F0900_P2_TUN_RNG 0xf2140003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  925) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  926) /*P2_DMDCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  927) #define R0900_P2_DMDCFG2 0xf215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  928) #define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  929) #define F0900_P2_INFINITE_RELOCK 0xf2150010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  930) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  931) /*P2_DMDISTATE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  932) #define R0900_P2_DMDISTATE 0xf216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  933) #define F0900_P2_I2C_DEMOD_MODE 0xf216001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  934) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  935) /*P2_DMDT0M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  936) #define R0900_P2_DMDT0M 0xf217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  937) #define F0900_P2_DMDT0_MIN 0xf21700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  938) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  939) /*P2_DMDSTATE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  940) #define R0900_P2_DMDSTATE 0xf21b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  941) #define F0900_P2_HEADER_MODE 0xf21b0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  942) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  943) /*P2_DMDFLYW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  944) #define R0900_P2_DMDFLYW 0xf21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  945) #define F0900_P2_I2C_IRQVAL 0xf21c00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  946) #define F0900_P2_FLYWHEEL_CPT 0xf21c000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  947) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  948) /*P2_DSTATUS3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  949) #define R0900_P2_DSTATUS3 0xf21d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  950) #define F0900_P2_DEMOD_CFGMODE 0xf21d0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  951) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  952) /*P2_DMDCFG3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  953) #define R0900_P2_DMDCFG3 0xf21e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  954) #define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  955) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  956) /*P2_DMDCFG4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  957) #define R0900_P2_DMDCFG4 0xf21f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  958) #define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  959) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  960) /*P2_CORRELMANT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  961) #define R0900_P2_CORRELMANT 0xf220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  962) #define F0900_P2_CORREL_MANT 0xf22000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  963) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  964) /*P2_CORRELABS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  965) #define R0900_P2_CORRELABS 0xf221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  966) #define F0900_P2_CORREL_ABS 0xf22100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  967) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  968) /*P2_CORRELEXP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  969) #define R0900_P2_CORRELEXP 0xf222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  970) #define F0900_P2_CORREL_ABSEXP 0xf22200f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  971) #define F0900_P2_CORREL_EXP 0xf222000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  972) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  973) /*P2_PLHMODCOD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  974) #define R0900_P2_PLHMODCOD 0xf224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  975) #define F0900_P2_SPECINV_DEMOD 0xf2240080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  976) #define F0900_P2_PLH_MODCOD 0xf224007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  977) #define F0900_P2_PLH_TYPE 0xf2240003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  978) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  979) /*P2_DMDREG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  980) #define R0900_P2_DMDREG 0xf225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  981) #define F0900_P2_DECIM_PLFRAMES 0xf2250001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  982) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  983) /*P2_AGC2O*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  984) #define R0900_P2_AGC2O 0xf22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  985) #define F0900_P2_AGC2_COEF 0xf22c0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  986) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  987) /*P2_AGC2REF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  988) #define R0900_P2_AGC2REF 0xf22d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  989) #define F0900_P2_AGC2_REF 0xf22d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  990) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  991) /*P2_AGC1ADJ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  992) #define R0900_P2_AGC1ADJ 0xf22e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  993) #define F0900_P2_AGC1_ADJUSTED 0xf22e007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  994) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  995) /*P2_AGC2I1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  996) #define R0900_P2_AGC2I1 0xf236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  997) #define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  998) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  999) /*P2_AGC2I0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define R0900_P2_AGC2I0 0xf237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*P2_CARCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define R0900_P2_CARCFG 0xf238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define F0900_P2_CFRUPLOW_AUTO 0xf2380080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define F0900_P2_CFRUPLOW_TEST 0xf2380040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define F0900_P2_ROTAON 0xf2380004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define F0900_P2_PH_DET_ALGO 0xf2380003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /*P2_ACLC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define R0900_P2_ACLC 0xf239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define F0900_P2_CAR_ALPHA_MANT 0xf2390030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define F0900_P2_CAR_ALPHA_EXP 0xf239000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*P2_BCLC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define R0900_P2_BCLC 0xf23a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define F0900_P2_CAR_BETA_MANT 0xf23a0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define F0900_P2_CAR_BETA_EXP 0xf23a000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /*P2_CARFREQ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define R0900_P2_CARFREQ 0xf23d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define F0900_P2_KC_COARSE_EXP 0xf23d00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define F0900_P2_BETA_FREQ 0xf23d000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /*P2_CARHDR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define R0900_P2_CARHDR 0xf23e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define F0900_P2_K_FREQ_HDR 0xf23e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*P2_LDT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define R0900_P2_LDT 0xf23f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define F0900_P2_CARLOCK_THRES 0xf23f01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*P2_LDT2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define R0900_P2_LDT2 0xf240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define F0900_P2_CARLOCK_THRES2 0xf24001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /*P2_CFRICFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define R0900_P2_CFRICFG 0xf241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define F0900_P2_NEG_CFRSTEP 0xf2410001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /*P2_CFRUP1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define R0900_P2_CFRUP1 0xf242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define F0900_P2_CFR_UP1 0xf24201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /*P2_CFRUP0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define R0900_P2_CFRUP0 0xf243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define F0900_P2_CFR_UP0 0xf24300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /*P2_CFRLOW1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define R0900_P2_CFRLOW1 0xf246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define F0900_P2_CFR_LOW1 0xf24601ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*P2_CFRLOW0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define R0900_P2_CFRLOW0 0xf247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define F0900_P2_CFR_LOW0 0xf24700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*P2_CFRINIT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define R0900_P2_CFRINIT1 0xf248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define F0900_P2_CFR_INIT1 0xf24801ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*P2_CFRINIT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define R0900_P2_CFRINIT0 0xf249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define F0900_P2_CFR_INIT0 0xf24900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /*P2_CFRINC1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define R0900_P2_CFRINC1 0xf24a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define F0900_P2_MANUAL_CFRINC 0xf24a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define F0900_P2_CFR_INC1 0xf24a003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*P2_CFRINC0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define R0900_P2_CFRINC0 0xf24b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define F0900_P2_CFR_INC0 0xf24b00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*P2_CFR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define R0900_P2_CFR2 0xf24c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define F0900_P2_CAR_FREQ2 0xf24c01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*P2_CFR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define R0900_P2_CFR1 0xf24d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define F0900_P2_CAR_FREQ1 0xf24d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*P2_CFR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define R0900_P2_CFR0 0xf24e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define F0900_P2_CAR_FREQ0 0xf24e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /*P2_LDI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define R0900_P2_LDI 0xf24f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*P2_TMGCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define R0900_P2_TMGCFG 0xf250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define F0900_P2_TMGLOCK_BETA 0xf25000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define F0900_P2_DO_TIMING_CORR 0xf2500010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define F0900_P2_TMG_MINFREQ 0xf2500003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*P2_RTC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define R0900_P2_RTC 0xf251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define F0900_P2_TMGALPHA_EXP 0xf25100f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define F0900_P2_TMGBETA_EXP 0xf251000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*P2_RTCS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define R0900_P2_RTCS2 0xf252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define F0900_P2_TMGBETAS2_EXP 0xf252000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /*P2_TMGTHRISE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define R0900_P2_TMGTHRISE 0xf253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define F0900_P2_TMGLOCK_THRISE 0xf25300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /*P2_TMGTHFALL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define R0900_P2_TMGTHFALL 0xf254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define F0900_P2_TMGLOCK_THFALL 0xf25400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*P2_SFRUPRATIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define R0900_P2_SFRUPRATIO 0xf255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define F0900_P2_SFR_UPRATIO 0xf25500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /*P2_SFRLOWRATIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define R0900_P2_SFRLOWRATIO 0xf256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define F0900_P2_SFR_LOWRATIO 0xf25600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /*P2_KREFTMG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define R0900_P2_KREFTMG 0xf258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define F0900_P2_KREF_TMG 0xf25800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /*P2_SFRSTEP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define R0900_P2_SFRSTEP 0xf259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define F0900_P2_SFR_SCANSTEP 0xf25900f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define F0900_P2_SFR_CENTERSTEP 0xf259000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*P2_TMGCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define R0900_P2_TMGCFG2 0xf25a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define F0900_P2_SFRRATIO_FINE 0xf25a0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /*P2_KREFTMG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define R0900_P2_KREFTMG2 0xf25b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define F0900_P2_KREF_TMG2 0xf25b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /*P2_SFRINIT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define R0900_P2_SFRINIT1 0xf25e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define F0900_P2_SFR_INIT1 0xf25e007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /*P2_SFRINIT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define R0900_P2_SFRINIT0 0xf25f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define F0900_P2_SFR_INIT0 0xf25f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*P2_SFRUP1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define R0900_P2_SFRUP1 0xf260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define F0900_P2_AUTO_GUP 0xf2600080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define F0900_P2_SYMB_FREQ_UP1 0xf260007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*P2_SFRUP0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define R0900_P2_SFRUP0 0xf261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*P2_SFRLOW1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define R0900_P2_SFRLOW1 0xf262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define F0900_P2_AUTO_GLOW 0xf2620080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*P2_SFRLOW0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define R0900_P2_SFRLOW0 0xf263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*P2_SFR3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define R0900_P2_SFR3 0xf264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define F0900_P2_SYMB_FREQ3 0xf26400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /*P2_SFR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define R0900_P2_SFR2 0xf265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define F0900_P2_SYMB_FREQ2 0xf26500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*P2_SFR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define R0900_P2_SFR1 0xf266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define F0900_P2_SYMB_FREQ1 0xf26600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*P2_SFR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define R0900_P2_SFR0 0xf267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define F0900_P2_SYMB_FREQ0 0xf26700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*P2_TMGREG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define R0900_P2_TMGREG2 0xf268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define F0900_P2_TMGREG2 0xf26800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /*P2_TMGREG1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define R0900_P2_TMGREG1 0xf269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define F0900_P2_TMGREG1 0xf26900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*P2_TMGREG0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define R0900_P2_TMGREG0 0xf26a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define F0900_P2_TMGREG0 0xf26a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /*P2_TMGLOCK1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define R0900_P2_TMGLOCK1 0xf26b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /*P2_TMGLOCK0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define R0900_P2_TMGLOCK0 0xf26c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*P2_TMGOBS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define R0900_P2_TMGOBS 0xf26d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*P2_EQUALCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define R0900_P2_EQUALCFG 0xf26f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define F0900_P2_EQUAL_ON 0xf26f0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define F0900_P2_MU_EQUALDFE 0xf26f0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /*P2_EQUAI1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define R0900_P2_EQUAI1 0xf270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define F0900_P2_EQUA_ACCI1 0xf27001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*P2_EQUAQ1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define R0900_P2_EQUAQ1 0xf271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define F0900_P2_EQUA_ACCQ1 0xf27101ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /*P2_EQUAI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define R0900_P2_EQUAI2 0xf272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define F0900_P2_EQUA_ACCI2 0xf27201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*P2_EQUAQ2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define R0900_P2_EQUAQ2 0xf273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define F0900_P2_EQUA_ACCQ2 0xf27301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*P2_EQUAI3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define R0900_P2_EQUAI3 0xf274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define F0900_P2_EQUA_ACCI3 0xf27401ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*P2_EQUAQ3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define R0900_P2_EQUAQ3 0xf275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define F0900_P2_EQUA_ACCQ3 0xf27501ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*P2_EQUAI4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define R0900_P2_EQUAI4 0xf276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define F0900_P2_EQUA_ACCI4 0xf27601ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*P2_EQUAQ4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define R0900_P2_EQUAQ4 0xf277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define F0900_P2_EQUA_ACCQ4 0xf27701ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*P2_EQUAI5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define R0900_P2_EQUAI5 0xf278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define F0900_P2_EQUA_ACCI5 0xf27801ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*P2_EQUAQ5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define R0900_P2_EQUAQ5 0xf279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define F0900_P2_EQUA_ACCQ5 0xf27901ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /*P2_EQUAI6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define R0900_P2_EQUAI6 0xf27a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define F0900_P2_EQUA_ACCI6 0xf27a01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /*P2_EQUAQ6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define R0900_P2_EQUAQ6 0xf27b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define F0900_P2_EQUA_ACCQ6 0xf27b01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /*P2_EQUAI7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define R0900_P2_EQUAI7 0xf27c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define F0900_P2_EQUA_ACCI7 0xf27c01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*P2_EQUAQ7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define R0900_P2_EQUAQ7 0xf27d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define F0900_P2_EQUA_ACCQ7 0xf27d01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*P2_EQUAI8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define R0900_P2_EQUAI8 0xf27e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define F0900_P2_EQUA_ACCI8 0xf27e01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*P2_EQUAQ8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define R0900_P2_EQUAQ8 0xf27f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define F0900_P2_EQUA_ACCQ8 0xf27f01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*P2_NNOSDATAT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define R0900_P2_NNOSDATAT1 0xf280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*P2_NNOSDATAT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define R0900_P2_NNOSDATAT0 0xf281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /*P2_NNOSDATA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define R0900_P2_NNOSDATA1 0xf282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define F0900_P2_NOSDATA_NORMED1 0xf28200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /*P2_NNOSDATA0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define R0900_P2_NNOSDATA0 0xf283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define F0900_P2_NOSDATA_NORMED0 0xf28300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*P2_NNOSPLHT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define R0900_P2_NNOSPLHT1 0xf284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /*P2_NNOSPLHT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define R0900_P2_NNOSPLHT0 0xf285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /*P2_NNOSPLH1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define R0900_P2_NNOSPLH1 0xf286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define F0900_P2_NOSPLH_NORMED1 0xf28600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*P2_NNOSPLH0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define R0900_P2_NNOSPLH0 0xf287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define F0900_P2_NOSPLH_NORMED0 0xf28700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*P2_NOSDATAT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define R0900_P2_NOSDATAT1 0xf288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*P2_NOSDATAT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define R0900_P2_NOSDATAT0 0xf289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /*P2_NOSDATA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define R0900_P2_NOSDATA1 0xf28a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /*P2_NOSDATA0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define R0900_P2_NOSDATA0 0xf28b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /*P2_NOSPLHT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define R0900_P2_NOSPLHT1 0xf28c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*P2_NOSPLHT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define R0900_P2_NOSPLHT0 0xf28d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /*P2_NOSPLH1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define R0900_P2_NOSPLH1 0xf28e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*P2_NOSPLH0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define R0900_P2_NOSPLH0 0xf28f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /*P2_CAR2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define R0900_P2_CAR2CFG 0xf290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define F0900_P2_CARRIER3_DISABLE 0xf2900040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define F0900_P2_ROTA2ON 0xf2900004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define F0900_P2_PH_DET_ALGO2 0xf2900003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*P2_CFR2CFR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define R0900_P2_CFR2CFR1 0xf291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define F0900_P2_EN_S2CAR2CENTER 0xf2910020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define F0900_P2_DIS_BCHERRCFR2 0xf2910010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define F0900_P2_CFR2TOCFR1_BETA 0xf2910007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*P2_CFR22*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define R0900_P2_CFR22 0xf293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define F0900_P2_CAR2_FREQ2 0xf29301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /*P2_CFR21*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define R0900_P2_CFR21 0xf294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define F0900_P2_CAR2_FREQ1 0xf29400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*P2_CFR20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define R0900_P2_CFR20 0xf295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define F0900_P2_CAR2_FREQ0 0xf29500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /*P2_ACLC2S2Q*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define R0900_P2_ACLC2S2Q 0xf297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define F0900_P2_ENAB_SPSKSYMB 0xf2970080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /*P2_ACLC2S28*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define R0900_P2_ACLC2S28 0xf298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define F0900_P2_OLDI3Q_MODE 0xf2980080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*P2_ACLC2S216A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define R0900_P2_ACLC2S216A 0xf299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define F0900_P2_DIS_C3STOPA2 0xf2990080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define F0900_P2_CAR2S2_16ADERAT 0xf2990040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*P2_ACLC2S232A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define R0900_P2_ACLC2S232A 0xf29a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*P2_BCLC2S2Q*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define R0900_P2_BCLC2S2Q 0xf29c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /*P2_BCLC2S28*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define R0900_P2_BCLC2S28 0xf29d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /*P2_BCLC2S216A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define R0900_P2_BCLC2S216A 0xf29e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /*P2_BCLC2S232A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define R0900_P2_BCLC2S232A 0xf29f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /*P2_PLROOT2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define R0900_P2_PLROOT2 0xf2ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /*P2_PLROOT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define R0900_P2_PLROOT1 0xf2ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /*P2_PLROOT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define R0900_P2_PLROOT0 0xf2ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*P2_MODCODLST0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define R0900_P2_MODCODLST0 0xf2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /*P2_MODCODLST1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define R0900_P2_MODCODLST1 0xf2b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define F0900_P2_DIS_MODCOD29 0xf2b100f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /*P2_MODCODLST2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define R0900_P2_MODCODLST2 0xf2b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /*P2_MODCODLST3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define R0900_P2_MODCODLST3 0xf2b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*P2_MODCODLST4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define R0900_P2_MODCODLST4 0xf2b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /*P2_MODCODLST5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define R0900_P2_MODCODLST5 0xf2b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /*P2_MODCODLST6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define R0900_P2_MODCODLST6 0xf2b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /*P2_MODCODLST7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define R0900_P2_MODCODLST7 0xf2b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define F0900_P2_DIS_8P_9_10 0xf2b700f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define F0900_P2_DIS_8P_8_9 0xf2b7000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /*P2_MODCODLST8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define R0900_P2_MODCODLST8 0xf2b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define F0900_P2_DIS_8P_5_6 0xf2b800f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define F0900_P2_DIS_8P_3_4 0xf2b8000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*P2_MODCODLST9*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define R0900_P2_MODCODLST9 0xf2b9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define F0900_P2_DIS_8P_2_3 0xf2b900f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define F0900_P2_DIS_8P_3_5 0xf2b9000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /*P2_MODCODLSTA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define R0900_P2_MODCODLSTA 0xf2ba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define F0900_P2_DIS_QP_9_10 0xf2ba00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define F0900_P2_DIS_QP_8_9 0xf2ba000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /*P2_MODCODLSTB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define R0900_P2_MODCODLSTB 0xf2bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define F0900_P2_DIS_QP_5_6 0xf2bb00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define F0900_P2_DIS_QP_4_5 0xf2bb000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /*P2_MODCODLSTC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define R0900_P2_MODCODLSTC 0xf2bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define F0900_P2_DIS_QP_3_4 0xf2bc00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define F0900_P2_DIS_QP_2_3 0xf2bc000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /*P2_MODCODLSTD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define R0900_P2_MODCODLSTD 0xf2bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define F0900_P2_DIS_QP_3_5 0xf2bd00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define F0900_P2_DIS_QP_1_2 0xf2bd000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /*P2_MODCODLSTE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define R0900_P2_MODCODLSTE 0xf2be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define F0900_P2_DIS_QP_2_5 0xf2be00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define F0900_P2_DIS_QP_1_3 0xf2be000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /*P2_MODCODLSTF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define R0900_P2_MODCODLSTF 0xf2bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define F0900_P2_DIS_QP_1_4 0xf2bf00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*P2_GAUSSR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define R0900_P2_GAUSSR0 0xf2c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define F0900_P2_EN_CCIMODE 0xf2c00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define F0900_P2_R0_GAUSSIEN 0xf2c0007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /*P2_CCIR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define R0900_P2_CCIR0 0xf2c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define F0900_P2_R0_CCI 0xf2c1007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /*P2_CCIQUANT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define R0900_P2_CCIQUANT 0xf2c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define F0900_P2_CCI_BETA 0xf2c200e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define F0900_P2_CCI_QUANT 0xf2c2001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /*P2_CCITHRES*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define R0900_P2_CCITHRES 0xf2c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define F0900_P2_CCI_THRESHOLD 0xf2c300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /*P2_CCIACC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define R0900_P2_CCIACC 0xf2c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define F0900_P2_CCI_VALUE 0xf2c400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /*P2_DMDRESCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define R0900_P2_DMDRESCFG 0xf2c6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define F0900_P2_DMDRES_RESET 0xf2c60080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define F0900_P2_DMDRES_STRALL 0xf2c60008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define F0900_P2_DMDRES_NEWONLY 0xf2c60004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define F0900_P2_DMDRES_NOSTORE 0xf2c60002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /*P2_DMDRESADR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define R0900_P2_DMDRESADR 0xf2c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define F0900_P2_DMDRES_MEMFULL 0xf2c70030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define F0900_P2_DMDRES_RESNBR 0xf2c7000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /*P2_DMDRESDATA7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define R0900_P2_DMDRESDATA7 0xf2c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define F0900_P2_DMDRES_DATA7 0xf2c800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*P2_DMDRESDATA6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define R0900_P2_DMDRESDATA6 0xf2c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define F0900_P2_DMDRES_DATA6 0xf2c900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /*P2_DMDRESDATA5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define R0900_P2_DMDRESDATA5 0xf2ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define F0900_P2_DMDRES_DATA5 0xf2ca00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /*P2_DMDRESDATA4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define R0900_P2_DMDRESDATA4 0xf2cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define F0900_P2_DMDRES_DATA4 0xf2cb00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /*P2_DMDRESDATA3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define R0900_P2_DMDRESDATA3 0xf2cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define F0900_P2_DMDRES_DATA3 0xf2cc00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /*P2_DMDRESDATA2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define R0900_P2_DMDRESDATA2 0xf2cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define F0900_P2_DMDRES_DATA2 0xf2cd00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /*P2_DMDRESDATA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define R0900_P2_DMDRESDATA1 0xf2ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define F0900_P2_DMDRES_DATA1 0xf2ce00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /*P2_DMDRESDATA0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define R0900_P2_DMDRESDATA0 0xf2cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define F0900_P2_DMDRES_DATA0 0xf2cf00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /*P2_FFEI1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define R0900_P2_FFEI1 0xf2d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define F0900_P2_FFE_ACCI1 0xf2d001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /*P2_FFEQ1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define R0900_P2_FFEQ1 0xf2d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define F0900_P2_FFE_ACCQ1 0xf2d101ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /*P2_FFEI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define R0900_P2_FFEI2 0xf2d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define F0900_P2_FFE_ACCI2 0xf2d201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /*P2_FFEQ2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define R0900_P2_FFEQ2 0xf2d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define F0900_P2_FFE_ACCQ2 0xf2d301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /*P2_FFEI3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define R0900_P2_FFEI3 0xf2d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define F0900_P2_FFE_ACCI3 0xf2d401ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /*P2_FFEQ3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define R0900_P2_FFEQ3 0xf2d5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define F0900_P2_FFE_ACCQ3 0xf2d501ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /*P2_FFEI4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define R0900_P2_FFEI4 0xf2d6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define F0900_P2_FFE_ACCI4 0xf2d601ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /*P2_FFEQ4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define R0900_P2_FFEQ4 0xf2d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define F0900_P2_FFE_ACCQ4 0xf2d701ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /*P2_FFECFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define R0900_P2_FFECFG 0xf2d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define F0900_P2_EQUALFFE_ON 0xf2d80040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define F0900_P2_MU_EQUALFFE 0xf2d80007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /*P2_TNRCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define R0900_P2_TNRCFG 0xf2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define F0900_P2_TUN_ACKFAIL 0xf2e00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define F0900_P2_TUN_TYPE 0xf2e00070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define F0900_P2_TUN_SECSTOP 0xf2e00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define F0900_P2_TUN_VCOSRCH 0xf2e00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define F0900_P2_TUN_MADDRESS 0xf2e00003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /*P2_TNRCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define R0900_P2_TNRCFG2 0xf2e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define F0900_P2_TUN_IQSWAP 0xf2e10080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define F0900_P2_DIS_BWCALC 0xf2e10004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define F0900_P2_SHORT_WAITSTATES 0xf2e10002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /*P2_TNRXTAL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define R0900_P2_TNRXTAL 0xf2e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define F0900_P2_TUN_XTALFREQ 0xf2e4001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /*P2_TNRSTEPS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define R0900_P2_TNRSTEPS 0xf2e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define F0900_P2_TUNER_BW0P125 0xf2e70080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define F0900_P2_BWINC_OFFSET 0xf2e70170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define F0900_P2_SOFTSTEP_RNG 0xf2e70008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define F0900_P2_TUN_BWOFFSET 0xf2e70007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /*P2_TNRGAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define R0900_P2_TNRGAIN 0xf2e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define F0900_P2_TUN_KDIVEN 0xf2e800c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define F0900_P2_STB6X00_OCK 0xf2e80030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define F0900_P2_TUN_GAIN 0xf2e8000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /*P2_TNRRF1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define R0900_P2_TNRRF1 0xf2e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define F0900_P2_TUN_RFFREQ2 0xf2e900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /*P2_TNRRF0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define R0900_P2_TNRRF0 0xf2ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /*P2_TNRBW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define R0900_P2_TNRBW 0xf2eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define F0900_P2_TUN_BW 0xf2eb003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*P2_TNRADJ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define R0900_P2_TNRADJ 0xf2ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define F0900_P2_STB61X0_CALTIME 0xf2ec0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /*P2_TNRCTL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define R0900_P2_TNRCTL2 0xf2ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define F0900_P2_STB61X0_CALOFF 0xf2ed0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define F0900_P2_STB6XX0_SYN 0xf2ed0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /*P2_TNRCFG3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define R0900_P2_TNRCFG3 0xf2ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define F0900_P2_TUN_PLLFREQ 0xf2ee001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /*P2_TNRLAUNCH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define R0900_P2_TNRLAUNCH 0xf2f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /*P2_TNRLD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define R0900_P2_TNRLD 0xf2f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define F0900_P2_TUNLD_VCOING 0xf2f00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define F0900_P2_TUN_REG1FAIL 0xf2f00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define F0900_P2_TUN_REG2FAIL 0xf2f00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define F0900_P2_TUN_REG3FAIL 0xf2f00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define F0900_P2_TUN_REG4FAIL 0xf2f00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define F0900_P2_TUN_REG5FAIL 0xf2f00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define F0900_P2_TUN_BWING 0xf2f00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define F0900_P2_TUN_LOCKED 0xf2f00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /*P2_TNROBSL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define R0900_P2_TNROBSL 0xf2f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define F0900_P2_TUN_I2CABORTED 0xf2f60080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define F0900_P2_TUN_LPEN 0xf2f60040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define F0900_P2_TUN_FCCK 0xf2f60020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define F0900_P2_TUN_I2CLOCKED 0xf2f60010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define F0900_P2_TUN_PROGDONE 0xf2f6000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define F0900_P2_TUN_RFRESTE1 0xf2f60003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /*P2_TNRRESTE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define R0900_P2_TNRRESTE 0xf2f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define F0900_P2_TUN_RFRESTE0 0xf2f700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /*P2_SMAPCOEF7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define R0900_P2_SMAPCOEF7 0xf300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define F0900_P2_DIS_QSCALE 0xf3000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /*P2_SMAPCOEF6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define R0900_P2_SMAPCOEF6 0xf301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define F0900_P2_ADJ_8PSKLLR1 0xf3010004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define F0900_P2_OLD_8PSKLLR1 0xf3010002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define F0900_P2_DIS_AB8PSK 0xf3010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /*P2_SMAPCOEF5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define R0900_P2_SMAPCOEF5 0xf302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define F0900_P2_DIS_8SCALE 0xf3020080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /*P2_NCO2MAX1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define R0900_P2_NCO2MAX1 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define F0900_P2_TETA2_MAXVABS1 0xf31400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /*P2_NCO2MAX0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define R0900_P2_NCO2MAX0 0xf315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define F0900_P2_TETA2_MAXVABS0 0xf31500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /*P2_NCO2FR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define R0900_P2_NCO2FR1 0xf316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /*P2_NCO2FR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define R0900_P2_NCO2FR0 0xf317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /*P2_CFR2AVRGE1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define R0900_P2_CFR2AVRGE1 0xf318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /*P2_CFR2AVRGE0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define R0900_P2_CFR2AVRGE0 0xf319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /*P2_DMDPLHSTAT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define R0900_P2_DMDPLHSTAT 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define F0900_P2_PLH_STATISTIC 0xf32000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /*P2_LOCKTIME3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define R0900_P2_LOCKTIME3 0xf322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /*P2_LOCKTIME2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define R0900_P2_LOCKTIME2 0xf323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /*P2_LOCKTIME1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define R0900_P2_LOCKTIME1 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /*P2_LOCKTIME0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define R0900_P2_LOCKTIME0 0xf325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /*P2_VITSCALE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define R0900_P2_VITSCALE 0xf332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define F0900_P2_NVTH_NOSRANGE 0xf3320080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define F0900_P2_VERROR_MAXMODE 0xf3320040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define F0900_P2_NSLOWSN_LOCKED 0xf3320008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define F0900_P2_DIS_RSFLOCK 0xf3320002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /*P2_FECM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define R0900_P2_FECM 0xf333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define F0900_P2_DSS_DVB 0xf3330080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define F0900_P2_DSS_SRCH 0xf3330010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define F0900_P2_SYNCVIT 0xf3330002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define F0900_P2_IQINV 0xf3330001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /*P2_VTH12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define R0900_P2_VTH12 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define F0900_P2_VTH12 0xf33400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) /*P2_VTH23*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define R0900_P2_VTH23 0xf335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define F0900_P2_VTH23 0xf33500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /*P2_VTH34*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define R0900_P2_VTH34 0xf336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define F0900_P2_VTH34 0xf33600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /*P2_VTH56*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define R0900_P2_VTH56 0xf337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define F0900_P2_VTH56 0xf33700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /*P2_VTH67*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define R0900_P2_VTH67 0xf338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define F0900_P2_VTH67 0xf33800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /*P2_VTH78*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define R0900_P2_VTH78 0xf339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define F0900_P2_VTH78 0xf33900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /*P2_VITCURPUN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define R0900_P2_VITCURPUN 0xf33a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define F0900_P2_VIT_CURPUN 0xf33a001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /*P2_VERROR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define R0900_P2_VERROR 0xf33b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define F0900_P2_REGERR_VIT 0xf33b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /*P2_PRVIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define R0900_P2_PRVIT 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define F0900_P2_DIS_VTHLOCK 0xf33c0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define F0900_P2_E7_8VIT 0xf33c0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define F0900_P2_E6_7VIT 0xf33c0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define F0900_P2_E5_6VIT 0xf33c0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define F0900_P2_E3_4VIT 0xf33c0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define F0900_P2_E2_3VIT 0xf33c0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define F0900_P2_E1_2VIT 0xf33c0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /*P2_VAVSRVIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define R0900_P2_VAVSRVIT 0xf33d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define F0900_P2_AMVIT 0xf33d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define F0900_P2_FROZENVIT 0xf33d0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define F0900_P2_SNVIT 0xf33d0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define F0900_P2_TOVVIT 0xf33d000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define F0900_P2_HYPVIT 0xf33d0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /*P2_VSTATUSVIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define R0900_P2_VSTATUSVIT 0xf33e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define F0900_P2_PRFVIT 0xf33e0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define F0900_P2_LOCKEDVIT 0xf33e0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /*P2_VTHINUSE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define R0900_P2_VTHINUSE 0xf33f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define F0900_P2_VIT_INUSE 0xf33f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /*P2_KDIV12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define R0900_P2_KDIV12 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define F0900_P2_K_DIVIDER_12 0xf340007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /*P2_KDIV23*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define R0900_P2_KDIV23 0xf341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define F0900_P2_K_DIVIDER_23 0xf341007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /*P2_KDIV34*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define R0900_P2_KDIV34 0xf342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define F0900_P2_K_DIVIDER_34 0xf342007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /*P2_KDIV56*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define R0900_P2_KDIV56 0xf343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define F0900_P2_K_DIVIDER_56 0xf343007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /*P2_KDIV67*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define R0900_P2_KDIV67 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define F0900_P2_K_DIVIDER_67 0xf344007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /*P2_KDIV78*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define R0900_P2_KDIV78 0xf345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define F0900_P2_K_DIVIDER_78 0xf345007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /*P2_PDELCTRL1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define R0900_P2_PDELCTRL1 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define F0900_P2_INV_MISMASK 0xf3500080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define F0900_P2_FILTER_EN 0xf3500020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define F0900_P2_EN_MIS00 0xf3500002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define F0900_P2_ALGOSWRST 0xf3500001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /*P2_PDELCTRL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define R0900_P2_PDELCTRL2 0xf351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define F0900_P2_RESET_UPKO_COUNT 0xf3510040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define F0900_P2_FRAME_MODE 0xf3510002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define F0900_P2_NOBCHERRFLG_USE 0xf3510001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /*P2_HYSTTHRESH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define R0900_P2_HYSTTHRESH 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define F0900_P2_UNLCK_THRESH 0xf35400f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define F0900_P2_DELIN_LCK_THRESH 0xf354000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /*P2_ISIENTRY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define R0900_P2_ISIENTRY 0xf35e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define F0900_P2_ISI_ENTRY 0xf35e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /*P2_ISIBITENA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define R0900_P2_ISIBITENA 0xf35f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define F0900_P2_ISI_BIT_EN 0xf35f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /*P2_MATSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define R0900_P2_MATSTR1 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define F0900_P2_MATYPE_CURRENT1 0xf36000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /*P2_MATSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define R0900_P2_MATSTR0 0xf361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define F0900_P2_MATYPE_CURRENT0 0xf36100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /*P2_UPLSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define R0900_P2_UPLSTR1 0xf362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define F0900_P2_UPL_CURRENT1 0xf36200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /*P2_UPLSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define R0900_P2_UPLSTR0 0xf363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define F0900_P2_UPL_CURRENT0 0xf36300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /*P2_DFLSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define R0900_P2_DFLSTR1 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define F0900_P2_DFL_CURRENT1 0xf36400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /*P2_DFLSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define R0900_P2_DFLSTR0 0xf365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define F0900_P2_DFL_CURRENT0 0xf36500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /*P2_SYNCSTR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define R0900_P2_SYNCSTR 0xf366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define F0900_P2_SYNC_CURRENT 0xf36600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) /*P2_SYNCDSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define R0900_P2_SYNCDSTR1 0xf367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define F0900_P2_SYNCD_CURRENT1 0xf36700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /*P2_SYNCDSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define R0900_P2_SYNCDSTR0 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define F0900_P2_SYNCD_CURRENT0 0xf36800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /*P2_PDELSTATUS1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define R0900_P2_PDELSTATUS1 0xf369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define F0900_P2_PKTDELIN_DELOCK 0xf3690080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define F0900_P2_CONTINUOUS_STREAM 0xf3690020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define F0900_P2_UNACCEPTED_STREAM 0xf3690010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define F0900_P2_BCH_ERROR_FLAG 0xf3690008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define F0900_P2_PKTDELIN_LOCK 0xf3690002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define F0900_P2_FIRST_LOCK 0xf3690001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /*P2_PDELSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define R0900_P2_PDELSTATUS2 0xf36a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define F0900_P2_FRAME_MODCOD 0xf36a007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define F0900_P2_FRAME_TYPE 0xf36a0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /*P2_BBFCRCKO1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define R0900_P2_BBFCRCKO1 0xf36b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /*P2_BBFCRCKO0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define R0900_P2_BBFCRCKO0 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*P2_UPCRCKO1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define R0900_P2_UPCRCKO1 0xf36d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) /*P2_UPCRCKO0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define R0900_P2_UPCRCKO0 0xf36e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /*P2_PDELCTRL3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define R0900_P2_PDELCTRL3 0xf36f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define F0900_P2_NOFIFO_BCHERR 0xf36f0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /*P2_TSSTATEM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define R0900_P2_TSSTATEM 0xf370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define F0900_P2_TSDIL_ON 0xf3700080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define F0900_P2_TSRS_ON 0xf3700020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define F0900_P2_TSDESCRAMB_ON 0xf3700010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define F0900_P2_TSFRAME_MODE 0xf3700008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define F0900_P2_TS_DISABLE 0xf3700004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define F0900_P2_TSOUT_NOSYNC 0xf3700001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /*P2_TSCFGH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define R0900_P2_TSCFGH 0xf372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define F0900_P2_TSFIFO_DVBCI 0xf3720080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define F0900_P2_TSFIFO_SERIAL 0xf3720040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define F0900_P2_TSFIFO_DUTY50 0xf3720010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define F0900_P2_TSFIFO_ERRMODE 0xf3720006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define F0900_P2_RST_HWARE 0xf3720001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /*P2_TSCFGM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define R0900_P2_TSCFGM 0xf373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define F0900_P2_TSFIFO_PERMDATA 0xf3730020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define F0900_P2_TSFIFO_DPUNACT 0xf3730002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define F0900_P2_TSFIFO_INVDATA 0xf3730001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /*P2_TSCFGL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define R0900_P2_TSCFGL 0xf374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define F0900_P2_BCHERROR_MODE 0xf3740030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define F0900_P2_TSFIFO_BITSPEED 0xf3740003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /*P2_TSINSDELH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define R0900_P2_TSINSDELH 0xf376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define F0900_P2_TSDEL_XXHEADER 0xf3760040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define F0900_P2_TSDEL_BBHEADER 0xf3760020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define F0900_P2_TSDEL_DATAFIELD 0xf3760010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define F0900_P2_TSINSDEL_ISCR 0xf3760008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define F0900_P2_TSINSDEL_NPD 0xf3760004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define F0900_P2_TSINSDEL_CRC8 0xf3760001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) /*P2_TSDIVN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #define R0900_P2_TSDIVN 0xf379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /*P2_TSCFG4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #define R0900_P2_TSCFG4 0xf37a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /*P2_TSSPEED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define R0900_P2_TSSPEED 0xf380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /*P2_TSSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define R0900_P2_TSSTATUS 0xf381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define F0900_P2_TSFIFO_LINEOK 0xf3810080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #define F0900_P2_TSFIFO_ERROR 0xf3810040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #define F0900_P2_DIL_READY 0xf3810001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /*P2_TSSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) #define R0900_P2_TSSTATUS2 0xf382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) #define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define F0900_P2_DILXX_RESET 0xf3820020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define F0900_P2_TSSERIAL_IMPOS 0xf3820010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #define F0900_P2_SCRAMBDETECT 0xf3820002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) /*P2_TSBITRATE1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define R0900_P2_TSBITRATE1 0xf383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /*P2_TSBITRATE0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) #define R0900_P2_TSBITRATE0 0xf384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) /*P2_ERRCTRL1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #define R0900_P2_ERRCTRL1 0xf398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define F0900_P2_ERR_SOURCE1 0xf39800f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #define F0900_P2_NUM_EVENT1 0xf3980007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /*P2_ERRCNT12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define R0900_P2_ERRCNT12 0xf399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define F0900_P2_ERR_CNT12 0xf399007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) /*P2_ERRCNT11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define R0900_P2_ERRCNT11 0xf39a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #define F0900_P2_ERR_CNT11 0xf39a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /*P2_ERRCNT10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define R0900_P2_ERRCNT10 0xf39b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define F0900_P2_ERR_CNT10 0xf39b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /*P2_ERRCTRL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define R0900_P2_ERRCTRL2 0xf39c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define F0900_P2_ERR_SOURCE2 0xf39c00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define F0900_P2_NUM_EVENT2 0xf39c0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /*P2_ERRCNT22*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) #define R0900_P2_ERRCNT22 0xf39d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define F0900_P2_ERR_CNT22 0xf39d007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /*P2_ERRCNT21*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define R0900_P2_ERRCNT21 0xf39e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define F0900_P2_ERR_CNT21 0xf39e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) /*P2_ERRCNT20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define R0900_P2_ERRCNT20 0xf39f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define F0900_P2_ERR_CNT20 0xf39f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /*P2_FECSPY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define R0900_P2_FECSPY 0xf3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define F0900_P2_SPY_ENABLE 0xf3a00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define F0900_P2_NO_SYNCBYTE 0xf3a00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define F0900_P2_SERIAL_MODE 0xf3a00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define F0900_P2_UNUSUAL_PACKET 0xf3a00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define F0900_P2_BERMETER_DATAMODE 0xf3a00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define F0900_P2_BERMETER_LMODE 0xf3a00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define F0900_P2_BERMETER_RESET 0xf3a00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /*P2_FSPYCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define R0900_P2_FSPYCFG 0xf3a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define F0900_P2_FECSPY_INPUT 0xf3a100c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define F0900_P2_RST_ON_ERROR 0xf3a10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define F0900_P2_ONE_SHOT 0xf3a10010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define F0900_P2_I2C_MODE 0xf3a1000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define F0900_P2_SPY_HYSTERESIS 0xf3a10003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /*P2_FSPYDATA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define R0900_P2_FSPYDATA 0xf3a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define F0900_P2_SPY_STUFFING 0xf3a20080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define F0900_P2_SPY_CNULLPKT 0xf3a20020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /*P2_FSPYOUT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define R0900_P2_FSPYOUT 0xf3a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define F0900_P2_FSPY_DIRECT 0xf3a30080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define F0900_P2_STUFF_MODE 0xf3a30007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /*P2_FSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define R0900_P2_FSTATUS 0xf3a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define F0900_P2_SPY_ENDSIM 0xf3a40080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define F0900_P2_VALID_SIM 0xf3a40040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define F0900_P2_FOUND_SIGNAL 0xf3a40020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define F0900_P2_DSS_SYNCBYTE 0xf3a40010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define F0900_P2_RESULT_STATE 0xf3a4000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /*P2_FBERCPT4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define R0900_P2_FBERCPT4 0xf3a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define F0900_P2_FBERMETER_CPT4 0xf3a800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /*P2_FBERCPT3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define R0900_P2_FBERCPT3 0xf3a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define F0900_P2_FBERMETER_CPT3 0xf3a900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /*P2_FBERCPT2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define R0900_P2_FBERCPT2 0xf3aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) /*P2_FBERCPT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define R0900_P2_FBERCPT1 0xf3ab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /*P2_FBERCPT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define R0900_P2_FBERCPT0 0xf3ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /*P2_FBERERR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define R0900_P2_FBERERR2 0xf3ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /*P2_FBERERR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define R0900_P2_FBERERR1 0xf3ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /*P2_FBERERR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define R0900_P2_FBERERR0 0xf3af
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define F0900_P2_FBERMETER_ERR0 0xf3af00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /*P2_FSPYBER*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define R0900_P2_FSPYBER 0xf3b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) #define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) #define F0900_P2_FSPYBER_CTIME 0xf3b20007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /*P1_IQCONST*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #define R0900_P1_IQCONST 0xf400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) #define IQCONST REGx(R0900_P1_IQCONST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define F0900_P1_CONSTEL_SELECT 0xf4000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define F0900_P1_IQSYMB_SEL 0xf400001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /*P1_NOSCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #define R0900_P1_NOSCFG 0xf401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define NOSCFG REGx(R0900_P1_NOSCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define F0900_P1_NOSPLH_BETA 0xf4010018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define F0900_P1_NOSDATA_BETA 0xf4010007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) /*P1_ISYMB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define R0900_P1_ISYMB 0xf402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define ISYMB REGx(R0900_P1_ISYMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define F0900_P1_I_SYMBOL 0xf40201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /*P1_QSYMB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define R0900_P1_QSYMB 0xf403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define QSYMB REGx(R0900_P1_QSYMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define F0900_P1_Q_SYMBOL 0xf40301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /*P1_AGC1CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define R0900_P1_AGC1CFG 0xf404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define AGC1CFG REGx(R0900_P1_AGC1CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #define F0900_P1_DC_FROZEN 0xf4040080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define F0900_P1_DC_CORRECT 0xf4040040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define F0900_P1_AMM_FROZEN 0xf4040020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define F0900_P1_AMM_CORRECT 0xf4040010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define F0900_P1_QUAD_FROZEN 0xf4040008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define F0900_P1_QUAD_CORRECT 0xf4040004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) /*P1_AGC1CN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) #define R0900_P1_AGC1CN 0xf406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define AGC1CN REGx(R0900_P1_AGC1CN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) #define F0900_P1_AGC1_LOCKED 0xf4060080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define F0900_P1_AGC1_MINPOWER 0xf4060010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define F0900_P1_AGCOUT_FAST 0xf4060008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define F0900_P1_AGCIQ_BETA 0xf4060007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /*P1_AGC1REF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define R0900_P1_AGC1REF 0xf407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define AGC1REF REGx(R0900_P1_AGC1REF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define F0900_P1_AGCIQ_REF 0xf40700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /*P1_IDCCOMP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define R0900_P1_IDCCOMP 0xf408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define IDCCOMP REGx(R0900_P1_IDCCOMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #define F0900_P1_IAVERAGE_ADJ 0xf40801ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /*P1_QDCCOMP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define R0900_P1_QDCCOMP 0xf409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define QDCCOMP REGx(R0900_P1_QDCCOMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define F0900_P1_QAVERAGE_ADJ 0xf40901ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /*P1_POWERI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define R0900_P1_POWERI 0xf40a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define POWERI REGx(R0900_P1_POWERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #define F0900_P1_POWER_I 0xf40a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) #define POWER_I FLDx(F0900_P1_POWER_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) /*P1_POWERQ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define R0900_P1_POWERQ 0xf40b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #define POWERQ REGx(R0900_P1_POWERQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #define F0900_P1_POWER_Q 0xf40b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #define POWER_Q FLDx(F0900_P1_POWER_Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) /*P1_AGC1AMM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #define R0900_P1_AGC1AMM 0xf40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define AGC1AMM REGx(R0900_P1_AGC1AMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define F0900_P1_AMM_VALUE 0xf40c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /*P1_AGC1QUAD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define R0900_P1_AGC1QUAD 0xf40d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define F0900_P1_QUAD_VALUE 0xf40d01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*P1_AGCIQIN1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #define R0900_P1_AGCIQIN1 0xf40e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) #define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /*P1_AGCIQIN0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #define R0900_P1_AGCIQIN0 0xf40f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) #define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) #define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /*P1_DEMOD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #define R0900_P1_DEMOD 0xf410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define DEMOD REGx(R0900_P1_DEMOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) #define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) #define F0900_P1_SPECINV_CONTROL 0xf4100030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #define F0900_P1_FORCE_ENASAMP 0xf4100008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define F0900_P1_ROLLOFF_CONTROL 0xf4100003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /*P1_DMDMODCOD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define R0900_P1_DMDMODCOD 0xf411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define F0900_P1_MANUAL_MODCOD 0xf4110080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define F0900_P1_DEMOD_MODCOD 0xf411007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define F0900_P1_DEMOD_TYPE 0xf4110003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) /*P1_DSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) #define R0900_P1_DSTATUS 0xf412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define DSTATUS REGx(R0900_P1_DSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define F0900_P1_CAR_LOCK 0xf4120080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define F0900_P1_TMGLOCK_QUALITY 0xf4120060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define F0900_P1_LOCK_DEFINITIF 0xf4120008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define F0900_P1_OVADC_DETECT 0xf4120001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /*P1_DSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #define R0900_P1_DSTATUS2 0xf413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) #define DSTATUS2 REGx(R0900_P1_DSTATUS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #define F0900_P1_DEMOD_DELOCK 0xf4130080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) #define F0900_P1_AGC2_OVERFLOW 0xf4130004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) #define F0900_P1_CFR_OVERFLOW 0xf4130002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) #define F0900_P1_GAMMA_OVERUNDER 0xf4130001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /*P1_DMDCFGMD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define R0900_P1_DMDCFGMD 0xf414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) #define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) #define F0900_P1_DVBS2_ENABLE 0xf4140080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #define F0900_P1_DVBS1_ENABLE 0xf4140040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) #define F0900_P1_SCAN_ENABLE 0xf4140010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) #define F0900_P1_CFR_AUTOSCAN 0xf4140008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define F0900_P1_TUN_RNG 0xf4140003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) /*P1_DMDCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #define R0900_P1_DMDCFG2 0xf415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define DMDCFG2 REGx(R0900_P1_DMDCFG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define F0900_P1_INFINITE_RELOCK 0xf4150010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /*P1_DMDISTATE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) #define R0900_P1_DMDISTATE 0xf416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) #define DMDISTATE REGx(R0900_P1_DMDISTATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #define F0900_P1_I2C_DEMOD_MODE 0xf416001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /*P1_DMDT0M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #define R0900_P1_DMDT0M 0xf417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define DMDT0M REGx(R0900_P1_DMDT0M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #define F0900_P1_DMDT0_MIN 0xf41700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) /*P1_DMDSTATE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #define R0900_P1_DMDSTATE 0xf41b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) #define DMDSTATE REGx(R0900_P1_DMDSTATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #define F0900_P1_HEADER_MODE 0xf41b0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) /*P1_DMDFLYW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define R0900_P1_DMDFLYW 0xf41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #define DMDFLYW REGx(R0900_P1_DMDFLYW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) #define F0900_P1_I2C_IRQVAL 0xf41c00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) #define F0900_P1_FLYWHEEL_CPT 0xf41c000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) #define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /*P1_DSTATUS3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) #define R0900_P1_DSTATUS3 0xf41d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) #define DSTATUS3 REGx(R0900_P1_DSTATUS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) #define F0900_P1_DEMOD_CFGMODE 0xf41d0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /*P1_DMDCFG3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) #define R0900_P1_DMDCFG3 0xf41e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) #define DMDCFG3 REGx(R0900_P1_DMDCFG3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) #define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /*P1_DMDCFG4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #define R0900_P1_DMDCFG4 0xf41f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #define DMDCFG4 REGx(R0900_P1_DMDCFG4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) #define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /*P1_CORRELMANT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #define R0900_P1_CORRELMANT 0xf420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #define CORRELMANT REGx(R0900_P1_CORRELMANT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) #define F0900_P1_CORREL_MANT 0xf42000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /*P1_CORRELABS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #define R0900_P1_CORRELABS 0xf421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) #define CORRELABS REGx(R0900_P1_CORRELABS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #define F0900_P1_CORREL_ABS 0xf42100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) /*P1_CORRELEXP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define R0900_P1_CORRELEXP 0xf422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define CORRELEXP REGx(R0900_P1_CORRELEXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define F0900_P1_CORREL_ABSEXP 0xf42200f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) #define F0900_P1_CORREL_EXP 0xf422000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) /*P1_PLHMODCOD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) #define R0900_P1_PLHMODCOD 0xf424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) #define F0900_P1_SPECINV_DEMOD 0xf4240080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) #define F0900_P1_PLH_MODCOD 0xf424007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #define F0900_P1_PLH_TYPE 0xf4240003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /*P1_DMDREG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #define R0900_P1_DMDREG 0xf425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #define DMDREG REGx(R0900_P1_DMDREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define F0900_P1_DECIM_PLFRAMES 0xf4250001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /*P1_AGC2O*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define R0900_P1_AGC2O 0xf42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #define AGC2O REGx(R0900_P1_AGC2O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define F0900_P1_AGC2_COEF 0xf42c0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /*P1_AGC2REF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define R0900_P1_AGC2REF 0xf42d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #define AGC2REF REGx(R0900_P1_AGC2REF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #define F0900_P1_AGC2_REF 0xf42d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) /*P1_AGC1ADJ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #define R0900_P1_AGC1ADJ 0xf42e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #define F0900_P1_AGC1_ADJUSTED 0xf42e007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /*P1_AGC2I1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #define R0900_P1_AGC2I1 0xf436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) #define AGC2I1 REGx(R0900_P1_AGC2I1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) #define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /*P1_AGC2I0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define R0900_P1_AGC2I0 0xf437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define AGC2I0 REGx(R0900_P1_AGC2I0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /*P1_CARCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #define R0900_P1_CARCFG 0xf438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #define CARCFG REGx(R0900_P1_CARCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) #define F0900_P1_CFRUPLOW_AUTO 0xf4380080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) #define F0900_P1_CFRUPLOW_TEST 0xf4380040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) #define F0900_P1_ROTAON 0xf4380004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) #define F0900_P1_PH_DET_ALGO 0xf4380003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /*P1_ACLC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #define R0900_P1_ACLC 0xf439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) #define ACLC REGx(R0900_P1_ACLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) #define F0900_P1_CAR_ALPHA_MANT 0xf4390030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) #define F0900_P1_CAR_ALPHA_EXP 0xf439000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /*P1_BCLC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) #define R0900_P1_BCLC 0xf43a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) #define BCLC REGx(R0900_P1_BCLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) #define F0900_P1_CAR_BETA_MANT 0xf43a0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) #define F0900_P1_CAR_BETA_EXP 0xf43a000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /*P1_CARFREQ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) #define R0900_P1_CARFREQ 0xf43d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) #define CARFREQ REGx(R0900_P1_CARFREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) #define F0900_P1_KC_COARSE_EXP 0xf43d00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) #define F0900_P1_BETA_FREQ 0xf43d000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /*P1_CARHDR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) #define R0900_P1_CARHDR 0xf43e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #define CARHDR REGx(R0900_P1_CARHDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) #define F0900_P1_K_FREQ_HDR 0xf43e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /*P1_LDT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) #define R0900_P1_LDT 0xf43f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) #define LDT REGx(R0900_P1_LDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) #define F0900_P1_CARLOCK_THRES 0xf43f01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /*P1_LDT2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) #define R0900_P1_LDT2 0xf440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) #define LDT2 REGx(R0900_P1_LDT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #define F0900_P1_CARLOCK_THRES2 0xf44001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /*P1_CFRICFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) #define R0900_P1_CFRICFG 0xf441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) #define CFRICFG REGx(R0900_P1_CFRICFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) #define F0900_P1_NEG_CFRSTEP 0xf4410001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) /*P1_CFRUP1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) #define R0900_P1_CFRUP1 0xf442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) #define CFRUP1 REGx(R0900_P1_CFRUP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) #define F0900_P1_CFR_UP1 0xf44201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) #define CFR_UP1 FLDx(F0900_P1_CFR_UP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /*P1_CFRUP0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #define R0900_P1_CFRUP0 0xf443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #define CFRUP0 REGx(R0900_P1_CFRUP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) #define F0900_P1_CFR_UP0 0xf44300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #define CFR_UP0 FLDx(F0900_P1_CFR_UP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /*P1_CFRLOW1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define R0900_P1_CFRLOW1 0xf446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define CFRLOW1 REGx(R0900_P1_CFRLOW1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define F0900_P1_CFR_LOW1 0xf44601ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /*P1_CFRLOW0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) #define R0900_P1_CFRLOW0 0xf447
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) #define CFRLOW0 REGx(R0900_P1_CFRLOW0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) #define F0900_P1_CFR_LOW0 0xf44700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) #define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /*P1_CFRINIT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #define R0900_P1_CFRINIT1 0xf448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) #define CFRINIT1 REGx(R0900_P1_CFRINIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) #define F0900_P1_CFR_INIT1 0xf44801ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) #define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) /*P1_CFRINIT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) #define R0900_P1_CFRINIT0 0xf449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) #define CFRINIT0 REGx(R0900_P1_CFRINIT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) #define F0900_P1_CFR_INIT0 0xf44900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) /*P1_CFRINC1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) #define R0900_P1_CFRINC1 0xf44a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) #define CFRINC1 REGx(R0900_P1_CFRINC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) #define F0900_P1_MANUAL_CFRINC 0xf44a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) #define F0900_P1_CFR_INC1 0xf44a003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) /*P1_CFRINC0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #define R0900_P1_CFRINC0 0xf44b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) #define CFRINC0 REGx(R0900_P1_CFRINC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #define F0900_P1_CFR_INC0 0xf44b00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /*P1_CFR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #define R0900_P1_CFR2 0xf44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) #define CFR2 REGx(R0900_P1_CFR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) #define F0900_P1_CAR_FREQ2 0xf44c01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) #define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /*P1_CFR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #define R0900_P1_CFR1 0xf44d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define CFR1 REGx(R0900_P1_CFR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #define F0900_P1_CAR_FREQ1 0xf44d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) /*P1_CFR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #define R0900_P1_CFR0 0xf44e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) #define CFR0 REGx(R0900_P1_CFR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #define F0900_P1_CAR_FREQ0 0xf44e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /*P1_LDI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define R0900_P1_LDI 0xf44f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #define LDI REGx(R0900_P1_LDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) #define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) /*P1_TMGCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #define R0900_P1_TMGCFG 0xf450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) #define TMGCFG REGx(R0900_P1_TMGCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #define F0900_P1_TMGLOCK_BETA 0xf45000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define F0900_P1_DO_TIMING_CORR 0xf4500010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #define F0900_P1_TMG_MINFREQ 0xf4500003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) /*P1_RTC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define R0900_P1_RTC 0xf451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #define RTC REGx(R0900_P1_RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define F0900_P1_TMGALPHA_EXP 0xf45100f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define F0900_P1_TMGBETA_EXP 0xf451000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) /*P1_RTCS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) #define R0900_P1_RTCS2 0xf452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) #define RTCS2 REGx(R0900_P1_RTCS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) #define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) #define F0900_P1_TMGBETAS2_EXP 0xf452000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /*P1_TMGTHRISE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) #define R0900_P1_TMGTHRISE 0xf453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) #define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) #define F0900_P1_TMGLOCK_THRISE 0xf45300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) /*P1_TMGTHFALL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #define R0900_P1_TMGTHFALL 0xf454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) #define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) #define F0900_P1_TMGLOCK_THFALL 0xf45400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) /*P1_SFRUPRATIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) #define R0900_P1_SFRUPRATIO 0xf455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) #define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) #define F0900_P1_SFR_UPRATIO 0xf45500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /*P1_SFRLOWRATIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) #define R0900_P1_SFRLOWRATIO 0xf456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) #define F0900_P1_SFR_LOWRATIO 0xf45600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /*P1_KREFTMG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #define R0900_P1_KREFTMG 0xf458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) #define KREFTMG REGx(R0900_P1_KREFTMG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) #define F0900_P1_KREF_TMG 0xf45800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) /*P1_SFRSTEP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) #define R0900_P1_SFRSTEP 0xf459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) #define SFRSTEP REGx(R0900_P1_SFRSTEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) #define F0900_P1_SFR_SCANSTEP 0xf45900f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) #define F0900_P1_SFR_CENTERSTEP 0xf459000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) /*P1_TMGCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) #define R0900_P1_TMGCFG2 0xf45a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) #define TMGCFG2 REGx(R0900_P1_TMGCFG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) #define F0900_P1_SFRRATIO_FINE 0xf45a0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /*P1_KREFTMG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #define R0900_P1_KREFTMG2 0xf45b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define KREFTMG2 REGx(R0900_P1_KREFTMG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #define F0900_P1_KREF_TMG2 0xf45b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) /*P1_SFRINIT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) #define R0900_P1_SFRINIT1 0xf45e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) #define SFRINIT1 REGx(R0900_P1_SFRINIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) #define F0900_P1_SFR_INIT1 0xf45e007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /*P1_SFRINIT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #define R0900_P1_SFRINIT0 0xf45f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) #define SFRINIT0 REGx(R0900_P1_SFRINIT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #define F0900_P1_SFR_INIT0 0xf45f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /*P1_SFRUP1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define R0900_P1_SFRUP1 0xf460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #define SFRUP1 REGx(R0900_P1_SFRUP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) #define F0900_P1_AUTO_GUP 0xf4600080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) #define F0900_P1_SYMB_FREQ_UP1 0xf460007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /*P1_SFRUP0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #define R0900_P1_SFRUP0 0xf461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) #define SFRUP0 REGx(R0900_P1_SFRUP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) #define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) /*P1_SFRLOW1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) #define R0900_P1_SFRLOW1 0xf462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #define SFRLOW1 REGx(R0900_P1_SFRLOW1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #define F0900_P1_AUTO_GLOW 0xf4620080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) #define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) #define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /*P1_SFRLOW0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define R0900_P1_SFRLOW0 0xf463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #define SFRLOW0 REGx(R0900_P1_SFRLOW0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) #define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /*P1_SFR3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #define R0900_P1_SFR3 0xf464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) #define SFR3 REGx(R0900_P1_SFR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) #define F0900_P1_SYMB_FREQ3 0xf46400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) #define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /*P1_SFR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) #define R0900_P1_SFR2 0xf465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) #define SFR2 REGx(R0900_P1_SFR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) #define F0900_P1_SYMB_FREQ2 0xf46500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) #define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) /*P1_SFR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) #define R0900_P1_SFR1 0xf466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) #define SFR1 REGx(R0900_P1_SFR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) #define F0900_P1_SYMB_FREQ1 0xf46600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) #define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /*P1_SFR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) #define R0900_P1_SFR0 0xf467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) #define SFR0 REGx(R0900_P1_SFR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) #define F0900_P1_SYMB_FREQ0 0xf46700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) #define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) /*P1_TMGREG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) #define R0900_P1_TMGREG2 0xf468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) #define TMGREG2 REGx(R0900_P1_TMGREG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #define F0900_P1_TMGREG2 0xf46800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) /*P1_TMGREG1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) #define R0900_P1_TMGREG1 0xf469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #define TMGREG1 REGx(R0900_P1_TMGREG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) #define F0900_P1_TMGREG1 0xf46900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /*P1_TMGREG0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) #define R0900_P1_TMGREG0 0xf46a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #define TMGREG0 REGx(R0900_P1_TMGREG0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) #define F0900_P1_TMGREG0 0xf46a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /*P1_TMGLOCK1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) #define R0900_P1_TMGLOCK1 0xf46b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) #define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) /*P1_TMGLOCK0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #define R0900_P1_TMGLOCK0 0xf46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) #define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /*P1_TMGOBS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define R0900_P1_TMGOBS 0xf46d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #define TMGOBS REGx(R0900_P1_TMGOBS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) #define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) /*P1_EQUALCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #define R0900_P1_EQUALCFG 0xf46f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) #define EQUALCFG REGx(R0900_P1_EQUALCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) #define F0900_P1_EQUAL_ON 0xf46f0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) #define F0900_P1_MU_EQUALDFE 0xf46f0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) /*P1_EQUAI1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) #define R0900_P1_EQUAI1 0xf470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define EQUAI1 REGx(R0900_P1_EQUAI1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define F0900_P1_EQUA_ACCI1 0xf47001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) /*P1_EQUAQ1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) #define R0900_P1_EQUAQ1 0xf471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) #define EQUAQ1 REGx(R0900_P1_EQUAQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #define F0900_P1_EQUA_ACCQ1 0xf47101ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /*P1_EQUAI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #define R0900_P1_EQUAI2 0xf472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) #define EQUAI2 REGx(R0900_P1_EQUAI2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #define F0900_P1_EQUA_ACCI2 0xf47201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) /*P1_EQUAQ2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) #define R0900_P1_EQUAQ2 0xf473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #define EQUAQ2 REGx(R0900_P1_EQUAQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) #define F0900_P1_EQUA_ACCQ2 0xf47301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) /*P1_EQUAI3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #define R0900_P1_EQUAI3 0xf474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) #define EQUAI3 REGx(R0900_P1_EQUAI3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) #define F0900_P1_EQUA_ACCI3 0xf47401ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) /*P1_EQUAQ3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #define R0900_P1_EQUAQ3 0xf475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define EQUAQ3 REGx(R0900_P1_EQUAQ3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #define F0900_P1_EQUA_ACCQ3 0xf47501ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) /*P1_EQUAI4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) #define R0900_P1_EQUAI4 0xf476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) #define EQUAI4 REGx(R0900_P1_EQUAI4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) #define F0900_P1_EQUA_ACCI4 0xf47601ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) /*P1_EQUAQ4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) #define R0900_P1_EQUAQ4 0xf477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) #define EQUAQ4 REGx(R0900_P1_EQUAQ4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) #define F0900_P1_EQUA_ACCQ4 0xf47701ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /*P1_EQUAI5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) #define R0900_P1_EQUAI5 0xf478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) #define EQUAI5 REGx(R0900_P1_EQUAI5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) #define F0900_P1_EQUA_ACCI5 0xf47801ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /*P1_EQUAQ5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) #define R0900_P1_EQUAQ5 0xf479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) #define EQUAQ5 REGx(R0900_P1_EQUAQ5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) #define F0900_P1_EQUA_ACCQ5 0xf47901ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /*P1_EQUAI6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) #define R0900_P1_EQUAI6 0xf47a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #define EQUAI6 REGx(R0900_P1_EQUAI6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #define F0900_P1_EQUA_ACCI6 0xf47a01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /*P1_EQUAQ6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #define R0900_P1_EQUAQ6 0xf47b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #define EQUAQ6 REGx(R0900_P1_EQUAQ6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #define F0900_P1_EQUA_ACCQ6 0xf47b01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) /*P1_EQUAI7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #define R0900_P1_EQUAI7 0xf47c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #define EQUAI7 REGx(R0900_P1_EQUAI7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) #define F0900_P1_EQUA_ACCI7 0xf47c01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /*P1_EQUAQ7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) #define R0900_P1_EQUAQ7 0xf47d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) #define EQUAQ7 REGx(R0900_P1_EQUAQ7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) #define F0900_P1_EQUA_ACCQ7 0xf47d01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /*P1_EQUAI8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) #define R0900_P1_EQUAI8 0xf47e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) #define EQUAI8 REGx(R0900_P1_EQUAI8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) #define F0900_P1_EQUA_ACCI8 0xf47e01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) /*P1_EQUAQ8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) #define R0900_P1_EQUAQ8 0xf47f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) #define EQUAQ8 REGx(R0900_P1_EQUAQ8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) #define F0900_P1_EQUA_ACCQ8 0xf47f01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) /*P1_NNOSDATAT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) #define R0900_P1_NNOSDATAT1 0xf480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) #define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) #define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) #define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) /*P1_NNOSDATAT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) #define R0900_P1_NNOSDATAT0 0xf481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) #define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) #define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) #define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) /*P1_NNOSDATA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) #define R0900_P1_NNOSDATA1 0xf482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) #define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) #define F0900_P1_NOSDATA_NORMED1 0xf48200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) /*P1_NNOSDATA0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) #define R0900_P1_NNOSDATA0 0xf483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) #define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) #define F0900_P1_NOSDATA_NORMED0 0xf48300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) /*P1_NNOSPLHT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) #define R0900_P1_NNOSPLHT1 0xf484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) #define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) #define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) #define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) /*P1_NNOSPLHT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) #define R0900_P1_NNOSPLHT0 0xf485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) #define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) #define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) #define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) /*P1_NNOSPLH1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) #define R0900_P1_NNOSPLH1 0xf486
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) #define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #define F0900_P1_NOSPLH_NORMED1 0xf48600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) /*P1_NNOSPLH0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) #define R0900_P1_NNOSPLH0 0xf487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) #define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) #define F0900_P1_NOSPLH_NORMED0 0xf48700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /*P1_NOSDATAT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) #define R0900_P1_NOSDATAT1 0xf488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) #define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) #define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) /*P1_NOSDATAT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) #define R0900_P1_NOSDATAT0 0xf489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) #define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) #define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /*P1_NOSDATA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) #define R0900_P1_NOSDATA1 0xf48a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) #define NOSDATA1 REGx(R0900_P1_NOSDATA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) #define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) /*P1_NOSDATA0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) #define R0900_P1_NOSDATA0 0xf48b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) #define NOSDATA0 REGx(R0900_P1_NOSDATA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) #define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /*P1_NOSPLHT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) #define R0900_P1_NOSPLHT1 0xf48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) #define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) #define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) /*P1_NOSPLHT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) #define R0900_P1_NOSPLHT0 0xf48d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) #define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) #define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) /*P1_NOSPLH1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) #define R0900_P1_NOSPLH1 0xf48e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) #define NOSPLH1 REGx(R0900_P1_NOSPLH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) #define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /*P1_NOSPLH0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) #define R0900_P1_NOSPLH0 0xf48f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #define NOSPLH0 REGx(R0900_P1_NOSPLH0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) /*P1_CAR2CFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) #define R0900_P1_CAR2CFG 0xf490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) #define CAR2CFG REGx(R0900_P1_CAR2CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define F0900_P1_CARRIER3_DISABLE 0xf4900040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) #define F0900_P1_ROTA2ON 0xf4900004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) #define F0900_P1_PH_DET_ALGO2 0xf4900003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) /*P1_CFR2CFR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) #define R0900_P1_CFR2CFR1 0xf491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) #define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) #define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #define F0900_P1_EN_S2CAR2CENTER 0xf4910020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #define F0900_P1_DIS_BCHERRCFR2 0xf4910010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) #define F0900_P1_CFR2TOCFR1_BETA 0xf4910007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) /*P1_CFR22*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) #define R0900_P1_CFR22 0xf493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) #define CFR22 REGx(R0900_P1_CFR22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) #define F0900_P1_CAR2_FREQ2 0xf49301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) /*P1_CFR21*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) #define R0900_P1_CFR21 0xf494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) #define CFR21 REGx(R0900_P1_CFR21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) #define F0900_P1_CAR2_FREQ1 0xf49400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) /*P1_CFR20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #define R0900_P1_CFR20 0xf495
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) #define CFR20 REGx(R0900_P1_CFR20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) #define F0900_P1_CAR2_FREQ0 0xf49500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) /*P1_ACLC2S2Q*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) #define R0900_P1_ACLC2S2Q 0xf497
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) #define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) #define F0900_P1_ENAB_SPSKSYMB 0xf4970080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) #define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) #define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) /*P1_ACLC2S28*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) #define R0900_P1_ACLC2S28 0xf498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) #define ACLC2S28 REGx(R0900_P1_ACLC2S28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) #define F0900_P1_OLDI3Q_MODE 0xf4980080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) #define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) #define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /*P1_ACLC2S216A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) #define R0900_P1_ACLC2S216A 0xf499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) #define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) #define F0900_P1_DIS_C3STOPA2 0xf4990080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) #define F0900_P1_CAR2S2_16ADERAT 0xf4990040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) #define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) #define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) /*P1_ACLC2S232A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) #define R0900_P1_ACLC2S232A 0xf49a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) #define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) #define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) #define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) #define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) /*P1_BCLC2S2Q*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) #define R0900_P1_BCLC2S2Q 0xf49c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) #define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) #define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) #define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) /*P1_BCLC2S28*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) #define R0900_P1_BCLC2S28 0xf49d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) #define BCLC2S28 REGx(R0900_P1_BCLC2S28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) #define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) #define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /*P1_BCLC2S216A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #define R0900_P1_BCLC2S216A 0xf49e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) #define BCLC2S216A REGx(R0900_P1_BCLC2S216A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /*P1_BCLC2S232A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) #define R0900_P1_BCLC2S232A 0xf49f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) #define BCLC2S232A REGx(R0900_P1_BCLC2S232A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) /*P1_PLROOT2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) #define R0900_P1_PLROOT2 0xf4ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) #define PLROOT2 REGx(R0900_P1_PLROOT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) #define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) #define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) /*P1_PLROOT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #define R0900_P1_PLROOT1 0xf4ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #define PLROOT1 REGx(R0900_P1_PLROOT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) #define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) /*P1_PLROOT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) #define R0900_P1_PLROOT0 0xf4ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) #define PLROOT0 REGx(R0900_P1_PLROOT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) #define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) /*P1_MODCODLST0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) #define R0900_P1_MODCODLST0 0xf4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) #define MODCODLST0 REGx(R0900_P1_MODCODLST0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /*P1_MODCODLST1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) #define R0900_P1_MODCODLST1 0xf4b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) #define MODCODLST1 REGx(R0900_P1_MODCODLST1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) #define F0900_P1_DIS_MODCOD29 0xf4b100f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) #define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) /*P1_MODCODLST2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) #define R0900_P1_MODCODLST2 0xf4b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) #define MODCODLST2 REGx(R0900_P1_MODCODLST2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) #define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) #define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /*P1_MODCODLST3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) #define R0900_P1_MODCODLST3 0xf4b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) #define MODCODLST3 REGx(R0900_P1_MODCODLST3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) #define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) #define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /*P1_MODCODLST4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) #define R0900_P1_MODCODLST4 0xf4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) #define MODCODLST4 REGx(R0900_P1_MODCODLST4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) #define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) #define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /*P1_MODCODLST5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) #define R0900_P1_MODCODLST5 0xf4b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) #define MODCODLST5 REGx(R0900_P1_MODCODLST5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) #define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) #define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) /*P1_MODCODLST6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) #define R0900_P1_MODCODLST6 0xf4b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) #define MODCODLST6 REGx(R0900_P1_MODCODLST6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) #define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) #define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) /*P1_MODCODLST7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) #define R0900_P1_MODCODLST7 0xf4b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) #define MODCODLST7 REGx(R0900_P1_MODCODLST7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) #define F0900_P1_DIS_8P_9_10 0xf4b700f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define F0900_P1_DIS_8P_8_9 0xf4b7000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) /*P1_MODCODLST8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define R0900_P1_MODCODLST8 0xf4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) #define MODCODLST8 REGx(R0900_P1_MODCODLST8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) #define F0900_P1_DIS_8P_5_6 0xf4b800f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) #define F0900_P1_DIS_8P_3_4 0xf4b8000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) /*P1_MODCODLST9*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) #define R0900_P1_MODCODLST9 0xf4b9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) #define MODCODLST9 REGx(R0900_P1_MODCODLST9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) #define F0900_P1_DIS_8P_2_3 0xf4b900f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) #define F0900_P1_DIS_8P_3_5 0xf4b9000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) /*P1_MODCODLSTA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) #define R0900_P1_MODCODLSTA 0xf4ba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) #define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) #define F0900_P1_DIS_QP_9_10 0xf4ba00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) #define F0900_P1_DIS_QP_8_9 0xf4ba000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) /*P1_MODCODLSTB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) #define R0900_P1_MODCODLSTB 0xf4bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) #define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) #define F0900_P1_DIS_QP_5_6 0xf4bb00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) #define F0900_P1_DIS_QP_4_5 0xf4bb000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /*P1_MODCODLSTC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) #define R0900_P1_MODCODLSTC 0xf4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) #define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) #define F0900_P1_DIS_QP_3_4 0xf4bc00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) #define F0900_P1_DIS_QP_2_3 0xf4bc000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) /*P1_MODCODLSTD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) #define R0900_P1_MODCODLSTD 0xf4bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) #define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) #define F0900_P1_DIS_QP_3_5 0xf4bd00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) #define F0900_P1_DIS_QP_1_2 0xf4bd000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) /*P1_MODCODLSTE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) #define R0900_P1_MODCODLSTE 0xf4be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) #define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) #define F0900_P1_DIS_QP_2_5 0xf4be00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) #define F0900_P1_DIS_QP_1_3 0xf4be000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /*P1_MODCODLSTF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) #define R0900_P1_MODCODLSTF 0xf4bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) #define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) #define F0900_P1_DIS_QP_1_4 0xf4bf00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) /*P1_GAUSSR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) #define R0900_P1_GAUSSR0 0xf4c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) #define GAUSSR0 REGx(R0900_P1_GAUSSR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) #define F0900_P1_EN_CCIMODE 0xf4c00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) #define F0900_P1_R0_GAUSSIEN 0xf4c0007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /*P1_CCIR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) #define R0900_P1_CCIR0 0xf4c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) #define CCIR0 REGx(R0900_P1_CCIR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) #define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) #define F0900_P1_R0_CCI 0xf4c1007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) /*P1_CCIQUANT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) #define R0900_P1_CCIQUANT 0xf4c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) #define CCIQUANT REGx(R0900_P1_CCIQUANT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) #define F0900_P1_CCI_BETA 0xf4c200e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) #define F0900_P1_CCI_QUANT 0xf4c2001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) /*P1_CCITHRES*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) #define R0900_P1_CCITHRES 0xf4c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) #define CCITHRES REGx(R0900_P1_CCITHRES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) #define F0900_P1_CCI_THRESHOLD 0xf4c300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) /*P1_CCIACC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) #define R0900_P1_CCIACC 0xf4c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) #define CCIACC REGx(R0900_P1_CCIACC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) #define F0900_P1_CCI_VALUE 0xf4c400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /*P1_DMDRESCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) #define R0900_P1_DMDRESCFG 0xf4c6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) #define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) #define F0900_P1_DMDRES_RESET 0xf4c60080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) #define F0900_P1_DMDRES_STRALL 0xf4c60008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) #define F0900_P1_DMDRES_NEWONLY 0xf4c60004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) #define F0900_P1_DMDRES_NOSTORE 0xf4c60002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) /*P1_DMDRESADR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) #define R0900_P1_DMDRESADR 0xf4c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) #define DMDRESADR REGx(R0900_P1_DMDRESADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) #define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) #define F0900_P1_DMDRES_MEMFULL 0xf4c70030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) #define F0900_P1_DMDRES_RESNBR 0xf4c7000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) /*P1_DMDRESDATA7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) #define R0900_P1_DMDRESDATA7 0xf4c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) #define F0900_P1_DMDRES_DATA7 0xf4c800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) /*P1_DMDRESDATA6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) #define R0900_P1_DMDRESDATA6 0xf4c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) #define F0900_P1_DMDRES_DATA6 0xf4c900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) /*P1_DMDRESDATA5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) #define R0900_P1_DMDRESDATA5 0xf4ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) #define F0900_P1_DMDRES_DATA5 0xf4ca00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /*P1_DMDRESDATA4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) #define R0900_P1_DMDRESDATA4 0xf4cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) #define F0900_P1_DMDRES_DATA4 0xf4cb00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) /*P1_DMDRESDATA3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) #define R0900_P1_DMDRESDATA3 0xf4cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) #define F0900_P1_DMDRES_DATA3 0xf4cc00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) /*P1_DMDRESDATA2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) #define R0900_P1_DMDRESDATA2 0xf4cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) #define F0900_P1_DMDRES_DATA2 0xf4cd00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) /*P1_DMDRESDATA1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #define R0900_P1_DMDRESDATA1 0xf4ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) #define F0900_P1_DMDRES_DATA1 0xf4ce00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /*P1_DMDRESDATA0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) #define R0900_P1_DMDRESDATA0 0xf4cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #define F0900_P1_DMDRES_DATA0 0xf4cf00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) /*P1_FFEI1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) #define R0900_P1_FFEI1 0xf4d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) #define FFEI1 REGx(R0900_P1_FFEI1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) #define F0900_P1_FFE_ACCI1 0xf4d001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /*P1_FFEQ1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) #define R0900_P1_FFEQ1 0xf4d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) #define FFEQ1 REGx(R0900_P1_FFEQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #define F0900_P1_FFE_ACCQ1 0xf4d101ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) /*P1_FFEI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) #define R0900_P1_FFEI2 0xf4d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) #define FFEI2 REGx(R0900_P1_FFEI2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) #define F0900_P1_FFE_ACCI2 0xf4d201ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) /*P1_FFEQ2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) #define R0900_P1_FFEQ2 0xf4d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) #define FFEQ2 REGx(R0900_P1_FFEQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) #define F0900_P1_FFE_ACCQ2 0xf4d301ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) /*P1_FFEI3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #define R0900_P1_FFEI3 0xf4d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) #define FFEI3 REGx(R0900_P1_FFEI3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) #define F0900_P1_FFE_ACCI3 0xf4d401ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /*P1_FFEQ3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) #define R0900_P1_FFEQ3 0xf4d5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) #define FFEQ3 REGx(R0900_P1_FFEQ3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) #define F0900_P1_FFE_ACCQ3 0xf4d501ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) /*P1_FFEI4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) #define R0900_P1_FFEI4 0xf4d6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) #define FFEI4 REGx(R0900_P1_FFEI4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) #define F0900_P1_FFE_ACCI4 0xf4d601ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) /*P1_FFEQ4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) #define R0900_P1_FFEQ4 0xf4d7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) #define FFEQ4 REGx(R0900_P1_FFEQ4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) #define F0900_P1_FFE_ACCQ4 0xf4d701ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) /*P1_FFECFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) #define R0900_P1_FFECFG 0xf4d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) #define FFECFG REGx(R0900_P1_FFECFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) #define F0900_P1_EQUALFFE_ON 0xf4d80040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) #define F0900_P1_MU_EQUALFFE 0xf4d80007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) /*P1_TNRCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) #define R0900_P1_TNRCFG 0xf4e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) #define TNRCFG REGx(R0900_P1_TNRCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) #define F0900_P1_TUN_ACKFAIL 0xf4e00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) #define F0900_P1_TUN_TYPE 0xf4e00070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) #define F0900_P1_TUN_SECSTOP 0xf4e00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) #define F0900_P1_TUN_VCOSRCH 0xf4e00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) #define F0900_P1_TUN_MADDRESS 0xf4e00003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) /*P1_TNRCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) #define R0900_P1_TNRCFG2 0xf4e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) #define TNRCFG2 REGx(R0900_P1_TNRCFG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) #define F0900_P1_TUN_IQSWAP 0xf4e10080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) #define F0900_P1_DIS_BWCALC 0xf4e10004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) #define F0900_P1_SHORT_WAITSTATES 0xf4e10002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) /*P1_TNRXTAL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) #define R0900_P1_TNRXTAL 0xf4e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) #define TNRXTAL REGx(R0900_P1_TNRXTAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) #define F0900_P1_TUN_XTALFREQ 0xf4e4001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) /*P1_TNRSTEPS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) #define R0900_P1_TNRSTEPS 0xf4e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) #define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) #define F0900_P1_TUNER_BW0P125 0xf4e70080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) #define F0900_P1_BWINC_OFFSET 0xf4e70170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) #define F0900_P1_SOFTSTEP_RNG 0xf4e70008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) #define F0900_P1_TUN_BWOFFSET 0xf4e70007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /*P1_TNRGAIN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) #define R0900_P1_TNRGAIN 0xf4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) #define TNRGAIN REGx(R0900_P1_TNRGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) #define F0900_P1_TUN_KDIVEN 0xf4e800c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) #define F0900_P1_STB6X00_OCK 0xf4e80030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) #define F0900_P1_TUN_GAIN 0xf4e8000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) /*P1_TNRRF1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) #define R0900_P1_TNRRF1 0xf4e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) #define TNRRF1 REGx(R0900_P1_TNRRF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) #define F0900_P1_TUN_RFFREQ2 0xf4e900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) #define TUN_RFFREQ2 FLDx(F0900_P1_TUN_RFFREQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) /*P1_TNRRF0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) #define R0900_P1_TNRRF0 0xf4ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) #define TNRRF0 REGx(R0900_P1_TNRRF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) #define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) #define TUN_RFFREQ1 FLDx(F0900_P1_TUN_RFFREQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) /*P1_TNRBW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) #define R0900_P1_TNRBW 0xf4eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) #define TNRBW REGx(R0900_P1_TNRBW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) #define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) #define TUN_RFFREQ0 FLDx(F0900_P1_TUN_RFFREQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) #define F0900_P1_TUN_BW 0xf4eb003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) #define TUN_BW FLDx(F0900_P1_TUN_BW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) /*P1_TNRADJ*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) #define R0900_P1_TNRADJ 0xf4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) #define TNRADJ REGx(R0900_P1_TNRADJ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) #define F0900_P1_STB61X0_CALTIME 0xf4ec0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) /*P1_TNRCTL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) #define R0900_P1_TNRCTL2 0xf4ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) #define TNRCTL2 REGx(R0900_P1_TNRCTL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) #define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) #define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) #define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) #define F0900_P1_STB61X0_CALOFF 0xf4ed0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) #define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) #define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) #define F0900_P1_STB6XX0_SYN 0xf4ed0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) /*P1_TNRCFG3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) #define R0900_P1_TNRCFG3 0xf4ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) #define TNRCFG3 REGx(R0900_P1_TNRCFG3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) #define F0900_P1_TUN_PLLFREQ 0xf4ee001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) #define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) /*P1_TNRLAUNCH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) #define R0900_P1_TNRLAUNCH 0xf4f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) #define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /*P1_TNRLD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) #define R0900_P1_TNRLD 0xf4f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) #define TNRLD REGx(R0900_P1_TNRLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) #define F0900_P1_TUNLD_VCOING 0xf4f00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) #define F0900_P1_TUN_REG1FAIL 0xf4f00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) #define F0900_P1_TUN_REG2FAIL 0xf4f00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) #define F0900_P1_TUN_REG3FAIL 0xf4f00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) #define F0900_P1_TUN_REG4FAIL 0xf4f00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) #define F0900_P1_TUN_REG5FAIL 0xf4f00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) #define F0900_P1_TUN_BWING 0xf4f00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) #define F0900_P1_TUN_LOCKED 0xf4f00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) /*P1_TNROBSL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) #define R0900_P1_TNROBSL 0xf4f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) #define TNROBSL REGx(R0900_P1_TNROBSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) #define F0900_P1_TUN_I2CABORTED 0xf4f60080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) #define F0900_P1_TUN_LPEN 0xf4f60040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) #define F0900_P1_TUN_FCCK 0xf4f60020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) #define F0900_P1_TUN_I2CLOCKED 0xf4f60010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) #define F0900_P1_TUN_PROGDONE 0xf4f6000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) #define F0900_P1_TUN_RFRESTE1 0xf4f60003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) #define TUN_RFRESTE1 FLDx(F0900_P1_TUN_RFRESTE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) /*P1_TNRRESTE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) #define R0900_P1_TNRRESTE 0xf4f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) #define TNRRESTE REGx(R0900_P1_TNRRESTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) #define F0900_P1_TUN_RFRESTE0 0xf4f700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) #define TUN_RFRESTE0 FLDx(F0900_P1_TUN_RFRESTE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /*P1_SMAPCOEF7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) #define R0900_P1_SMAPCOEF7 0xf500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) #define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) #define F0900_P1_DIS_QSCALE 0xf5000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) #define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) /*P1_SMAPCOEF6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) #define R0900_P1_SMAPCOEF6 0xf501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) #define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) #define F0900_P1_ADJ_8PSKLLR1 0xf5010004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) #define F0900_P1_OLD_8PSKLLR1 0xf5010002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) #define F0900_P1_DIS_AB8PSK 0xf5010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /*P1_SMAPCOEF5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) #define R0900_P1_SMAPCOEF5 0xf502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) #define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) #define F0900_P1_DIS_8SCALE 0xf5020080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) #define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) /*P1_NCO2MAX1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) #define R0900_P1_NCO2MAX1 0xf514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) #define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) #define F0900_P1_TETA2_MAXVABS1 0xf51400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /*P1_NCO2MAX0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) #define R0900_P1_NCO2MAX0 0xf515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) #define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) #define F0900_P1_TETA2_MAXVABS0 0xf51500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) /*P1_NCO2FR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) #define R0900_P1_NCO2FR1 0xf516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) #define NCO2FR1 REGx(R0900_P1_NCO2FR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) #define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /*P1_NCO2FR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) #define R0900_P1_NCO2FR0 0xf517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) #define NCO2FR0 REGx(R0900_P1_NCO2FR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) #define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) /*P1_CFR2AVRGE1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) #define R0900_P1_CFR2AVRGE1 0xf518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) #define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) #define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /*P1_CFR2AVRGE0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) #define R0900_P1_CFR2AVRGE0 0xf519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) #define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) #define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) /*P1_DMDPLHSTAT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) #define R0900_P1_DMDPLHSTAT 0xf520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) #define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) #define F0900_P1_PLH_STATISTIC 0xf52000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) /*P1_LOCKTIME3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) #define R0900_P1_LOCKTIME3 0xf522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) #define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) #define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /*P1_LOCKTIME2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) #define R0900_P1_LOCKTIME2 0xf523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) #define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) #define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) /*P1_LOCKTIME1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) #define R0900_P1_LOCKTIME1 0xf524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) #define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) #define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) /*P1_LOCKTIME0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) #define R0900_P1_LOCKTIME0 0xf525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) #define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) #define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) /*P1_VITSCALE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) #define R0900_P1_VITSCALE 0xf532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) #define VITSCALE REGx(R0900_P1_VITSCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) #define F0900_P1_NVTH_NOSRANGE 0xf5320080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) #define F0900_P1_VERROR_MAXMODE 0xf5320040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) #define F0900_P1_NSLOWSN_LOCKED 0xf5320008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) #define F0900_P1_DIS_RSFLOCK 0xf5320002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) /*P1_FECM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) #define R0900_P1_FECM 0xf533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) #define FECM REGx(R0900_P1_FECM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) #define F0900_P1_DSS_DVB 0xf5330080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) #define DSS_DVB FLDx(F0900_P1_DSS_DVB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) #define F0900_P1_DSS_SRCH 0xf5330010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) #define F0900_P1_SYNCVIT 0xf5330002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) #define F0900_P1_IQINV 0xf5330001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #define IQINV FLDx(F0900_P1_IQINV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /*P1_VTH12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) #define R0900_P1_VTH12 0xf534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) #define VTH12 REGx(R0900_P1_VTH12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) #define F0900_P1_VTH12 0xf53400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) /*P1_VTH23*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) #define R0900_P1_VTH23 0xf535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) #define VTH23 REGx(R0900_P1_VTH23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) #define F0900_P1_VTH23 0xf53500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) /*P1_VTH34*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) #define R0900_P1_VTH34 0xf536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) #define VTH34 REGx(R0900_P1_VTH34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) #define F0900_P1_VTH34 0xf53600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) /*P1_VTH56*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) #define R0900_P1_VTH56 0xf537
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) #define VTH56 REGx(R0900_P1_VTH56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) #define F0900_P1_VTH56 0xf53700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) /*P1_VTH67*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) #define R0900_P1_VTH67 0xf538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) #define VTH67 REGx(R0900_P1_VTH67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) #define F0900_P1_VTH67 0xf53800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) /*P1_VTH78*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) #define R0900_P1_VTH78 0xf539
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) #define VTH78 REGx(R0900_P1_VTH78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) #define F0900_P1_VTH78 0xf53900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /*P1_VITCURPUN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) #define R0900_P1_VITCURPUN 0xf53a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) #define VITCURPUN REGx(R0900_P1_VITCURPUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) #define F0900_P1_VIT_CURPUN 0xf53a001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) #define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) /*P1_VERROR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) #define R0900_P1_VERROR 0xf53b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) #define VERROR REGx(R0900_P1_VERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) #define F0900_P1_REGERR_VIT 0xf53b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) /*P1_PRVIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) #define R0900_P1_PRVIT 0xf53c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) #define PRVIT REGx(R0900_P1_PRVIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) #define F0900_P1_DIS_VTHLOCK 0xf53c0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) #define F0900_P1_E7_8VIT 0xf53c0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) #define F0900_P1_E6_7VIT 0xf53c0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) #define F0900_P1_E5_6VIT 0xf53c0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) #define F0900_P1_E3_4VIT 0xf53c0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) #define F0900_P1_E2_3VIT 0xf53c0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) #define F0900_P1_E1_2VIT 0xf53c0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) /*P1_VAVSRVIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) #define R0900_P1_VAVSRVIT 0xf53d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) #define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) #define F0900_P1_AMVIT 0xf53d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) #define F0900_P1_FROZENVIT 0xf53d0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) #define F0900_P1_SNVIT 0xf53d0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) #define F0900_P1_TOVVIT 0xf53d000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) #define F0900_P1_HYPVIT 0xf53d0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) /*P1_VSTATUSVIT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) #define R0900_P1_VSTATUSVIT 0xf53e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) #define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) #define F0900_P1_PRFVIT 0xf53e0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) #define PRFVIT FLDx(F0900_P1_PRFVIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) #define F0900_P1_LOCKEDVIT 0xf53e0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) #define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) /*P1_VTHINUSE*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) #define R0900_P1_VTHINUSE 0xf53f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) #define VTHINUSE REGx(R0900_P1_VTHINUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) #define F0900_P1_VIT_INUSE 0xf53f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) /*P1_KDIV12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) #define R0900_P1_KDIV12 0xf540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) #define KDIV12 REGx(R0900_P1_KDIV12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) #define F0900_P1_K_DIVIDER_12 0xf540007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) /*P1_KDIV23*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) #define R0900_P1_KDIV23 0xf541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) #define KDIV23 REGx(R0900_P1_KDIV23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) #define F0900_P1_K_DIVIDER_23 0xf541007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) /*P1_KDIV34*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) #define R0900_P1_KDIV34 0xf542
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) #define KDIV34 REGx(R0900_P1_KDIV34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) #define F0900_P1_K_DIVIDER_34 0xf542007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) /*P1_KDIV56*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) #define R0900_P1_KDIV56 0xf543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) #define KDIV56 REGx(R0900_P1_KDIV56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) #define F0900_P1_K_DIVIDER_56 0xf543007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) /*P1_KDIV67*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) #define R0900_P1_KDIV67 0xf544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) #define KDIV67 REGx(R0900_P1_KDIV67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) #define F0900_P1_K_DIVIDER_67 0xf544007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) /*P1_KDIV78*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) #define R0900_P1_KDIV78 0xf545
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) #define KDIV78 REGx(R0900_P1_KDIV78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) #define F0900_P1_K_DIVIDER_78 0xf545007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) /*P1_PDELCTRL1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) #define R0900_P1_PDELCTRL1 0xf550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) #define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) #define F0900_P1_INV_MISMASK 0xf5500080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) #define INV_MISMASK FLDx(F0900_P1_INV_MISMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) #define F0900_P1_FILTER_EN 0xf5500020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) #define FILTER_EN FLDx(F0900_P1_FILTER_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) #define F0900_P1_EN_MIS00 0xf5500002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) #define EN_MIS00 FLDx(F0900_P1_EN_MIS00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) #define F0900_P1_ALGOSWRST 0xf5500001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) #define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) /*P1_PDELCTRL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) #define R0900_P1_PDELCTRL2 0xf551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) #define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) #define F0900_P1_RESET_UPKO_COUNT 0xf5510040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) #define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) #define F0900_P1_FRAME_MODE 0xf5510002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) #define F0900_P1_NOBCHERRFLG_USE 0xf5510001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) /*P1_HYSTTHRESH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) #define R0900_P1_HYSTTHRESH 0xf554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) #define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) #define F0900_P1_UNLCK_THRESH 0xf55400f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) #define F0900_P1_DELIN_LCK_THRESH 0xf554000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) /*P1_ISIENTRY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) #define R0900_P1_ISIENTRY 0xf55e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) #define ISIENTRY REGx(R0900_P1_ISIENTRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) #define F0900_P1_ISI_ENTRY 0xf55e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) /*P1_ISIBITENA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) #define R0900_P1_ISIBITENA 0xf55f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) #define ISIBITENA REGx(R0900_P1_ISIBITENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) #define F0900_P1_ISI_BIT_EN 0xf55f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) /*P1_MATSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) #define R0900_P1_MATSTR1 0xf560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) #define MATSTR1 REGx(R0900_P1_MATSTR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) #define F0900_P1_MATYPE_CURRENT1 0xf56000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) /*P1_MATSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) #define R0900_P1_MATSTR0 0xf561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) #define MATSTR0 REGx(R0900_P1_MATSTR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) #define F0900_P1_MATYPE_CURRENT0 0xf56100ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) /*P1_UPLSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) #define R0900_P1_UPLSTR1 0xf562
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) #define UPLSTR1 REGx(R0900_P1_UPLSTR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) #define F0900_P1_UPL_CURRENT1 0xf56200ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) /*P1_UPLSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) #define R0900_P1_UPLSTR0 0xf563
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) #define UPLSTR0 REGx(R0900_P1_UPLSTR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) #define F0900_P1_UPL_CURRENT0 0xf56300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) /*P1_DFLSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) #define R0900_P1_DFLSTR1 0xf564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) #define DFLSTR1 REGx(R0900_P1_DFLSTR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) #define F0900_P1_DFL_CURRENT1 0xf56400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) /*P1_DFLSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) #define R0900_P1_DFLSTR0 0xf565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) #define DFLSTR0 REGx(R0900_P1_DFLSTR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) #define F0900_P1_DFL_CURRENT0 0xf56500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /*P1_SYNCSTR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) #define R0900_P1_SYNCSTR 0xf566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) #define SYNCSTR REGx(R0900_P1_SYNCSTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) #define F0900_P1_SYNC_CURRENT 0xf56600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) /*P1_SYNCDSTR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) #define R0900_P1_SYNCDSTR1 0xf567
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) #define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) #define F0900_P1_SYNCD_CURRENT1 0xf56700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) /*P1_SYNCDSTR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) #define R0900_P1_SYNCDSTR0 0xf568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) #define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) #define F0900_P1_SYNCD_CURRENT0 0xf56800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) /*P1_PDELSTATUS1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) #define R0900_P1_PDELSTATUS1 0xf569
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) #define F0900_P1_PKTDELIN_DELOCK 0xf5690080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) #define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) #define F0900_P1_CONTINUOUS_STREAM 0xf5690020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) #define F0900_P1_UNACCEPTED_STREAM 0xf5690010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) #define F0900_P1_BCH_ERROR_FLAG 0xf5690008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) #define F0900_P1_PKTDELIN_LOCK 0xf5690002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) #define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) #define F0900_P1_FIRST_LOCK 0xf5690001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) /*P1_PDELSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) #define R0900_P1_PDELSTATUS2 0xf56a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) #define F0900_P1_FRAME_MODCOD 0xf56a007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) #define F0900_P1_FRAME_TYPE 0xf56a0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) /*P1_BBFCRCKO1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) #define R0900_P1_BBFCRCKO1 0xf56b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) #define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) #define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) /*P1_BBFCRCKO0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) #define R0900_P1_BBFCRCKO0 0xf56c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) #define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) #define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /*P1_UPCRCKO1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) #define R0900_P1_UPCRCKO1 0xf56d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) #define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) #define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) /*P1_UPCRCKO0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) #define R0900_P1_UPCRCKO0 0xf56e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) #define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) #define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) /*P1_PDELCTRL3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) #define R0900_P1_PDELCTRL3 0xf56f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) #define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) #define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) #define F0900_P1_NOFIFO_BCHERR 0xf56f0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) /*P1_TSSTATEM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) #define R0900_P1_TSSTATEM 0xf570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) #define TSSTATEM REGx(R0900_P1_TSSTATEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) #define F0900_P1_TSDIL_ON 0xf5700080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) #define F0900_P1_TSRS_ON 0xf5700020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) #define F0900_P1_TSDESCRAMB_ON 0xf5700010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) #define F0900_P1_TSFRAME_MODE 0xf5700008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) #define F0900_P1_TS_DISABLE 0xf5700004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) #define F0900_P1_TSOUT_NOSYNC 0xf5700001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) /*P1_TSCFGH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) #define R0900_P1_TSCFGH 0xf572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) #define TSCFGH REGx(R0900_P1_TSCFGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) #define F0900_P1_TSFIFO_DVBCI 0xf5720080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) #define F0900_P1_TSFIFO_SERIAL 0xf5720040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) #define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) #define F0900_P1_TSFIFO_DUTY50 0xf5720010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) #define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) #define F0900_P1_TSFIFO_ERRMODE 0xf5720006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) #define F0900_P1_RST_HWARE 0xf5720001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) #define RST_HWARE FLDx(F0900_P1_RST_HWARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /*P1_TSCFGM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) #define R0900_P1_TSCFGM 0xf573
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) #define TSCFGM REGx(R0900_P1_TSCFGM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) #define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) #define F0900_P1_TSFIFO_PERMDATA 0xf5730020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) #define F0900_P1_TSFIFO_DPUNACT 0xf5730002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) #define F0900_P1_TSFIFO_INVDATA 0xf5730001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) /*P1_TSCFGL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) #define R0900_P1_TSCFGL 0xf574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) #define TSCFGL REGx(R0900_P1_TSCFGL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) #define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) #define F0900_P1_BCHERROR_MODE 0xf5740030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) #define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) #define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) #define F0900_P1_TSFIFO_BITSPEED 0xf5740003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) /*P1_TSINSDELH*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) #define R0900_P1_TSINSDELH 0xf576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) #define TSINSDELH REGx(R0900_P1_TSINSDELH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) #define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) #define F0900_P1_TSDEL_XXHEADER 0xf5760040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) #define F0900_P1_TSDEL_BBHEADER 0xf5760020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) #define F0900_P1_TSDEL_DATAFIELD 0xf5760010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) #define F0900_P1_TSINSDEL_ISCR 0xf5760008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) #define F0900_P1_TSINSDEL_NPD 0xf5760004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) #define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) #define F0900_P1_TSINSDEL_CRC8 0xf5760001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) /*P1_TSDIVN*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) #define R0900_P1_TSDIVN 0xf579
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) #define TSDIVN REGx(R0900_P1_TSDIVN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) #define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) /*P1_TSCFG4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) #define R0900_P1_TSCFG4 0xf57a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) #define TSCFG4 REGx(R0900_P1_TSCFG4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) #define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) /*P1_TSSPEED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) #define R0900_P1_TSSPEED 0xf580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) #define TSSPEED REGx(R0900_P1_TSSPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) #define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) /*P1_TSSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) #define R0900_P1_TSSTATUS 0xf581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) #define TSSTATUS REGx(R0900_P1_TSSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) #define F0900_P1_TSFIFO_LINEOK 0xf5810080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) #define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) #define F0900_P1_TSFIFO_ERROR 0xf5810040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) #define F0900_P1_DIL_READY 0xf5810001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) /*P1_TSSTATUS2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) #define R0900_P1_TSSTATUS2 0xf582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) #define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) #define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) #define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) #define F0900_P1_DILXX_RESET 0xf5820020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) #define F0900_P1_TSSERIAL_IMPOS 0xf5820010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) #define F0900_P1_SCRAMBDETECT 0xf5820002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) /*P1_TSBITRATE1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) #define R0900_P1_TSBITRATE1 0xf583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) #define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) #define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /*P1_TSBITRATE0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) #define R0900_P1_TSBITRATE0 0xf584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) #define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) #define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) /*P1_ERRCTRL1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) #define R0900_P1_ERRCTRL1 0xf598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) #define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) #define F0900_P1_ERR_SOURCE1 0xf59800f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) #define F0900_P1_NUM_EVENT1 0xf5980007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) /*P1_ERRCNT12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) #define R0900_P1_ERRCNT12 0xf599
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) #define ERRCNT12 REGx(R0900_P1_ERRCNT12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) #define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) #define F0900_P1_ERR_CNT12 0xf599007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) #define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) /*P1_ERRCNT11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) #define R0900_P1_ERRCNT11 0xf59a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) #define ERRCNT11 REGx(R0900_P1_ERRCNT11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) #define F0900_P1_ERR_CNT11 0xf59a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) #define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) /*P1_ERRCNT10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) #define R0900_P1_ERRCNT10 0xf59b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) #define ERRCNT10 REGx(R0900_P1_ERRCNT10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) #define F0900_P1_ERR_CNT10 0xf59b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) #define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) /*P1_ERRCTRL2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) #define R0900_P1_ERRCTRL2 0xf59c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) #define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) #define F0900_P1_ERR_SOURCE2 0xf59c00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) #define F0900_P1_NUM_EVENT2 0xf59c0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) /*P1_ERRCNT22*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) #define R0900_P1_ERRCNT22 0xf59d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) #define ERRCNT22 REGx(R0900_P1_ERRCNT22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) #define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) #define F0900_P1_ERR_CNT22 0xf59d007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) #define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) /*P1_ERRCNT21*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) #define R0900_P1_ERRCNT21 0xf59e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) #define ERRCNT21 REGx(R0900_P1_ERRCNT21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) #define F0900_P1_ERR_CNT21 0xf59e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) #define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) /*P1_ERRCNT20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) #define R0900_P1_ERRCNT20 0xf59f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) #define ERRCNT20 REGx(R0900_P1_ERRCNT20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) #define F0900_P1_ERR_CNT20 0xf59f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) #define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) /*P1_FECSPY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) #define R0900_P1_FECSPY 0xf5a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) #define FECSPY REGx(R0900_P1_FECSPY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) #define F0900_P1_SPY_ENABLE 0xf5a00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) #define F0900_P1_NO_SYNCBYTE 0xf5a00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) #define F0900_P1_SERIAL_MODE 0xf5a00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) #define F0900_P1_UNUSUAL_PACKET 0xf5a00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) #define F0900_P1_BERMETER_DATAMODE 0xf5a00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) #define F0900_P1_BERMETER_LMODE 0xf5a00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) #define F0900_P1_BERMETER_RESET 0xf5a00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /*P1_FSPYCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) #define R0900_P1_FSPYCFG 0xf5a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) #define FSPYCFG REGx(R0900_P1_FSPYCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) #define F0900_P1_FECSPY_INPUT 0xf5a100c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) #define F0900_P1_RST_ON_ERROR 0xf5a10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) #define F0900_P1_ONE_SHOT 0xf5a10010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) #define F0900_P1_I2C_MODE 0xf5a1000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) #define F0900_P1_SPY_HYSTERESIS 0xf5a10003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) /*P1_FSPYDATA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) #define R0900_P1_FSPYDATA 0xf5a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) #define FSPYDATA REGx(R0900_P1_FSPYDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) #define F0900_P1_SPY_STUFFING 0xf5a20080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) #define F0900_P1_SPY_CNULLPKT 0xf5a20020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) #define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) /*P1_FSPYOUT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) #define R0900_P1_FSPYOUT 0xf5a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) #define FSPYOUT REGx(R0900_P1_FSPYOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) #define F0900_P1_FSPY_DIRECT 0xf5a30080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) #define F0900_P1_STUFF_MODE 0xf5a30007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) /*P1_FSTATUS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) #define R0900_P1_FSTATUS 0xf5a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) #define FSTATUS REGx(R0900_P1_FSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) #define F0900_P1_SPY_ENDSIM 0xf5a40080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) #define F0900_P1_VALID_SIM 0xf5a40040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) #define F0900_P1_FOUND_SIGNAL 0xf5a40020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) #define F0900_P1_DSS_SYNCBYTE 0xf5a40010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) #define F0900_P1_RESULT_STATE 0xf5a4000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) /*P1_FBERCPT4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) #define R0900_P1_FBERCPT4 0xf5a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) #define FBERCPT4 REGx(R0900_P1_FBERCPT4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) #define F0900_P1_FBERMETER_CPT4 0xf5a800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) /*P1_FBERCPT3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) #define R0900_P1_FBERCPT3 0xf5a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) #define FBERCPT3 REGx(R0900_P1_FBERCPT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) #define F0900_P1_FBERMETER_CPT3 0xf5a900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) /*P1_FBERCPT2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) #define R0900_P1_FBERCPT2 0xf5aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) #define FBERCPT2 REGx(R0900_P1_FBERCPT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) #define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) /*P1_FBERCPT1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) #define R0900_P1_FBERCPT1 0xf5ab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) #define FBERCPT1 REGx(R0900_P1_FBERCPT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) #define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) /*P1_FBERCPT0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) #define R0900_P1_FBERCPT0 0xf5ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) #define FBERCPT0 REGx(R0900_P1_FBERCPT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) #define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) /*P1_FBERERR2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) #define R0900_P1_FBERERR2 0xf5ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) #define FBERERR2 REGx(R0900_P1_FBERERR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) #define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) /*P1_FBERERR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) #define R0900_P1_FBERERR1 0xf5ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) #define FBERERR1 REGx(R0900_P1_FBERERR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) #define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) /*P1_FBERERR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) #define R0900_P1_FBERERR0 0xf5af
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) #define FBERERR0 REGx(R0900_P1_FBERERR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) #define F0900_P1_FBERMETER_ERR0 0xf5af00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) /*P1_FSPYBER*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) #define R0900_P1_FSPYBER 0xf5b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) #define FSPYBER REGx(R0900_P1_FSPYBER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) #define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) #define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) #define F0900_P1_FSPYBER_CTIME 0xf5b20007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) /*RCCFG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) #define R0900_RCCFG2 0xf600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) /*TSGENERAL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) #define R0900_TSGENERAL 0xf630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) #define F0900_TSFIFO_DISTS2PAR 0xf6300040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) #define F0900_MUXSTREAM_OUTMODE 0xf6300008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) #define F0900_TSFIFO_PERMPARAL 0xf6300006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) /*TSGENERAL1X*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) #define R0900_TSGENERAL1X 0xf670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) /*NBITER_NF4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) #define R0900_NBITER_NF4 0xfa03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) #define F0900_NBITER_NF_QP_1_2 0xfa0300ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) /*NBITER_NF5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) #define R0900_NBITER_NF5 0xfa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) #define F0900_NBITER_NF_QP_3_5 0xfa0400ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) /*NBITER_NF6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) #define R0900_NBITER_NF6 0xfa05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) #define F0900_NBITER_NF_QP_2_3 0xfa0500ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) /*NBITER_NF7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) #define R0900_NBITER_NF7 0xfa06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) #define F0900_NBITER_NF_QP_3_4 0xfa0600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) /*NBITER_NF8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) #define R0900_NBITER_NF8 0xfa07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) #define F0900_NBITER_NF_QP_4_5 0xfa0700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) /*NBITER_NF9*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) #define R0900_NBITER_NF9 0xfa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) #define F0900_NBITER_NF_QP_5_6 0xfa0800ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) /*NBITER_NF10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) #define R0900_NBITER_NF10 0xfa09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) #define F0900_NBITER_NF_QP_8_9 0xfa0900ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) /*NBITER_NF11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) #define R0900_NBITER_NF11 0xfa0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) #define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) /*NBITER_NF12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) #define R0900_NBITER_NF12 0xfa0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) #define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) /*NBITER_NF13*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) #define R0900_NBITER_NF13 0xfa0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) #define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) /*NBITER_NF14*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) #define R0900_NBITER_NF14 0xfa0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) #define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) /*NBITER_NF15*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) #define R0900_NBITER_NF15 0xfa0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) #define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) /*NBITER_NF16*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) #define R0900_NBITER_NF16 0xfa0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) #define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) /*NBITER_NF17*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) #define R0900_NBITER_NF17 0xfa10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) #define F0900_NBITER_NF_8P_9_10 0xfa1000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) /*NBITERNOERR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) #define R0900_NBITERNOERR 0xfa3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) #define F0900_NBITER_STOP_CRIT 0xfa3f000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) /*GAINLLR_NF4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) #define R0900_GAINLLR_NF4 0xfa43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) #define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) /*GAINLLR_NF5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) #define R0900_GAINLLR_NF5 0xfa44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) #define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) /*GAINLLR_NF6*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) #define R0900_GAINLLR_NF6 0xfa45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) #define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) /*GAINLLR_NF7*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) #define R0900_GAINLLR_NF7 0xfa46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) #define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) /*GAINLLR_NF8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) #define R0900_GAINLLR_NF8 0xfa47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) #define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) /*GAINLLR_NF9*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) #define R0900_GAINLLR_NF9 0xfa48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) #define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) /*GAINLLR_NF10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) #define R0900_GAINLLR_NF10 0xfa49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) #define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) /*GAINLLR_NF11*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) #define R0900_GAINLLR_NF11 0xfa4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) #define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) /*GAINLLR_NF12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) #define R0900_GAINLLR_NF12 0xfa4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) #define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) /*GAINLLR_NF13*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) #define R0900_GAINLLR_NF13 0xfa4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) #define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) /*GAINLLR_NF14*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) #define R0900_GAINLLR_NF14 0xfa4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) #define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) /*GAINLLR_NF15*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) #define R0900_GAINLLR_NF15 0xfa4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) #define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) /*GAINLLR_NF16*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) #define R0900_GAINLLR_NF16 0xfa4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) #define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) /*GAINLLR_NF17*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) #define R0900_GAINLLR_NF17 0xfa50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) #define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) /*CFGEXT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) #define R0900_CFGEXT 0xfa80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) #define F0900_STAGMODE 0xfa800080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) #define F0900_BYPBCH 0xfa800040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) #define F0900_BYPLDPC 0xfa800020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) #define F0900_LDPCMODE 0xfa800010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) #define F0900_INVLLRSIGN 0xfa800008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) #define F0900_SHORTMULT 0xfa800004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) #define F0900_EXTERNTX 0xfa800001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) /*GENCFG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) #define R0900_GENCFG 0xfa86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) #define F0900_BROADCAST 0xfa860010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) #define F0900_PRIORITY 0xfa860002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) #define F0900_DDEMOD 0xfa860001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) /*LDPCERR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) #define R0900_LDPCERR1 0xfa96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) #define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) /*LDPCERR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) #define R0900_LDPCERR0 0xfa97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) #define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) /*BCHERR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) #define R0900_BCHERR 0xfa98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) #define F0900_ERRORFLAG 0xfa980010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) #define F0900_BCH_ERRORS_COUNTER 0xfa98000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) /*TSTRES0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) #define R0900_TSTRES0 0xff11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) #define F0900_FRESFEC 0xff110080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) /*P2_TCTL4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) #define R0900_P2_TCTL4 0xff28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) #define F0900_P2_PN4_SELECT 0xff280020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) /*P1_TCTL4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) #define R0900_P1_TCTL4 0xff48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) #define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) #define F0900_P1_PN4_SELECT 0xff480020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) /*P2_TSTDISRX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) #define R0900_P2_TSTDISRX 0xff65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) #define F0900_P2_PIN_SELECT1 0xff650008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) /*P1_TSTDISRX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) #define R0900_P1_TSTDISRX 0xff67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) #define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) #define F0900_P1_PIN_SELECT1 0xff670008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) #define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) #define STV0900_NBREGS 723
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) #define STV0900_NBFIELDS 1420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970)