^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * stv0367.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) ST Microelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2010,2011 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/dvb_math.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "stv0367.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "stv0367_defs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "stv0367_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "stv0367_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Max transfer size done by I2C transfer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX_XFER_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int stvdebug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param_named(debug, stvdebug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int i2cdebug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param_named(i2c_debug, i2cdebug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (stvdebug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) printk(KERN_DEBUG args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* DVB-C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum active_demod_state { demod_none, demod_ter, demod_cab };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct stv0367cab_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum stv0367_cab_signal_type state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) s32 search_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) s32 derot_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int locked; /* channel found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 freq_khz; /* found frequency (in kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 symbol_rate; /* found symbol rate (in Bds) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct stv0367ter_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum stv0367_ter_signal_type state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum stv0367_ter_if_iq_mode if_iq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum stv0367_ter_mode mode;/* mode 2K or 8K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum fe_guard_interval guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum stv0367_ter_hierarchy hierarchy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum fe_spectral_inversion sense; /* current search spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 force; /* force mode/guard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 bw; /* channel width 6, 7 or 8 in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 pBW; /* channel width used during previous lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 pBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 pPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) s8 echo_pos; /* echo position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 first_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 unlock_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 agc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct stv0367_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dvb_frontend fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* config settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct stv0367_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* DVB-C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct stv0367cab_state *cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct stv0367ter_state *ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* flags for operation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 use_i2c_gatectrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 deftabs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 reinit_on_setfrontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 auto_if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum active_demod_state activedemod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RF_LOOKUP_TABLE_SIZE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RF_LOOKUP_TABLE2_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {/*AGC1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 76, 77, 78, 80, 83, 85, 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }, {/*RF(dbm)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 49, 50, 52, 53, 54, 55, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {/*AGC2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 28, 29, 31, 32, 34, 35, 36, 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 38, 39, 40, 41, 42, 43, 44, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }, {/*RF(dbm)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 57, 58, 59, 60, 61, 62, 63, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 65, 66, 67, 68, 69, 70, 71, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 buf[MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .len = len + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (2 + len > sizeof(buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "%s: i2c wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) KBUILD_MODNAME, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) buf[0] = MSB(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) buf[1] = LSB(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) memcpy(buf + 2, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (i2cdebug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) state->config->demod_address, reg, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __func__, state->config->demod_address, reg, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return (ret != 1) ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return stv0367_writeregs(state, reg, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 b0[] = { 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .buf = b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .addr = state->config->demod_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .buf = b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) b0[0] = MSB(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) b0[1] = LSB(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __func__, state->config->demod_address, reg, b1[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (i2cdebug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) state->config->demod_address, reg, b1[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 position = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (*mask) = label & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) while ((position == 0) && (i < 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) position = ((*mask) >> i) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (*pos) = (i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 reg, mask, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg = stv0367_readreg(state, (label >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) extract_mask_pos(label, &mask, &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val = mask & (val << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg = (reg & (~mask)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) stv0367_writereg(state, (label >> 16) & 0xffff, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void stv0367_setbits(u8 *reg, u32 label, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 mask, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) extract_mask_pos(label, &mask, &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val = mask & (val << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (*reg) = ((*reg) & (~mask)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 val = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 mask, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) extract_mask_pos(label, &mask, &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) val = stv0367_readreg(state, label >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val = (val & mask) >> pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #if 0 /* Currently, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static u8 stv0367_getbits(u8 reg, u32 label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 mask, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) extract_mask_pos(label, &mask, &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return (reg & mask) >> pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void stv0367_write_table(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) const struct st_register *deftab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!deftab[i].addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) stv0367_writereg(state, deftab[i].addr, deftab[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void stv0367_pll_setup(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 icspeed, u32 xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* note on regs: R367TER_* and R367CAB_* defines each point to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * 0xf0d8, so just use R367TER_ for both cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (icspeed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case STV0367_ICSPEED_58000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) switch (xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 27000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PLLMDIV: 27, PLLNDIV: 232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case STV0367_ICSPEED_53125:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) switch (xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* set internal freq to 53.125MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case 16000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case 25000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case 27000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case 30000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *ifkhz = *ifkhz / 1000; /* hz -> khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *ifkhz = state->config->if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) stv0367_writereg(state, R367TER_I2CRPT, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct dvb_frontend_ops *frontend_ops = &fe->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (tuner_ops->get_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) err = tuner_ops->get_frequency(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) printk(KERN_ERR "%s: Invalid parameter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dprintk("%s: frequency=%d\n", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 mclk_Hz = 0; /* master clock frequency (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 m, n, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) n = n + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (m == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) m = m + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (p > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) p = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) n, m, p, mclk_Hz, ExtClk_Hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mclk_Hz = ExtClk_Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return mclk_Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u16 CellsCoeffs[3][6][5], u32 DemodXtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int i, j, k, freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) freq = stv0367ter_get_mclk(state, DemodXtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (freq == 53125000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) k = 1; /* equivalent to Xtal 25M on 362*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else if (freq == 54000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) k = 0; /* equivalent to Xtal 27M on 362*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else if (freq == 52500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) k = 2; /* equivalent to Xtal 30M on 362*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) for (i = 1; i <= 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (j = 1; j <= 5; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) stv0367_writereg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MSB(CellsCoeffs[k][i-1][j-1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) stv0367_writereg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) LSB(CellsCoeffs[k][i-1][j-1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Lock detect 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Lock detect 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Lock detect 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Lock detect 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 DemodXtalValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) stv0367_writebits(state, F367TER_NRST_IIR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) switch (Bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!stv0367ter_filt_coeff_init(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CellsCoeffs_6MHz_367cofdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) DemodXtalValue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!stv0367ter_filt_coeff_init(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CellsCoeffs_7MHz_367cofdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) DemodXtalValue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!stv0367ter_filt_coeff_init(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) CellsCoeffs_8MHz_367cofdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) DemodXtalValue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) stv0367_writebits(state, F367TER_NRST_IIR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 com_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) com_n = stv0367_readbits(state, F367TER_COM_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) stv0367_writebits(state, F367TER_COM_N, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) stv0367_writebits(state, F367TER_COM_N, com_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int local_tempo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) local_tempo = tempo1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) local_tempo = tempo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) local_tempo = tempo3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* msleep(local_tempo); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return local_tempo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int wd = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned short int SYR_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) s32 SYRStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) while ((!SYR_var) && (wd > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) wd -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!SYR_var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SYRStatus = FE_TER_NOSYMBOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SYRStatus = FE_TER_SYMBOLOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dprintk("stv0367ter_check_syr SYRStatus %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SYR_var == 0 ? "No Symbol" : "OK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return SYRStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) s32 FFTmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int wd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) switch (FFTmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case 0: /*2k mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CPAMPMin = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) wd = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case 1: /*8k mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) CPAMPMin = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) wd = 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case 2: /*4k mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) CPAMPMin = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) wd = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CPAMPMin = 0xffff; /*drives to NOCPAMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) wd -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (CPAMPvalue < CPAMPMin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CPAMPStatus = FE_TER_NOCPAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dprintk("%s: CPAMP failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dprintk("%s: CPAMP OK !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) CPAMPStatus = FE_TER_CPAMPOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return CPAMPStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static enum stv0367_ter_signal_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) stv0367ter_lock_algo(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum stv0367_ter_signal_type ret_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) short int wd, tempo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u8 tmp, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return FE_TER_SWNOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) try = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret_flag = FE_TER_LOCKOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (state->config->if_iq_mode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) stv0367_writebits(state, F367TER_COM_N, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) stv0367_writebits(state, F367TER_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return FE_TER_NOSYMBOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else { /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if chip locked on wrong mode first try,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) it must lock correctly second try */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mode = stv0367_readbits(state, F367TER_SYR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (stv0367ter_check_cpamp(state, mode) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) FE_TER_NOCPAMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (try == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret_flag = FE_TER_NOCPAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) try++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) tmp = stv0367_readreg(state, R367TER_SYR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) tmp2 = stv0367_readreg(state, R367TER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dprintk("state=%p\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mode, tmp, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) tmp = stv0367_readreg(state, R367TER_PRVIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dprintk("GAIN_SRC1=0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if ((mode != 0) && (mode != 1) && (mode != 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return FE_TER_SWNOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) and set channel predictor in automatic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) switch (guard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return FE_TER_SWNOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*reset fec an reedsolo FOR 367 only*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) stv0367_writebits(state, F367TER_RST_SFEC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) stv0367_writebits(state, F367TER_RST_SFEC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u_var1 = stv0367_readbits(state, F367TER_LK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u_var2 = stv0367_readbits(state, F367TER_PRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) wd = stv0367ter_duration(mode, 125, 500, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) tempo = stv0367ter_duration(mode, 4, 16, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) usleep_range(1000 * tempo, 1000 * (tempo + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) wd -= tempo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u_var1 = stv0367_readbits(state, F367TER_LK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u_var2 = stv0367_readbits(state, F367TER_PRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!u_var1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return FE_TER_NOLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!u_var2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return FE_TER_NOPRFOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!u_var3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return FE_TER_NOTPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) guard = stv0367_readbits(state, F367TER_SYR_GUARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) switch (guard) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) stv0367_writebits(state, F367TER_SYR_FILTER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) stv0367_writebits(state, F367TER_SYR_FILTER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return FE_TER_SWNOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (mode == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) wd = stv0367ter_duration(mode, 125, 500, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) while ((!u_var4) && (wd >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) usleep_range(1000 * tempo, 1000 * (tempo + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) wd -= tempo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!u_var4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return FE_TER_NOLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* for 367 leave COM_N at 0x7 for IQ_mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) tempo=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ChipWaitOrAbort(state,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) tempo+=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) stv0367_writebits(state,F367TER_COM_N,0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dprintk("FE_TER_LOCKOK !!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return FE_TER_LOCKOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void stv0367ter_set_ts_mode(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) enum stv0367_ts_mode PathTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) stv0367_writebits(state, F367TER_TS_DIS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) switch (PathTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*for removing warning :default we can assume in parallel mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case STV0367_PARALLEL_PUNCT_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case STV0367_SERIAL_PUNCT_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static void stv0367ter_set_clk_pol(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) enum stv0367_clk_pol clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case STV0367_RISINGEDGE_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case STV0367_FALLINGEDGE_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static void stv0367ter_core_sw(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) msleep(350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (standby_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) stv0367_writebits(state, F367TER_STDBY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) stv0367_writebits(state, F367TER_STDBY_FEC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) stv0367_writebits(state, F367TER_STDBY_CORE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) stv0367_writebits(state, F367TER_STDBY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) stv0367_writebits(state, F367TER_STDBY_FEC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) stv0367_writebits(state, F367TER_STDBY_CORE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int stv0367ter_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return stv0367ter_standby(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int stv0367ter_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ter_state->pBER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) stv0367_write_table(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) stv0367_writereg(state, R367TER_ANACTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*Set TS1 and TS2 to serial or parallel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) stv0367ter_set_ts_mode(state, state->config->ts_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) stv0367ter_set_clk_pol(state, state->config->clk_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) state->chip_id = stv0367_readreg(state, R367TER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ter_state->first_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ter_state->unlock_counter = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int stv0367ter_algo(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int offset = 0, tempo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u8 u_var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u8 /*constell,*/ counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) s8 step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) s32 timing_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) stv0367_get_if_khz(state, &ifkhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ter_state->frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ter_state->force = FE_TER_FORCENONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) + stv0367_readbits(state, F367TER_FORCE) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ter_state->if_iq_mode = state->config->if_iq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) switch (state->config->if_iq_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) stv0367_writebits(state, F367TER_TUNER_BB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) stv0367_writebits(state, F367TER_TUNER_BB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) case FE_TER_IQ_TUNER: /* IQ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) stv0367_writebits(state, F367TER_TUNER_BB, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) switch (p->inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case INVERSION_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dprintk("%s: inversion AUTO\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) stv0367_writebits(state, F367TER_IQ_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ter_state->sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) stv0367_writebits(state, F367TER_INV_SPECTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ter_state->sense);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) stv0367_writebits(state, F367TER_IQ_INVERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) stv0367_writebits(state, F367TER_INV_SPECTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) p->inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) (ter_state->pBW != ter_state->bw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) stv0367ter_agc_iir_lock_detect_set(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /*set fine agc target to 180 for LPIF or IQ mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* set Q_AGCTarget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* set Q_AGCTarget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!stv0367_iir_filt_init(state, ter_state->bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) state->config->xtal))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*set IIR filter once for 6,7 or 8MHz BW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ter_state->pBW = ter_state->bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) stv0367ter_agc_iir_rst(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) temp = (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ((((ter_state->bw * 64 * (1 << 15) * 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) / (InternalFreq)) * 10) / 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) temp = temp / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) stv0367_readbits(state, F367TER_GAIN_SRC_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) temp = (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dprintk("DEROT temp=0x%x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ter_state->echo_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ter_state->ucblocks = 0; /* liplianin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ter_state->pBER = 0; /* liplianin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ter_state->state = FE_TER_LOCKOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ter_state->first_lock = 1; /* we know sense now :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ter_state->agc_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Carrier offset calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) stv0367_writebits(state, F367TER_FREEZE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) stv0367_writebits(state, F367TER_FREEZE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (offset > 8388607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) offset -= 16777216;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) offset = offset * 2 / 16384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ter_state->mode == FE_TER_MODE_2K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) else if (ter_state->mode == FE_TER_MODE_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) else if (ter_state->mode == FE_TER_MODE_8K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) (stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) F367TER_STATUS_INV_SPECRUM) == 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) offset = offset * -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ter_state->bw == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) offset = (offset * 6) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) else if (ter_state->bw == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) offset = (offset * 7) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ter_state->frequency += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) tempo = 10; /* exit even if timing_offset stays null */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) while ((timing_offset == 0) && (tempo > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) usleep_range(10000, 20000); /*was 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* fine tuning of timing offset if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) + 256 * stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) F367TER_TRL_TOFFSET_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (timing_offset >= 32768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) timing_offset -= 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) trl_nomrate = (512 * stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) F367TER_TRL_NOMRATE_HI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) timing_offset = ((signed)(1000000 / trl_nomrate) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) timing_offset) / 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) tempo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (timing_offset <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) timing_offset = (timing_offset - 11) / 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) step = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) timing_offset = (timing_offset + 11) / 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) for (counter = 0; counter < abs(timing_offset); counter++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) trl_nomrate += step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) trl_nomrate % 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) trl_nomrate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* unlocks could happen in case of trl centring big step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) then a core off/on restarts demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u_var = stv0367_readbits(state, F367TER_LK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!u_var) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static int stv0367ter_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*u8 trials[2]; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) s8 num_trials, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (state->reinit_on_setfrontend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) stv0367ter_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) switch (p->transmission_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case TRANSMISSION_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) case TRANSMISSION_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ter_state->mode = FE_TER_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* case TRANSMISSION_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) pLook.mode = FE_TER_MODE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) break;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case TRANSMISSION_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ter_state->mode = FE_TER_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) switch (p->guard_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) case GUARD_INTERVAL_1_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case GUARD_INTERVAL_1_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case GUARD_INTERVAL_1_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case GUARD_INTERVAL_1_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ter_state->guard = p->guard_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case GUARD_INTERVAL_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ter_state->guard = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) switch (p->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ter_state->bw = FE_TER_CHAN_BW_6M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ter_state->bw = FE_TER_CHAN_BW_7M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ter_state->bw = FE_TER_CHAN_BW_8M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ter_state->hierarchy = FE_TER_HIER_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) switch (p->inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) num_trials = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) num_trials = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (ter_state->first_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) num_trials = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ter_state->state = FE_TER_NOLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (!ter_state->first_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (p->inversion == INVERSION_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ter_state->sense = SenseTrials[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) stv0367ter_algo(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if ((ter_state->state == FE_TER_LOCKOK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) (p->inversion == INVERSION_AUTO) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) (index == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* invert spectrum sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) SenseTrials[index] = SenseTrials[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) u32 errs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /*wait for counting completion*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) errs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * (1 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ter_state->ucblocks = errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) (*ucblocks) = ter_state->ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static int stv0367ter_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) enum stv0367_ter_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int constell = 0,/* snr = 0,*/ Data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) p->frequency = stv0367_get_tuner_freq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if ((int)p->frequency < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) p->frequency = -p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) constell = stv0367_readbits(state, F367TER_TPS_CONST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (constell == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) p->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) else if (constell == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) p->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) p->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* Get the Hierarchical mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) switch (Data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) p->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) p->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) p->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) p->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) p->hierarchy = HIERARCHY_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) break; /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* Get the FEC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) switch (Data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) p->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) p->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) p->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) p->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) p->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) p->code_rate_HP = FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) break; /* error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) mode = stv0367_readbits(state, F367TER_SYR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case FE_TER_MODE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) p->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* case FE_TER_MODE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) p->transmission_mode = TRANSMISSION_MODE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) break;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case FE_TER_MODE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) p->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) p->transmission_mode = TRANSMISSION_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u32 snru32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int cpt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) while (cpt < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (cut == 0x50) /*cut 1.0 cut 1.1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) else /*cu2.0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) cpt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) snru32 /= 10;/*average on 10 values*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return snru32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u32 snrval = stv0367ter_snr_readreg(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) *snr = snrval / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static int stv0367ter_status(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) int locked = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) locked = (stv0367_readbits(state, F367TER_LK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (!locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ter_state->unlock_counter += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ter_state->unlock_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ter_state->unlock_counter > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) (!stv0367_readbits(state, F367TER_LK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) msleep(350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) (stv0367_readbits(state, F367TER_LK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int stv0367ter_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (stv0367_readbits(state, F367TER_LK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) dprintk("%s: stv0367 has locked\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u32 Errors = 0, tber = 0, temporary = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) int abc = 0, def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /*wait for counting completion*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * (1 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) + ((u32)stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) F367TER_SFEC_ERR_CNT_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /*measurement not completed, load previous value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) tber = ter_state->pBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (Errors == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) tber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) } else if (abc == 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (Errors <= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) temporary = (Errors * 1000000000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) } else if (Errors <= 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) temporary = (Errors * 100000000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) temporary = temporary * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) } else if (Errors <= 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) temporary = (Errors * 10000000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) temporary = temporary * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) } else if (Errors <= 4294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) temporary = (Errors * 1000000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) temporary = temporary * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) } else if (Errors <= 42949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) temporary = (Errors * 100000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) temporary = temporary * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) } else if (Errors <= 429496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) temporary = (Errors * 10000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) temporary = temporary * 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) } else { /*if (Errors<4294967) 2^22 max error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) temporary = (Errors * 1000) / (8 * (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) temporary = temporary * 100000; /* still to *10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* Byte error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (def == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /*tber=Errors/(8*(1 <<14));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) tber = temporary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) else if (def == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /*tber=Errors/(8*(1 <<16));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) tber = temporary / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) else if (def == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /*tber=Errors/(8*(1 <<18));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) tber = temporary / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) else if (def == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /*tber=Errors/(8*(1 <<20));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) tber = temporary / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) else if (def == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /*tber=Errors/(8*(1 <<22));*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) tber = temporary / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* should not pass here*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) tber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if ((Errors < 4294967) && (Errors > 429496))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) tber *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* save actual value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ter_state->pBER = tber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) (*ber) = tber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static u32 stv0367ter_get_per(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) u32 Errors = 0, Per = 0, temporary = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int abc = 0, def = 0, cpt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * (1 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) cpt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) abc = stv0367_readbits(state, F367TER_ERR_SRC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) def = stv0367_readbits(state, F367TER_NUM_EVT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (Errors == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) Per = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) else if (abc == 0x9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (Errors <= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) temporary = (Errors * 1000000000) / (8 * (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) } else if (Errors <= 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) temporary = (Errors * 100000000) / (8 * (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) temporary = temporary * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } else if (Errors <= 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) temporary = (Errors * 10000000) / (8 * (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) temporary = temporary * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) } else if (Errors <= 4294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) temporary = (Errors * 1000000) / (8 * (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) temporary = temporary * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) } else if (Errors <= 42949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) temporary = (Errors * 100000) / (8 * (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) temporary = temporary * 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) } else { /*if(Errors<=429496) 2^16 errors max*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) temporary = (Errors * 10000) / (8 * (1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) temporary = temporary * 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* pkt error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (def == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /*Per=Errors/(1 << 8);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) Per = temporary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) else if (def == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /*Per=Errors/(1 << 10);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) Per = temporary / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) else if (def == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /*Per=Errors/(1 << 12);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) Per = temporary / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) else if (def == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /*Per=Errors/(1 << 14);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) Per = temporary / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) else if (def == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /*Per=Errors/(1 << 16);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) Per = temporary / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) Per = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* save actual value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ter_state->pPER = Per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return Per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static int stv0367_get_tune_settings(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct dvb_frontend_tune_settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) *fe_tune_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) fe_tune_settings->min_delay_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) fe_tune_settings->step_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) fe_tune_settings->max_drift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static void stv0367_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) kfree(state->ter_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) kfree(state->cab_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static const struct dvb_frontend_ops stv0367ter_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .name = "ST STV0367 DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .frequency_min_hz = 47 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .frequency_stepsize_hz = 15625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .release = stv0367_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .init = stv0367ter_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .sleep = stv0367ter_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .i2c_gate_ctrl = stv0367ter_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .set_frontend = stv0367ter_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .get_frontend = stv0367ter_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .get_tune_settings = stv0367_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .read_status = stv0367ter_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .read_ber = stv0367ter_read_ber,/* too slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* .read_signal_strength = stv0367_read_signal_strength,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .read_snr = stv0367ter_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .read_ucblocks = stv0367ter_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct stv0367_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct stv0367ter_state *ter_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (ter_state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) state->ter_state = ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) state->fe.ops = stv0367ter_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) state->fe.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) state->chip_id = stv0367_readreg(state, 0xf000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /* demod operation options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) state->use_i2c_gatectrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) state->deftabs = STV0367_DEFTAB_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) state->reinit_on_setfrontend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) state->auto_if_khz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return &state->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) kfree(ter_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) EXPORT_SYMBOL(stv0367ter_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) u32 mclk_Hz = 0;/* master clock frequency (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) u32 M, N, P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (N == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) N = N + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (M == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) M = M + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (P > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) P = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) mclk_Hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) mclk_Hz = ExtClk_Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return mclk_Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u32 ADCClk_Hz = ExtClk_Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return ADCClk_Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) u32 SymbolRate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) enum stv0367cab_mod QAMSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /* Set QAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* Set Registers settings specific to the QAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) switch (QAMSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) case FE_CAB_MOD_QAM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) case FE_CAB_MOD_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) case FE_CAB_MOD_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) case FE_CAB_MOD_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (SymbolRate > 4500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) } else if (SymbolRate > 2500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) case FE_CAB_MOD_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (SymbolRate > 4500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) else if (SymbolRate > 2500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) case FE_CAB_MOD_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (SymbolRate > 4500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) else if (SymbolRate > 2500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) case FE_CAB_MOD_QAM512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) case FE_CAB_MOD_QAM1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return QAMSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) u32 adc_hz, s32 derot_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) u32 sampled_if = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) u32 adc_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) adc_khz = adc_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (adc_khz != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (derot_hz < 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) derot_hz = adc_hz / 4; /* ZIF operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (derot_hz > adc_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) derot_hz = derot_hz - adc_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) sampled_if = (u32)derot_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) sampled_if *= 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) sampled_if /= adc_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) sampled_if *= 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (sampled_if > 8388607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) sampled_if = 8388607;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return derot_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) u32 sampled_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) sampled_if /= 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) sampled_if *= (adc_hz / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) sampled_if += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) sampled_if /= 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return sampled_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) u32 mclk_hz, u32 SymbolRate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) enum stv0367cab_mod QAMSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) u32 QamSizeCorr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) u32 u32_tmp = 0, u32_tmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) u32 adp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /* Set Correction factor of SRC gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) switch (QAMSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) case FE_CAB_MOD_QAM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) QamSizeCorr = 1110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) case FE_CAB_MOD_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) QamSizeCorr = 1032;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) case FE_CAB_MOD_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) QamSizeCorr = 954;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case FE_CAB_MOD_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) QamSizeCorr = 983;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) case FE_CAB_MOD_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) QamSizeCorr = 957;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) case FE_CAB_MOD_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) QamSizeCorr = 948;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) case FE_CAB_MOD_QAM512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) QamSizeCorr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) case FE_CAB_MOD_QAM1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) QamSizeCorr = 944;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* Transfer ratio calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (adc_hz != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) u32_tmp = 256 * SymbolRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) u32_tmp = u32_tmp / adc_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /* Symbol rate and SRC gain calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (adp_khz != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) u32_tmp = SymbolRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) u32_tmp1 = SymbolRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* Symbol rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) u32_tmp *= 2048; /* 2048 = 2^11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) u32_tmp = u32_tmp / adp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) u32_tmp /= 125 ; /* 125 = 1000/2^3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* SRC Gain Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) u32_tmp1 *= 2048; /* *2*2^10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) u32_tmp1 /= 439; /* *2/878 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) u32_tmp1 *= 256; /* *2^8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) u32_tmp1 = u32_tmp1 / 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* Symbol rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) u32_tmp *= 1024 ; /* 1024 = 2**10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) u32_tmp = u32_tmp / adp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) u32_tmp /= 125 ; /* 125 = 1000/2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* SRC Gain Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) u32_tmp1 *= 1024; /* *2*2^9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) u32_tmp1 /= 439; /* *2/878 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) u32_tmp1 *= 256; /* *2^8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) u32_tmp1 = u32_tmp1 / 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* Symbol rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) u32_tmp *= 512 ; /* 512 = 2**9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) u32_tmp = u32_tmp / adp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) u32_tmp /= 125 ; /* 125 = 1000/2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) /* SRC Gain Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) u32_tmp1 *= 512; /* *2*2^8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) u32_tmp1 /= 439; /* *2/878 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) u32_tmp1 *= 256; /* *2^8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) u32_tmp1 = u32_tmp1 / 2500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) /* Symbol rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) u32_tmp *= 256 ; /* 256 = 2**8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) u32_tmp = u32_tmp / adp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) u32_tmp /= 125 ; /* 125 = 1000/2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /* SRC Gain Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) u32_tmp1 *= 256; /* 2*2^7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) u32_tmp1 /= 439; /* *2/878 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) u32_tmp1 *= 256; /* *2^8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) u32_tmp1 = u32_tmp1 / 1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* Filters' coefficients are calculated and written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) into registers only if the filters are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) SymbolRate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* AllPass filter must be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) when the adjacents filter is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* AllPass filter must be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) when the adjacents filter is not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return SymbolRate ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) u32 regsym;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) u32 adp_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (regsym < 134217728) { /* 134217728L = 2**27*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) regsym = regsym * 32; /* 32 = 2**5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) regsym = regsym / 32768; /* 32768L = 2**15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) regsym = adp_khz * regsym; /* AdpClk in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) regsym = regsym / 128; /* 128 = 2**7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) regsym *= 125 ; /* 125 = 1000/2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) regsym /= 2048 ; /* 2048 = 2**11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) } else if (regsym < 268435456) { /* 268435456L = 2**28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) regsym = regsym * 16; /* 16 = 2**4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) regsym = regsym / 32768; /* 32768L = 2**15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) regsym = adp_khz * regsym; /* AdpClk in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) regsym = regsym / 128; /* 128 = 2**7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) regsym *= 125 ; /* 125 = 1000/2**3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) regsym /= 1024 ; /* 256 = 2**10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) } else if (regsym < 536870912) { /* 536870912L = 2**29*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) regsym = regsym * 8; /* 8 = 2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) regsym = regsym / 32768; /* 32768L = 2**15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) regsym = adp_khz * regsym; /* AdpClk in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) regsym = regsym / 128; /* 128 = 2**7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) regsym *= 125 ; /* 125 = 1000/2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) regsym /= 512 ; /* 128 = 2**9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) regsym = regsym * 4; /* 4 = 2**2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) regsym = regsym / 32768; /* 32768L = 2**15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) regsym = adp_khz * regsym; /* AdpClk in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) regsym = regsym / 128; /* 128 = 2**7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) regsym *= 125 ; /* 125 = 1000/2**3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) regsym /= 256 ; /* 64 = 2**8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return regsym;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static u32 stv0367cab_fsm_status(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) return stv0367_readbits(state, F367CAB_FSM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) (state->cab_state->qamfec_status_reg ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) state->cab_state->qamfec_status_reg :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) F367CAB_QAMFEC_LOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) switch (qam_fsm_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) signaltype = FE_CAB_NOAGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) signaltype = FE_CAB_NOTIMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) signaltype = FE_CAB_TIMINGOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) signaltype = FE_CAB_NOCARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) signaltype = FE_CAB_CARRIEROK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) signaltype = FE_CAB_NOBLIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) signaltype = FE_CAB_BLINDOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) signaltype = FE_CAB_NODEMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) signaltype = FE_CAB_DEMODOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) signaltype = FE_CAB_DEMODOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) signaltype = FE_CAB_NODEMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) signaltype = FE_CAB_NOBLIND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) signaltype = FE_CAB_NOSIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return signaltype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static int stv0367cab_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) /* update cab_state->state from QAM_FSM_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) state->cab_state->state = stv0367cab_fsm_signaltype(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) stv0367cab_fsm_status(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (stv0367cab_qamfec_lock(state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) | FE_HAS_SYNC | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) dprintk("%s: stv0367 has locked\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (state->cab_state->state > FE_CAB_NOSIGNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (state->cab_state->state > FE_CAB_NOCARRIER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (state->cab_state->state >= FE_CAB_DEMODOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (state->cab_state->state >= FE_CAB_DATAOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) if (standby_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) stv0367_writebits(state, F367CAB_STDBY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) stv0367_writebits(state, F367CAB_POFFQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) stv0367_writebits(state, F367CAB_POFFI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) stv0367_writebits(state, F367CAB_STDBY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) stv0367_writebits(state, F367CAB_POFFQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) stv0367_writebits(state, F367CAB_POFFI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static int stv0367cab_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return stv0367cab_standby(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static int stv0367cab_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) struct stv0367cab_state *cab_state = state->cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) stv0367_write_table(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) switch (state->config->ts_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) case STV0367_DVBCI_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) case STV0367_SERIAL_PUNCT_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) case STV0367_SERIAL_CONT_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) case STV0367_PARALLEL_PUNCT_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) case STV0367_OUTPUTMODE_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) switch (state->config->clk_pol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) case STV0367_RISINGEDGE_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) case STV0367_FALLINGEDGE_CLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) case STV0367_CLOCKPOLARITY_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) struct stv0367cab_state *cab_state = state->cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) u8 TrackAGCAccum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) s32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) stv0367_get_if_khz(state, &ifkhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /* Timeouts calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /* A max lock time of 25 ms is allowed for delayed AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) AGCTimeOut = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) /* 100000 symbols needed by the TRL as a maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) TRLTimeOut = 100000000 / p->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* CRLSymbols is the needed number of symbols to achieve a lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) within [-4%, +4%] of the symbol rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) CRL timeout is calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) for a lock within [-search_range, +search_range].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) EQL timeout can be changed depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) the micro-reflections we want to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) A characterization must be performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) with these echoes to get new timeout values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) CRLSymbols = 150000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) EQLTimeOut = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) case QAM_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) CRLSymbols = 250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) EQLTimeOut = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) CRLSymbols = 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) EQLTimeOut = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) case QAM_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) CRLSymbols = 250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) EQLTimeOut = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) CRLSymbols = 250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) EQLTimeOut = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) CRLSymbols = 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) EQLTimeOut = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (pIntParams->search_range < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) CRLTimeOut = (25 * CRLSymbols *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) (-pIntParams->search_range / 1000)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) (pIntParams->symbol_rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) (p->symbol_rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) /* Timeouts below 50ms are coerced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (CRLTimeOut < 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) CRLTimeOut = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* A maximum of 100 TS packets is needed to get FEC lock even in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) the spectrum inversion needs to be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) FECTimeOut = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* Reset the TRL to ensure nothing starts until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) AGC is stable which ensures a better lock time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /* Set AGC accumulation time to minimum and lock threshold to maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) in order to speed up the AGC lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /* Modulus Mapper is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* Disable the sweep function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* The sweep function is never used, Sweep rate must be set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* Set the derotator frequency in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) stv0367cab_set_derot_freq(state, cab_state->adc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) (1000 * (s32)ifkhz + cab_state->derot_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) /* Disable the Allpass Filter when the symbol rate is out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) stv0367_writebits(state, F367CAB_ADJ_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* Check if the tuner is locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) tuner_lock = stv0367cab_tuner_get_status(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) if (tuner_lock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) return FE_367CAB_NOTUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* Release the TRL to start demodulator acquisition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /* Wait for QAM lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) LockTime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) QAM_Lock = stv0367cab_fsm_status(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) (QAM_Lock == 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) * We don't wait longer, the frequency/phase offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) * must be too big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) LockTime = DemodTimeOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) (QAM_Lock == 0x02))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * We don't wait longer, either there is no signal or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * it is not the right symbol rate or it is an analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) LockTime = DemodTimeOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) u32_tmp = stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) F367CAB_AGC_PWR_WORD_LO) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) (stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) F367CAB_AGC_PWR_WORD_ME) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) (stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) F367CAB_AGC_PWR_WORD_HI) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (u32_tmp >= 131072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) u32_tmp = 262144 - u32_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) F367CAB_AGC_IF_BWSEL)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (u32_tmp < stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) F367CAB_AGC_PWRREF_LO) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) 256 * stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) F367CAB_AGC_PWRREF_HI) - 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) QAM_Lock = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) LockTime += 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) (LockTime < DemodTimeOut));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) dprintk("QAM_Lock=0x%x\n", QAM_Lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /* Wait for FEC lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) LockTime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) LockTime += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) QAMFEC_Lock = stv0367cab_qamfec_lock(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) QAMFEC_Lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (QAMFEC_Lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) signalType = FE_CAB_DATAOK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) cab_state->spect_inv = stv0367_readbits(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) F367CAB_QUAD_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) /* not clear for me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (ifkhz != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (ifkhz > cab_state->adc_clk / 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) cab_state->freq_khz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) FE_Cab_TunerGetFrequency(pIntParams->hTuner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) - cab_state->adc_clk / 1000 + ifkhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) cab_state->freq_khz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) FE_Cab_TunerGetFrequency(pIntParams->hTuner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) + ifkhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) cab_state->freq_khz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) stv0367cab_get_derot_freq(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) cab_state->adc_clk) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) cab_state->adc_clk / 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) cab_state->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) cab_state->locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) signalType = stv0367cab_fsm_signaltype(QAM_Lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) /* Set the AGC control values to tracking values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) return signalType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) static int stv0367cab_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) struct stv0367cab_state *cab_state = state->cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) enum stv0367cab_mod QAMSize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) dprintk("%s: freq = %d, srate = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) p->frequency, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) cab_state->derot_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) QAMSize = FE_CAB_MOD_QAM16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) case QAM_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) QAMSize = FE_CAB_MOD_QAM32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) QAMSize = FE_CAB_MOD_QAM64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) case QAM_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) QAMSize = FE_CAB_MOD_QAM128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) QAMSize = FE_CAB_MOD_QAM256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) if (state->reinit_on_setfrontend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) stv0367cab_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) /* Tuner Frequency Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) stv0367cab_SetQamSize(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) p->symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) QAMSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) stv0367cab_set_srate(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) cab_state->adc_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) cab_state->mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) p->symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) QAMSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) cab_state->state = stv0367cab_algo(state, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static int stv0367cab_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) struct stv0367cab_state *cab_state = state->cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) u32 ifkhz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) enum stv0367cab_mod QAMSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) stv0367_get_if_khz(state, &ifkhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) switch (QAMSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) case FE_CAB_MOD_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) p->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) case FE_CAB_MOD_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) p->modulation = QAM_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) case FE_CAB_MOD_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) p->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) case FE_CAB_MOD_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) p->modulation = QAM_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) case FE_CAB_MOD_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) p->modulation = QAM_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) p->frequency = stv0367_get_tuner_freq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (ifkhz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) p->frequency +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) cab_state->adc_clk / 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if (ifkhz > cab_state->adc_clk / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) p->frequency += (ifkhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) - cab_state->adc_clk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) p->frequency += (ifkhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) stv0367cab_GetPacketsCount(state, Monitor_results);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) s32 rfLevel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) s32 RfAgcPwm = 0, IfAgcPwm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) RfAgcPwm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) RfAgcPwm = 100 * RfAgcPwm / 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) IfAgcPwm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) if (IfAgcPwm >= 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) IfAgcPwm -= 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) IfAgcPwm += 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) IfAgcPwm = 100 * IfAgcPwm / 4095;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) /* For DTT75467 on NIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (RfAgcPwm < 90 && IfAgcPwm < 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (i == RF_LOOKUP_TABLE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) rfLevel = -56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) } else { /*if IF AGC>10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (i == RF_LOOKUP_TABLE2_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) rfLevel = -72;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) return rfLevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) s32 signal = stv0367cab_get_rf_lvl(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) dprintk("%s: signal=%d dBm\n", __func__, signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (signal <= -72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) *strength = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) *strength = (22 + signal) * (-1311);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) dprintk("%s: strength=%d\n", __func__, (*strength));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static int stv0367cab_snr_power(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) enum stv0367cab_mod QAMSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) switch (QAMSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) case FE_CAB_MOD_QAM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) return 21904;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) case FE_CAB_MOD_QAM16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) return 20480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) case FE_CAB_MOD_QAM32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) return 23040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) case FE_CAB_MOD_QAM64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return 21504;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) case FE_CAB_MOD_QAM128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) return 23616;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) case FE_CAB_MOD_QAM256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) return 21760;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) case FE_CAB_MOD_QAM1024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) return 21280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) u32 regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) regval += (stv0367_readbits(state, F367CAB_SNR_LO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (avgdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) regval /= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) u32 noisepercentage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) u32 regval = 0, temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) int power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) power = stv0367cab_snr_power(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) regval = stv0367cab_snr_readreg(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (regval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) temp = power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) temp /= regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* table values, not needed to calculate logarithms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) if (temp >= 5012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) noisepercentage = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) else if (temp >= 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) noisepercentage = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) else if (temp >= 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) noisepercentage = 86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) else if (temp >= 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) noisepercentage = 79;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) else if (temp >= 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) noisepercentage = 72;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) else if (temp >= 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) noisepercentage = 65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) else if (temp >= 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) noisepercentage = 58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) else if (temp >= 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) noisepercentage = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) else if (temp >= 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) noisepercentage = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) else if (temp >= 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) noisepercentage = 36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) else if (temp >= 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) noisepercentage = 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) else if (temp >= 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) noisepercentage = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) else if (temp >= 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) noisepercentage = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) else if (temp >= 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) noisepercentage = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) noisepercentage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) *snr = (noisepercentage * 65535) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) int corrected, tscount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) __func__, *ucblocks, corrected, tscount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) static const struct dvb_frontend_ops stv0367cab_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .delsys = { SYS_DVBC_ANNEX_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .name = "ST STV0367 DVB-C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .frequency_min_hz = 47 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .symbol_rate_min = 870000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .symbol_rate_max = 11700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .caps = 0x400 |/* FE_CAN_QAM_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) FE_CAN_QAM_16 | FE_CAN_QAM_32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) FE_CAN_QAM_64 | FE_CAN_QAM_128 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .release = stv0367_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .init = stv0367cab_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .sleep = stv0367cab_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .i2c_gate_ctrl = stv0367cab_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .set_frontend = stv0367cab_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .get_frontend = stv0367cab_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .read_status = stv0367cab_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) /* .read_ber = stv0367cab_read_ber, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .read_signal_strength = stv0367cab_read_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .read_snr = stv0367cab_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .read_ucblocks = stv0367cab_read_ucblcks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .get_tune_settings = stv0367_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) struct stv0367_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) struct stv0367cab_state *cab_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) if (cab_state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) cab_state->search_range = 280000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) state->cab_state = cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) state->fe.ops = stv0367cab_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) state->fe.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) state->chip_id = stv0367_readreg(state, 0xf000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) /* demod operation options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) state->use_i2c_gatectrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) state->deftabs = STV0367_DEFTAB_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) state->reinit_on_setfrontend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) state->auto_if_khz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) return &state->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) kfree(cab_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) EXPORT_SYMBOL(stv0367cab_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) * Functions for operation on Digital Devices hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static void stv0367ddb_setup_ter(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /* Tuner Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) /* Buffer Q disabled, I Enabled, unsigned ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) /* Clock setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) /* PLL bypassed and disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) /* IC runs at 54 MHz with a 27 MHz crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) /* PLL enabled and used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) stv0367_writereg(state, R367TER_ANACTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) state->activedemod = demod_ter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) static void stv0367ddb_setup_cab(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) /* Tuner Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) /* Buffer Q disabled, I Enabled, signed ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) /* ADCQ disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /* Clock setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) /* PLL bypassed and disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* Set QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) /* IC runs at 58 MHz with a 27 MHz crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /* PLL enabled and used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) stv0367_writereg(state, R367TER_ANACTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) state->activedemod = demod_cab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) switch (fe->dtv_property_cache.delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (state->activedemod != demod_ter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) stv0367ddb_setup_ter(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) return stv0367ter_set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) if (state->activedemod != demod_cab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) stv0367ddb_setup_cab(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) /* protect against division error oopses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) if (fe->dtv_property_cache.symbol_rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) printk(KERN_ERR "Invalid symbol rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) return stv0367cab_set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) s32 signalstrength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) switch (state->activedemod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) case demod_cab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) p->strength.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) p->strength.stat[0].uvalue = signalstrength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static void stv0367ddb_read_snr(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) int cab_pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) u32 regval, tmpval, snrval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) switch (state->activedemod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) case demod_ter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) snrval = stv0367ter_snr_readreg(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) case demod_cab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) cab_pwr = stv0367cab_snr_power(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) regval = stv0367cab_snr_readreg(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) /* prevent division by zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) if (!regval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) snrval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) tmpval = (cab_pwr * 320) / regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) p->cnr.stat[0].uvalue = snrval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) u32 ucblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) switch (state->activedemod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) case demod_ter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) stv0367ter_read_ucblocks(fe, &ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) case demod_cab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) stv0367cab_read_ucblcks(fe, &ucblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) p->block_error.stat[0].scale = FE_SCALE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) p->block_error.stat[0].uvalue = ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) static int stv0367ddb_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) switch (state->activedemod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) case demod_ter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) ret = stv0367ter_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) case demod_cab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) ret = stv0367cab_read_status(fe, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) /* stop and report on *_read_status failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) stv0367ddb_read_signal_strength(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) /* read carrier/noise when a carrier is detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (*status & FE_HAS_CARRIER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) stv0367ddb_read_snr(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) /* read uncorrected blocks on FE_HAS_LOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) if (*status & FE_HAS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) stv0367ddb_read_ucblocks(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) switch (state->activedemod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) case demod_ter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) return stv0367ter_get_frontend(fe, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) case demod_cab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) return stv0367cab_get_frontend(fe, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) static int stv0367ddb_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) struct stv0367_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) switch (state->activedemod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) case demod_ter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) state->activedemod = demod_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) return stv0367ter_sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) case demod_cab:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) state->activedemod = demod_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) return stv0367cab_sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) static int stv0367ddb_init(struct stv0367_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) struct stv0367ter_state *ter_state = state->ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) stv0367_write_table(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) stv0367_write_table(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) stv0367_write_table(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) /* OFDM TS Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) stv0367_writereg(state, R367TER_TSCFGH, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) stv0367_writereg(state, R367TER_TSCFGL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) stv0367_writereg(state, R367TER_TSCFGH, 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) stv0367_writereg(state, R367TER_TSCFGH, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) /* Also needed for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) /* QAM TS setup, note exact format also depends on descrambler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) /* settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) /* Inverted Clock, Swap, serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) /* Clock setup (PLL bypassed and disabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) /* IC runs at 58 MHz with a 27 MHz crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) /* Tuner setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) /* Buffer Q disabled, I Enabled, signed ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* Improves the C/N lock limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /* ZIF/IF Automatic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* Improving burst noise performances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* Improving ACI performances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) /* PLL enabled and used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) stv0367_writereg(state, R367TER_ANACTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) ter_state->pBER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) ter_state->first_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) ter_state->unlock_counter = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) p->strength.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) p->cnr.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) p->block_error.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) static const struct dvb_frontend_ops stv0367ddb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) .name = "ST STV0367 DDB DVB-C/T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .frequency_min_hz = 47 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .frequency_max_hz = 865 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .frequency_stepsize_hz = 166667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .symbol_rate_min = 870000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) .symbol_rate_max = 11700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) .caps = /* DVB-C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) 0x400 |/* FE_CAN_QAM_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) FE_CAN_QAM_16 | FE_CAN_QAM_32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) FE_CAN_QAM_64 | FE_CAN_QAM_128 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) FE_CAN_QAM_256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) /* DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) FE_CAN_MUTE_TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .release = stv0367_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .sleep = stv0367ddb_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .set_frontend = stv0367ddb_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .get_frontend = stv0367ddb_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) .get_tune_settings = stv0367_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) .read_status = stv0367ddb_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) struct stv0367_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) struct stv0367ter_state *ter_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) struct stv0367cab_state *cab_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) if (ter_state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) if (cab_state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) state->ter_state = ter_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) cab_state->search_range = 280000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) state->cab_state = cab_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) state->fe.ops = stv0367ddb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) state->fe.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) state->chip_id = stv0367_readreg(state, R367TER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) /* demod operation options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) state->use_i2c_gatectrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) state->deftabs = STV0367_DEFTAB_DDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) state->reinit_on_setfrontend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) state->auto_if_khz = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) state->activedemod = demod_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) state->fe.ops.info.name, state->chip_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) config->demod_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) stv0367ddb_init(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) return &state->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) kfree(cab_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) kfree(ter_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) EXPORT_SYMBOL(stv0367ddb_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) MODULE_PARM_DESC(debug, "Set debug");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) MODULE_AUTHOR("Igor M. Liplianin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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