^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Driver for ST STV0299 demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2001-2002 Convergence Integrated Media GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) <ralph@convergence.de>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) <holger@convergence.de>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) <js@convergence.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Philips SU1278/SH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Copyright (C) 2002 by Peter Schildmann <peter.schildmann@web.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) LG TDQF-S001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Copyright (C) 2002 Felix Domke <tmbinc@elitedvb.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) & Andreas Oberritter <obi@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Support for Samsung TBMU24112IMB used on Technisat SkyStar2 rev. 2.6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Copyright (C) 2003 Vadim Catana <skystar@moldova.cc>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Support for Philips SU1278 on Technotrend hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "stv0299.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct stv0299_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct i2c_adapter* i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const struct stv0299_config* config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 initialised:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 tuner_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum fe_code_rate fec_inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int errmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 mcr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STATUS_BER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STATUS_UCBLOCKS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int debug_legacy_dish_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (debug) printk(KERN_DEBUG "stv0299: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int stv0299_writeregI (struct stv0299_state* state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 buf [] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = i2c_transfer (state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return (ret != 1) ? -EREMOTEIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int stv0299_write(struct dvb_frontend* fe, const u8 buf[], int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (len != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return stv0299_writeregI(state, buf[0], buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static u8 stv0299_readreg (struct stv0299_state* state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 b0 [] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 b1 [] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = i2c_transfer (state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int stv0299_readregs (struct stv0299_state* state, u8 reg1, u8 *b, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = ®1, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = len } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = i2c_transfer (state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dprintk("%s: readreg error (ret == %i)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret == 2 ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int stv0299_set_FEC(struct stv0299_state *state, enum fe_code_rate fec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (fec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case FEC_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return stv0299_writeregI (state, 0x31, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case FEC_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return stv0299_writeregI (state, 0x31, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case FEC_2_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return stv0299_writeregI (state, 0x31, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case FEC_3_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return stv0299_writeregI (state, 0x31, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case FEC_5_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return stv0299_writeregI (state, 0x31, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case FEC_7_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return stv0299_writeregI (state, 0x31, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static enum fe_code_rate stv0299_get_fec(struct stv0299_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static enum fe_code_rate fec_tab[] = { FEC_2_3, FEC_3_4, FEC_5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FEC_7_8, FEC_1_2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) index = stv0299_readreg (state, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) index &= 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (index > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return FEC_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return fec_tab [index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int stv0299_wait_diseqc_fifo (struct stv0299_state* state, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) while (stv0299_readreg(state, 0x0a) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (jiffies - start > timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dprintk ("%s: timeout!!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int stv0299_wait_diseqc_idle (struct stv0299_state* state, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) while ((stv0299_readreg(state, 0x0a) & 3) != 2 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (jiffies - start > timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dprintk ("%s: timeout!!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int stv0299_set_symbolrate (struct dvb_frontend* fe, u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u64 big = srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) // check rate is within limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if ((srate < 1000000) || (srate > 45000000)) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) // calculate value to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) big = big << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) big += (state->config->mclk-1); // round correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) do_div(big, state->config->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ratio = big << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return state->config->set_symbol_rate(fe, srate, ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int stv0299_get_symbolrate (struct stv0299_state* state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 Mclk = state->config->mclk / 4096L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) s32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 sfr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) s8 rtf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) stv0299_readregs (state, 0x1f, sfr, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) stv0299_readregs (state, 0x1a, (u8 *)&rtf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) srate = (sfr[0] << 8) | sfr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) srate *= Mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) srate /= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) srate += (sfr[2] >> 4) * Mclk / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) offset = (s32) rtf * (srate / 4096L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) offset /= 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dprintk ("%s : srate = %i\n", __func__, srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dprintk ("%s : ofset = %i\n", __func__, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) srate += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) srate += 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) srate /= 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) srate *= 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int stv0299_send_diseqc_msg (struct dvb_frontend* fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct dvb_diseqc_master_cmd *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (stv0299_wait_diseqc_idle (state, 100) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val = stv0299_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x6)) /* DiSEqC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (i=0; i<m->msg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (stv0299_wait_diseqc_fifo (state, 100) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (stv0299_writeregI (state, 0x09, m->msg[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (stv0299_wait_diseqc_idle (state, 100) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int stv0299_send_diseqc_burst(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum fe_sec_mini_cmd burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dprintk ("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (stv0299_wait_diseqc_idle (state, 100) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = stv0299_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (stv0299_writeregI (state, 0x08, (val & ~0x7) | 0x2)) /* burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (stv0299_writeregI (state, 0x09, burst == SEC_MINI_A ? 0x00 : 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (stv0299_wait_diseqc_idle (state, 100) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (stv0299_writeregI (state, 0x08, val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int stv0299_set_tone(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum fe_sec_tone_mode tone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (stv0299_wait_diseqc_idle (state, 100) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) val = stv0299_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch (tone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case SEC_TONE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return stv0299_writeregI (state, 0x08, val | 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case SEC_TONE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return stv0299_writeregI (state, 0x08, (val & ~0x3) | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int stv0299_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 reg0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 reg0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dprintk("%s: %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) voltage == SEC_VOLTAGE_13 ? "SEC_VOLTAGE_13" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) voltage == SEC_VOLTAGE_18 ? "SEC_VOLTAGE_18" : "??");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reg0x08 = stv0299_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg0x0c = stv0299_readreg (state, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * H/V switching over OP0, OP1 and OP2 are LNB power enable bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg0x0c &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg0x08 = (reg0x08 & 0x3f) | (state->config->lock_output << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (state->config->volt13_op0_op1 == STV0299_VOLT13_OP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg0x0c |= 0x10; /* OP1 off, OP0 on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg0x0c |= 0x40; /* OP1 on, OP0 off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg0x0c |= 0x50; /* OP1 on, OP0 on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* LNB power off! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) reg0x08 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reg0x0c = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (state->config->op0_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) reg0x0c &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) stv0299_writeregI(state, 0x08, reg0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return stv0299_writeregI(state, 0x0c, reg0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int stv0299_send_legacy_dish_cmd (struct dvb_frontend* fe, unsigned long cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 reg0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 reg0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 lv_mask = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 last = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ktime_t nexttime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ktime_t tv[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) reg0x08 = stv0299_readreg (state, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg0x0c = stv0299_readreg (state, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg0x0c &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) stv0299_writeregI (state, 0x08, (reg0x08 & 0x3f) | (state->config->lock_output << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (state->config->volt13_op0_op1 == STV0299_VOLT13_OP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) lv_mask = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cmd = cmd << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (debug_legacy_dish_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) printk ("%s switch command: 0x%04lx\n",__func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) nexttime = ktime_get_boottime();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (debug_legacy_dish_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tv[0] = nexttime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) stv0299_writeregI (state, 0x0c, reg0x0c | 0x50); /* set LNB to 18V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dvb_frontend_sleep_until(&nexttime, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (i=0; i<9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (debug_legacy_dish_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tv[i+1] = ktime_get_boottime();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if((cmd & 0x01) != last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* set voltage to (last ? 13V : 18V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) stv0299_writeregI (state, 0x0c, reg0x0c | (last ? lv_mask : 0x50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) last = (last) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cmd = cmd >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (i != 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dvb_frontend_sleep_until(&nexttime, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (debug_legacy_dish_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) printk ("%s(%d): switch delay (should be 32k followed by all 8k\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) __func__, fe->dvb->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 1; i < 10; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) printk("%d: %d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) (int) ktime_us_delta(tv[i], tv[i-1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int stv0299_init (struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dprintk("stv0299: init chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) stv0299_writeregI(state, 0x02, 0x30 | state->mcr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0; ; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) reg = state->config->inittab[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val = state->config->inittab[i+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (reg == 0xff && val == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (reg == 0x0c && state->config->op0_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (reg == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) state->mcr_reg = val & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) stv0299_writeregI(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int stv0299_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 signal = 0xff - stv0299_readreg (state, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 sync = stv0299_readreg (state, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dprintk ("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (signal > 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *status |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (sync & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *status |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (sync & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *status |= FE_HAS_VITERBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (sync & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *status |= FE_HAS_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if ((sync & 0x98) == 0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *status |= FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int stv0299_read_ber(struct dvb_frontend* fe, u32* ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (state->errmode != STATUS_BER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *ber = stv0299_readreg(state, 0x1e) | (stv0299_readreg(state, 0x1d) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int stv0299_read_signal_strength(struct dvb_frontend* fe, u16* strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) s32 signal = 0xffff - ((stv0299_readreg (state, 0x18) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) | stv0299_readreg (state, 0x19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dprintk ("%s : FE_READ_SIGNAL_STRENGTH : AGC2I: 0x%02x%02x, signal=0x%04x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) stv0299_readreg (state, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) stv0299_readreg (state, 0x19), (int) signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) signal = signal * 5 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *strength = (signal > 0xffff) ? 0xffff : (signal < 0) ? 0 : signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int stv0299_read_snr(struct dvb_frontend* fe, u16* snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) s32 xsnr = 0xffff - ((stv0299_readreg (state, 0x24) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) | stv0299_readreg (state, 0x25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) xsnr = 3 * (xsnr - 0xa100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *snr = (xsnr > 0xffff) ? 0xffff : (xsnr < 0) ? 0 : xsnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int stv0299_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (state->errmode != STATUS_UCBLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) state->ucblocks += stv0299_readreg(state, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) state->ucblocks += (stv0299_readreg(state, 0x1d) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *ucblocks = state->ucblocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int stv0299_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int invval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dprintk ("%s : FE_SET_FRONTEND\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (state->config->set_ts_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) state->config->set_ts_params(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) // set the inversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (p->inversion == INVERSION_OFF) invval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) else if (p->inversion == INVERSION_ON) invval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) printk("stv0299 does not support auto-inversion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (state->config->invert) invval = (~invval) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) stv0299_writeregI(state, 0x0c, (stv0299_readreg(state, 0x0c) & 0xfe) | invval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stv0299_set_FEC(state, p->fec_inner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) stv0299_set_symbolrate(fe, p->symbol_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) stv0299_writeregI(state, 0x22, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) stv0299_writeregI(state, 0x23, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) state->tuner_frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) state->fec_inner = p->fec_inner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) state->symbol_rate = p->symbol_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int stv0299_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) s32 derot_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int invval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) derot_freq = (s32)(s16) ((stv0299_readreg (state, 0x22) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) | stv0299_readreg (state, 0x23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) derot_freq *= (state->config->mclk >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) derot_freq += 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) derot_freq /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) p->frequency += derot_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) invval = stv0299_readreg (state, 0x0c) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (state->config->invert) invval = (~invval) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) p->inversion = invval ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) p->fec_inner = stv0299_get_fec(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) p->symbol_rate = stv0299_get_symbolrate(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int stv0299_sleep(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) stv0299_writeregI(state, 0x02, 0xb0 | state->mcr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) state->initialised = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int stv0299_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) stv0299_writeregI(state, 0x05, 0xb5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) stv0299_writeregI(state, 0x05, 0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int stv0299_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fesettings->min_delay_ms = state->config->min_delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (p->symbol_rate < 10000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fesettings->step_size = p->symbol_rate / 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fesettings->max_drift = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) fesettings->step_size = p->symbol_rate / 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fesettings->max_drift = p->symbol_rate / 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void stv0299_release(struct dvb_frontend* fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct stv0299_state* state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const struct dvb_frontend_ops stv0299_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct dvb_frontend* stv0299_attach(const struct stv0299_config* config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct i2c_adapter* i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct stv0299_state* state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) state = kzalloc(sizeof(struct stv0299_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (state == NULL) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) state->initialised = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) state->tuner_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) state->symbol_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) state->fec_inner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) state->errmode = STATUS_BER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) stv0299_writeregI(state, 0x02, 0x30); /* standby off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) id = stv0299_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* register 0x00 contains 0xa1 for STV0299 and STV0299B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* register 0x00 might contain 0x80 when returning from standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (id != 0xa1 && id != 0x80) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) memcpy(&state->frontend.ops, &stv0299_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct dvb_frontend_ops stv0299_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .delsys = { SYS_DVBS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "ST STV0299 DVB-S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .frequency_min_hz = 950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .frequency_stepsize_hz = 125 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .symbol_rate_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .symbol_rate_max = 45000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .symbol_rate_tolerance = 500, /* ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) FE_CAN_QPSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) FE_CAN_FEC_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .release = stv0299_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .init = stv0299_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .sleep = stv0299_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .write = stv0299_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .i2c_gate_ctrl = stv0299_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .set_frontend = stv0299_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .get_frontend = stv0299_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .get_tune_settings = stv0299_get_tune_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .read_status = stv0299_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .read_ber = stv0299_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .read_signal_strength = stv0299_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .read_snr = stv0299_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .read_ucblocks = stv0299_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .diseqc_send_master_cmd = stv0299_send_diseqc_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .diseqc_send_burst = stv0299_send_diseqc_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .set_tone = stv0299_set_tone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .set_voltage = stv0299_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .dishnetwork_send_legacy_command = stv0299_send_legacy_dish_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) module_param(debug_legacy_dish_switch, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) MODULE_PARM_DESC(debug_legacy_dish_switch, "Enable timing analysis for Dish Network legacy switches");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION("ST STV0299 DVB Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Peter Schildmann, Felix Domke, Andreas Oberritter, Andrew de Quincey, Kenneth Aafly");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) EXPORT_SYMBOL(stv0299_attach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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