Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Driver for STV0297 demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)     Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "stv0297.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct stv0297_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	const struct stv0297_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned long last_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned long base_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define dprintk(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define dprintk(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define STV0297_CLOCK_KHZ   28900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			__func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return (ret != 1) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int stv0297_readreg(struct stv0297_state *state, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			       };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	// this device needs a STOP between the register and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (state->config->stop_during_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	val = stv0297_readreg(state, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	val |= (data & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	stv0297_writereg(state, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				  &reg1,.len = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	// this device needs a STOP between the register and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (state->config->stop_during_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static u32 stv0297_get_symbolrate(struct stv0297_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	tmp = (u64)(stv0297_readreg(state, 0x55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		    | (stv0297_readreg(state, 0x56) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		    | (stv0297_readreg(state, 0x57) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		    | (stv0297_readreg(state, 0x58) << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tmp *= STV0297_CLOCK_KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	tmp >>= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return (u32) tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tmp = 131072L * srate;	/* 131072 = 2^17  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	tmp = tmp / (STV0297_CLOCK_KHZ / 4);	/* 1/4 = 2^-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	tmp = tmp * 8192L;	/* 8192 = 2^13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tmp = (long) fshift *262144L;	/* 262144 = 2*18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	tmp /= symrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	tmp *= 1024;		/* 1024 = 2*10   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	// adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (tmp >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		tmp += 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		tmp -= 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tmp /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	stv0297_writereg(state, 0x60, tmp & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* symrate is hardcoded to 10000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	tmp = offset * 26844L;	/* (2**28)/10000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		tmp += 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	tmp &= 0x0FFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static long stv0297_get_carrieroffset(struct stv0297_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	s64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	stv0297_writereg(state, 0x6B, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	tmp = stv0297_readreg(state, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	tmp |= (stv0297_readreg(state, 0x67) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	tmp |= (stv0297_readreg(state, 0x68) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	tmp *= stv0297_get_symbolrate(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	tmp >>= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return (s32) tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	s32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (freq > 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		freq -= STV0297_CLOCK_KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	tmp = (freq * 1000) / tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (tmp > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		tmp = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	stv0297_writereg(state, 0x21, tmp >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	stv0297_writereg(state, 0x20, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int stv0297_set_qam(struct stv0297_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			   enum fe_modulation modulation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	switch (modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	case QAM_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		val = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	case QAM_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int stv0297_set_inversion(struct stv0297_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				 enum fe_spectral_inversion inversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		stv0297_writereg(state, 0x87, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		stv0297_writereg(state, 0x86, 0xc8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int stv0297_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* load init table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	state->last_ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int stv0297_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	stv0297_writereg_mask(state, 0x80, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int stv0297_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			       enum fe_status *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	u8 sync = stv0297_readreg(state, 0xDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (sync & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		*status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	u8 BER[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	stv0297_readregs(state, 0xA0, BER, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (!(BER[0] & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		state->last_ber = BER[2] << 8 | BER[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	*ber = state->last_ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u8 STRENGTH[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	stv0297_readregs(state, 0x41, STRENGTH, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (STRENGTH[2] & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (tmp < 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			tmp = tmp - 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		if (tmp > 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			tmp = 0x1ff - tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	*strength = (tmp << 7) | (tmp >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	u8 SNR[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	stv0297_readregs(state, 0x07, SNR, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	*snr = SNR[1] << 8 | SNR[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		| stv0297_readreg(state, 0xD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int stv0297_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	int u_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	int initial_u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int blind_u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	int sweeprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	int carrieroffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	enum fe_spectral_inversion inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	case QAM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	case QAM_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		sweeprate = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	case QAM_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		delay = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		sweeprate = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	// determine inversion dependent parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	inversion = p->inversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	carrieroffset = -330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	switch (inversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	case INVERSION_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	case INVERSION_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		sweeprate = -sweeprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		carrieroffset = -carrieroffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	stv0297_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (fe->ops.tuner_ops.set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	/* clear software interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	stv0297_writereg(state, 0x82, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	/* set initial demodulation frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	stv0297_set_initialdemodfreq(state, 7250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	/* setup AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	stv0297_writereg(state, 0x41, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	stv0297_writereg(state, 0x72, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	stv0297_writereg(state, 0x73, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	/* setup STL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	/* disable frequency sweep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	/* reset deinterleaver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	/* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	/* reset equaliser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	u_threshold = stv0297_readreg(state, 0x00) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	initial_u = stv0297_readreg(state, 0x01) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	blind_u = stv0297_readreg(state, 0x01) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	/* data comes from internal A/D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	/* clear phase registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	stv0297_writereg(state, 0x63, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	stv0297_writereg(state, 0x64, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	stv0297_writereg(state, 0x65, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	stv0297_writereg(state, 0x66, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	stv0297_writereg(state, 0x67, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	stv0297_writereg(state, 0x68, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	/* set parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	stv0297_set_qam(state, p->modulation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	stv0297_set_symbolrate(state, p->symbol_rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	stv0297_set_carrieroffset(state, carrieroffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	stv0297_set_inversion(state, inversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	/* kick off lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	/* Disable corner detection for higher QAMs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (p->modulation == QAM_128 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		p->modulation == QAM_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	/* wait for WGAGC lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	timeout = jiffies + msecs_to_jiffies(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		if (stv0297_readreg(state, 0x43) & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		goto timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	/* wait for equaliser partial convergence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	timeout = jiffies + msecs_to_jiffies(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		if (stv0297_readreg(state, 0x82) & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		goto timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	/* wait for equaliser full convergence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	timeout = jiffies + msecs_to_jiffies(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		if (stv0297_readreg(state, 0x82) & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		goto timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	/* disable sweep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	stv0297_writereg_mask(state, 0x6a, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	stv0297_writereg_mask(state, 0x88, 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	/* wait for main lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	timeout = jiffies + msecs_to_jiffies(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		if (stv0297_readreg(state, 0xDF) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		goto timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	/* is it still locked after that delay? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		goto timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	/* success!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	state->base_freq = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int stv0297_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 				struct dtv_frontend_properties *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	int reg_00, reg_83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	reg_00 = stv0297_readreg(state, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	reg_83 = stv0297_readreg(state, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	p->frequency = state->base_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	if (state->config->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 		p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	p->fec_inner = FEC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	switch ((reg_00 >> 4) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		p->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		p->modulation = QAM_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		p->modulation = QAM_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		p->modulation = QAM_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 		p->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void stv0297_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	struct stv0297_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct dvb_frontend_ops stv0297_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 				    struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	struct stv0297_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	/* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	/* setup the state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	state->last_ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	state->base_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	/* check if the demod is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 	/* create dvb_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 	state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const struct dvb_frontend_ops stv0297_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	.delsys = { SYS_DVBC_ANNEX_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 		 .name = "ST STV0297 DVB-C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 		 .frequency_min_hz = 47 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 		 .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 		 .frequency_stepsize_hz = 62500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 		 .symbol_rate_min = 870000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 		 .symbol_rate_max = 11700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 		 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 		 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	.release = stv0297_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	.init = stv0297_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	.sleep = stv0297_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	.i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 	.set_frontend = stv0297_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	.get_frontend = stv0297_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	.read_status = stv0297_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	.read_ber = stv0297_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 	.read_signal_strength = stv0297_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	.read_snr = stv0297_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	.read_ucblocks = stv0297_read_ucblocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) EXPORT_SYMBOL(stv0297_attach);