^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) STB0899 Multistandard Frontend driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) Manu Abraham (abraham.manu@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __STB0899_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __STB0899_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* S1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STB0899_DEV_ID 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STB0899_CHIP_ID (0x0f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STB0899_OFFST_CHIP_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STB0899_WIDTH_CHIP_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STB0899_CHIP_REL (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STB0899_OFFST_CHIP_REL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STB0899_WIDTH_CHIP_REL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STB0899_DEMOD 0xf40e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STB0899_MODECOEFF (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STB0899_OFFST_MODECOEFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STB0899_WIDTH_MODECOEFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STB0899_RCOMPC 0xf410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STB0899_AGC1CN 0xf412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STB0899_AGC1REF 0xf413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STB0899_RTC 0xf417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STB0899_TMGCFG 0xf418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STB0899_AGC2REF 0xf419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STB0899_TLSR 0xf41a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STB0899_CFD 0xf41b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STB0899_CFD_ON (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STB0899_OFFST_CFD_ON 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STB0899_WIDTH_CFD_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STB0899_ACLC 0xf41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STB0899_BCLC 0xf41d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STB0899_OFFST_ALGO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STB0899_WIDTH_ALGO_QPSK2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STB0899_ALGO_QPSK2 (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STB0899_ALGO_QPSK1 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STB0899_ALGO_BPSK (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STB0899_OFFST_BETA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STB0899_WIDTH_BETA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STB0899_EQON 0xf41e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STB0899_LDT 0xf41f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STB0899_LDT2 0xf420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STB0899_EQUALREF 0xf425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STB0899_TMGRAMP 0xf426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STB0899_TMGTHD 0xf427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STB0899_IDCCOMP 0xf428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STB0899_QDCCOMP 0xf429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STB0899_POWERI 0xf42a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STB0899_POWERQ 0xf42b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STB0899_RCOMP 0xf42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STB0899_AGCIQIN 0xf42e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STB0899_AGCIQVALUE (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STB0899_OFFST_AGCIQVALUE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STB0899_WIDTH_AGCIQVALUE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STB0899_AGC2I1 0xf436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STB0899_AGC2I2 0xf437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STB0899_TLIR 0xf438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STB0899_TLIR_TMG_LOCK_IND (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STB0899_OFFST_TLIR_TMG_LOCK_IND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STB0899_WIDTH_TLIR_TMG_LOCK_IND 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STB0899_RTF 0xf439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STB0899_RTF_TIMING_LOOP_FREQ (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STB0899_OFFST_RTF_TIMING_LOOP_FREQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STB0899_WIDTH_RTF_TIMING_LOOP_FREQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STB0899_DSTATUS 0xf43a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STB0899_CARRIER_FOUND (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STB0899_OFFST_CARRIER_FOUND 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STB0899_WIDTH_CARRIER_FOUND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STB0899_TMG_LOCK (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STB0899_OFFST_TMG_LOCK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STB0899_WIDTH_TMG_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STB0899_DEMOD_LOCK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STB0899_OFFST_DEMOD_LOCK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STB0899_WIDTH_DEMOD_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STB0899_TMG_AUTO (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STB0899_OFFST_TMG_AUTO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STB0899_WIDTH_TMG_AUTO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STB0899_END_MAIN (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STB0899_OFFST_END_MAIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STB0899_WIDTH_END_MAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STB0899_LDI 0xf43b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STB0899_OFFST_LDI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STB0899_WIDTH_LDI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STB0899_CFRM 0xf43e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STB0899_OFFST_CFRM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STB0899_WIDTH_CFRM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STB0899_CFRL 0xf43f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STB0899_OFFST_CFRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STB0899_WIDTH_CFRL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STB0899_NIRM 0xf440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STB0899_OFFST_NIRM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define STB0899_WIDTH_NIRM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STB0899_NIRL 0xf441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STB0899_OFFST_NIRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STB0899_WIDTH_NIRL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STB0899_ISYMB 0xf444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STB0899_QSYMB 0xf445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STB0899_SFRH 0xf446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STB0899_OFFST_SFRH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STB0899_WIDTH_SFRH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define STB0899_SFRM 0xf447
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define STB0899_OFFST_SFRM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define STB0899_WIDTH_SFRM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STB0899_SFRL 0xf448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define STB0899_OFFST_SFRL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STB0899_WIDTH_SFRL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define STB0899_SFRUPH 0xf44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define STB0899_SFRUPM 0xf44d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define STB0899_SFRUPL 0xf44e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define STB0899_EQUAI1 0xf4e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define STB0899_EQUAQ1 0xf4e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define STB0899_EQUAI2 0xf4e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define STB0899_EQUAQ2 0xf4e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define STB0899_EQUAI3 0xf4e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define STB0899_EQUAQ3 0xf4e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define STB0899_EQUAI4 0xf4e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define STB0899_EQUAQ4 0xf4e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define STB0899_EQUAI5 0xf4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define STB0899_EQUAQ5 0xf4e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define STB0899_DSTATUS2 0xf50c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define STB0899_DS2_TMG_AUTOSRCH (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define STB8999_OFFST_DS2_TMG_AUTOSRCH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define STB0899_WIDTH_DS2_TMG_AUTOSRCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STB0899_DS2_END_MAINLOOP (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define STB0899_OFFST_DS2_END_MAINLOOP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define STB0899_WIDTH_DS2_END_MAINLOOP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define STB0899_DS2_CFSYNC (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define STB0899_OFFST_DS2_CFSYNC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define STB0899_WIDTH_DS2_CFSYNC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define STB0899_DS2_TMGLOCK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define STB0899_OFFST_DS2_TMGLOCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define STB0899_WIDTH_DS2_TMGLOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define STB0899_DS2_DEMODWAIT (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define STB0899_OFFST_DS2_DEMODWAIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define STB0899_WIDTH_DS2_DEMODWAIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define STB0899_DS2_FECON (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define STB0899_OFFST_DS2_FECON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define STB0899_WIDTH_DS2_FECON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* S1 FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define STB0899_VSTATUS 0xf50d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define STB0899_VSTATUS_VITERBI_ON (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define STB0899_OFFST_VSTATUS_VITERBI_ON 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define STB0899_WIDTH_VSTATUS_VITERBI_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define STB0899_VSTATUS_END_LOOPVIT (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define STB0899_OFFST_VSTATUS_END_LOOPVIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define STB0899_WIDTH_VSTATUS_END_LOOPVIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define STB0899_VSTATUS_PRFVIT (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define STB0899_OFFST_VSTATUS_PRFVIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define STB0899_WIDTH_VSTATUS_PRFVIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define STB0899_VSTATUS_LOCKEDVIT (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define STB0899_OFFST_VSTATUS_LOCKEDVIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define STB0899_WIDTH_VSTATUS_LOCKEDVIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define STB0899_VERROR 0xf50f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define STB0899_IQSWAP 0xf523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define STB0899_SYM (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define STB0899_OFFST_SYM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define STB0899_WIDTH_SYM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define STB0899_FECAUTO1 0xf530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define STB0899_DSSSRCH (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define STB0899_OFFST_DSSSRCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define STB0899_WIDTH_DSSSRCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define STB0899_SYMSRCH (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define STB0899_OFFST_SYMSRCH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define STB0899_WIDTH_SYMSRCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define STB0899_QPSKSRCH (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define STB0899_OFFST_QPSKSRCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define STB0899_WIDTH_QPSKSRCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define STB0899_BPSKSRCH (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define STB0899_OFFST_BPSKSRCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define STB0899_WIDTH_BPSKSRCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define STB0899_FECM 0xf533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define STB0899_FECM_NOT_DVB (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define STB0899_OFFST_FECM_NOT_DVB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define STB0899_WIDTH_FECM_NOT_DVB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define STB0899_FECM_RSVD1 (0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define STB0899_OFFST_FECM_RSVD1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define STB0899_WIDTH_FECM_RSVD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define STB0899_FECM_VITERBI_ON (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define STB0899_OFFST_FECM_VITERBI_ON 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define STB0899_WIDTH_FECM_VITERBI_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define STB0899_FECM_RSVD0 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define STB0899_OFFST_FECM_RSVD0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define STB0899_WIDTH_FECM_RSVD0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define STB0899_FECM_SYNCDIS (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define STB0899_OFFST_FECM_SYNCDIS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define STB0899_WIDTH_FECM_SYNCDIS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define STB0899_FECM_SYMI (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define STB0899_OFFST_FECM_SYMI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define STB0899_WIDTH_FECM_SYMI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define STB0899_VTH12 0xf534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define STB0899_VTH23 0xf535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define STB0899_VTH34 0xf536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define STB0899_VTH56 0xf537
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define STB0899_VTH67 0xf538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define STB0899_VTH78 0xf539
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define STB0899_PRVIT 0xf53c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define STB0899_PR_7_8 (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define STB0899_OFFST_PR_7_8 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define STB0899_WIDTH_PR_7_8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define STB0899_PR_6_7 (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define STB0899_OFFST_PR_6_7 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define STB0899_WIDTH_PR_6_7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define STB0899_PR_5_6 (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define STB0899_OFFST_PR_5_6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define STB0899_WIDTH_PR_5_6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define STB0899_PR_3_4 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define STB0899_OFFST_PR_3_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define STB0899_WIDTH_PR_3_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define STB0899_PR_2_3 (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define STB0899_OFFST_PR_2_3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define STB0899_WIDTH_PR_2_3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define STB0899_PR_1_2 (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STB0899_OFFST_PR_1_2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STB0899_WIDTH_PR_1_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STB0899_VITSYNC 0xf53d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define STB0899_AM (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STB0899_OFFST_AM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define STB0899_WIDTH_AM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STB0899_FREEZE (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define STB0899_OFFST_FREEZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define STB0899_WIDTH_FREEZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define STB0899_SN_65536 (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define STB0899_OFFST_SN_65536 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define STB0899_WIDTH_SN_65536 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define STB0899_SN_16384 (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define STB0899_OFFST_SN_16384 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define STB0899_WIDTH_SN_16384 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define STB0899_SN_4096 (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define STB0899_OFFST_SN_4096 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define STB0899_WIDTH_SN_4096 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define STB0899_SN_1024 (0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define STB0899_OFFST_SN_1024 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define STB0899_WIDTH_SN_1024 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define STB0899_TO_128 (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define STB0899_OFFST_TO_128 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define STB0899_WIDTH_TO_128 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define STB0899_TO_64 (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define STB0899_OFFST_TO_64 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define STB0899_WIDTH_TO_64 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define STB0899_TO_32 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define STB0899_OFFST_TO_32 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define STB0899_WIDTH_TO_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define STB0899_TO_16 (0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define STB0899_OFFST_TO_16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define STB0899_WIDTH_TO_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define STB0899_HYST_128 (0x03 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define STB0899_OFFST_HYST_128 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define STB0899_WIDTH_HYST_128 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define STB0899_HYST_64 (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define STB0899_OFFST_HYST_64 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define STB0899_WIDTH_HYST_64 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define STB0899_HYST_32 (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define STB0899_OFFST_HYST_32 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define STB0899_WIDTH_HYST_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define STB0899_HYST_16 (0x00 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define STB0899_OFFST_HYST_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define STB0899_WIDTH_HYST_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define STB0899_RSULC 0xf548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define STB0899_ULDIL_ON (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define STB0899_OFFST_ULDIL_ON 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define STB0899_WIDTH_ULDIL_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define STB0899_ULAUTO_ON (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define STB0899_OFFST_ULAUTO_ON 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define STB0899_WIDTH_ULAUTO_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define STB0899_ULRS_ON (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define STB0899_OFFST_ULRS_ON 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define STB0899_WIDTH_ULRS_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define STB0899_ULDESCRAM_ON (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define STB0899_OFFST_ULDESCRAM_ON 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define STB0899_WIDTH_ULDESCRAM_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define STB0899_UL_DISABLE (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define STB0899_OFFST_UL_DISABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define STB0899_WIDTH_UL_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define STB0899_NOFTHRESHOLD (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define STB0899_OFFST_NOFTHRESHOLD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define STB0899_WIDTH_NOFTHRESHOLD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define STB0899_RSLLC 0xf54a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define STB0899_DEMAPVIT 0xf583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define STB0899_DEMAPVIT_RSVD (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define STB0899_OFFST_DEMAPVIT_RSVD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define STB0899_WIDTH_DEMAPVIT_RSVD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define STB0899_DEMAPVIT_KDIVIDER (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define STB0899_OFFST_DEMAPVIT_KDIVIDER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define STB0899_WIDTH_DEMAPVIT_KDIVIDER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define STB0899_PLPARM 0xf58c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define STB0899_VITMAPPING (0x07 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define STB0899_OFFST_VITMAPPING 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define STB0899_WIDTH_VITMAPPING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define STB0899_VITMAPPING_BPSK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define STB0899_OFFST_VITMAPPING_BPSK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define STB0899_WIDTH_VITMAPPING_BPSK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define STB0899_VITMAPPING_QPSK (0x00 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define STB0899_OFFST_VITMAPPING_QPSK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define STB0899_WIDTH_VITMAPPING_QPSK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define STB0899_VITCURPUN (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define STB0899_OFFST_VITCURPUN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define STB0899_WIDTH_VITCURPUN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define STB0899_VITCURPUN_1_2 (0x0d << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define STB0899_VITCURPUN_2_3 (0x12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define STB0899_VITCURPUN_3_4 (0x15 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define STB0899_VITCURPUN_5_6 (0x18 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define STB0899_VITCURPUN_6_7 (0x19 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define STB0899_VITCURPUN_7_8 (0x1a << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* S2 DEMOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define STB0899_OFF0_DMD_STATUS 0xf300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define STB0899_BASE_DMD_STATUS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define STB0899_IF_AGC_LOCK (0x01 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define STB0899_OFFST_IF_AGC_LOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define STB0899_WIDTH_IF_AGC_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define STB0899_OFF0_CRL_FREQ 0xf304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define STB0899_BASE_CRL_FREQ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define STB0899_CARR_FREQ (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define STB0899_OFFST_CARR_FREQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define STB0899_WIDTH_CARR_FREQ 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define STB0899_OFF0_BTR_FREQ 0xf308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define STB0899_BASE_BTR_FREQ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define STB0899_BTR_FREQ (0xfffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define STB0899_OFFST_BTR_FREQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define STB0899_WIDTH_BTR_FREQ 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define STB0899_OFF0_IF_AGC_GAIN 0xf30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define STB0899_BASE_IF_AGC_GAIN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define STB0899_IF_AGC_GAIN (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define STB0899_OFFST_IF_AGC_GAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define STB0899_WIDTH_IF_AGC_GAIN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define STB0899_OFF0_BB_AGC_GAIN 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define STB0899_BASE_BB_AGC_GAIN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define STB0899_BB_AGC_GAIN (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define STB0899_OFFST_BB_AGC_GAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define STB0899_WIDTH_BB_AGC_GAIN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define STB0899_OFF0_DC_OFFSET 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define STB0899_BASE_DC_OFFSET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define STB0899_I (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define STB0899_OFFST_I 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define STB0899_WIDTH_I 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define STB0899_Q (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define STB0899_OFFST_Q 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define STB0899_WIDTH_Q 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define STB0899_OFF0_DMD_CNTRL 0xf31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define STB0899_BASE_DMD_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define STB0899_ADC0_PINS1IN (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define STB0899_OFFST_ADC0_PINS1IN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define STB0899_WIDTH_ADC0_PINS1IN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define STB0899_IN2COMP1_OFFBIN0 (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define STB0899_OFFST_IN2COMP1_OFFBIN0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define STB0899_WIDTH_IN2COMP1_OFFBIN0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define STB0899_DC_COMP (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define STB0899_OFFST_DC_COMP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define STB0899_WIDTH_DC_COMP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define STB0899_MODMODE (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define STB0899_OFFST_MODMODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define STB0899_WIDTH_MODMODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define STB0899_OFF0_IF_AGC_CNTRL 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define STB0899_BASE_IF_AGC_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define STB0899_IF_GAIN_INIT (0x3fff << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define STB0899_OFFST_IF_GAIN_INIT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define STB0899_WIDTH_IF_GAIN_INIT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define STB0899_IF_GAIN_SENSE (0x01 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define STB0899_OFFST_IF_GAIN_SENSE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define STB0899_WIDTH_IF_GAIN_SENSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define STB0899_IF_LOOP_GAIN (0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define STB0899_OFFST_IF_LOOP_GAIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define STB0899_WIDTH_IF_LOOP_GAIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define STB0899_IF_LD_GAIN_INIT (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define STB0899_OFFST_IF_LD_GAIN_INIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define STB0899_WIDTH_IF_LD_GAIN_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define STB0899_IF_AGC_REF (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define STB0899_OFFST_IF_AGC_REF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define STB0899_WIDTH_IF_AGC_REF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define STB0899_OFF0_BB_AGC_CNTRL 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define STB0899_BASE_BB_AGC_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define STB0899_BB_GAIN_INIT (0x3fff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define STB0899_OFFST_BB_GAIN_INIT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define STB0899_WIDTH_BB_GAIN_INIT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define STB0899_BB_LOOP_GAIN (0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define STB0899_OFFST_BB_LOOP_GAIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define STB0899_WIDTH_BB_LOOP_GAIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define STB0899_BB_LD_GAIN_INIT (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define STB0899_OFFST_BB_LD_GAIN_INIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define STB0899_WIDTH_BB_LD_GAIN_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define STB0899_BB_AGC_REF (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define STB0899_OFFST_BB_AGC_REF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define STB0899_WIDTH_BB_AGC_REF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define STB0899_OFF0_CRL_CNTRL 0xf328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define STB0899_BASE_CRL_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define STB0899_CRL_LOCK_CLEAR (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define STB0899_OFFST_CRL_LOCK_CLEAR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define STB0899_WIDTH_CRL_LOCK_CLEAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define STB0899_CRL_SWPR_CLEAR (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define STB0899_OFFST_CRL_SWPR_CLEAR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define STB0899_WIDTH_CRL_SWPR_CLEAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define STB0899_CRL_SWP_ENA (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define STB0899_OFFST_CRL_SWP_ENA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define STB0899_WIDTH_CRL_SWP_ENA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define STB0899_CRL_DET_SEL (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define STB0899_OFFST_CRL_DET_SEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define STB0899_WIDTH_CRL_DET_SEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define STB0899_CRL_SENSE (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define STB0899_OFFST_CRL_SENSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define STB0899_WIDTH_CRL_SENSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define STB0899_CRL_PHSERR_CLEAR (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define STB0899_OFFST_CRL_PHSERR_CLEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define STB0899_WIDTH_CRL_PHSERR_CLEAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define STB0899_OFF0_CRL_PHS_INIT 0xf32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define STB0899_BASE_CRL_PHS_INIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define STB0899_CRL_PHS_INIT_31 (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define STB0899_OFFST_CRL_PHS_INIT_31 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define STB0899_WIDTH_CRL_PHS_INIT_31 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define STB0899_CRL_LD_INIT_PHASE (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define STB0899_OFFST_CRL_LD_INIT_PHASE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define STB0899_WIDTH_CRL_LD_INIT_PHASE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define STB0899_CRL_INIT_PHASE (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define STB0899_OFFST_CRL_INIT_PHASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define STB0899_WIDTH_CRL_INIT_PHASE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define STB0899_OFF0_CRL_FREQ_INIT 0xf330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define STB0899_BASE_CRL_FREQ_INIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define STB0899_CRL_FREQ_INIT_31 (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define STB0899_OFFST_CRL_FREQ_INIT_31 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define STB0899_WIDTH_CRL_FREQ_INIT_31 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define STB0899_CRL_LD_FREQ_INIT (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define STB0899_OFFST_CRL_LD_FREQ_INIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define STB0899_WIDTH_CRL_LD_FREQ_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define STB0899_CRL_FREQ_INIT (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define STB0899_OFFST_CRL_FREQ_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define STB0899_WIDTH_CRL_FREQ_INIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define STB0899_OFF0_CRL_LOOP_GAIN 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define STB0899_BASE_CRL_LOOP_GAIN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define STB0899_KCRL2_RSHFT (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define STB0899_OFFST_KCRL2_RSHFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define STB0899_WIDTH_KCRL2_RSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define STB0899_KCRL1 (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define STB0899_OFFST_KCRL1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define STB0899_WIDTH_KCRL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define STB0899_KCRL1_RSHFT (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define STB0899_OFFST_KCRL1_RSHFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define STB0899_WIDTH_KCRL1_RSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define STB0899_KCRL0 (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define STB0899_OFFST_KCRL0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define STB0899_WIDTH_KCRL0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define STB0899_KCRL0_RSHFT (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define STB0899_OFFST_KCRL0_RSHFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define STB0899_WIDTH_KCRL0_RSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define STB0899_OFF0_CRL_NOM_FREQ 0xf338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define STB0899_BASE_CRL_NOM_FREQ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define STB0899_CRL_NOM_FREQ (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define STB0899_OFFST_CRL_NOM_FREQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define STB0899_WIDTH_CRL_NOM_FREQ 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define STB0899_OFF0_CRL_SWP_RATE 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define STB0899_BASE_CRL_SWP_RATE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define STB0899_CRL_SWP_RATE (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define STB0899_OFFST_CRL_SWP_RATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define STB0899_WIDTH_CRL_SWP_RATE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define STB0899_OFF0_CRL_MAX_SWP 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define STB0899_BASE_CRL_MAX_SWP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define STB0899_CRL_MAX_SWP (0x3fffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define STB0899_OFFST_CRL_MAX_SWP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define STB0899_WIDTH_CRL_MAX_SWP 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define STB0899_OFF0_CRL_LK_CNTRL 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define STB0899_BASE_CRL_LK_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define STB0899_OFF0_DECIM_CNTRL 0xf348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define STB0899_BASE_DECIM_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define STB0899_BAND_LIMIT_B (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define STB0899_OFFST_BAND_LIMIT_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define STB0899_WIDTH_BAND_LIMIT_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define STB0899_WIN_SEL (0x03 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define STB0899_OFFST_WIN_SEL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define STB0899_WIDTH_WIN_SEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define STB0899_DECIM_RATE (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define STB0899_OFFST_DECIM_RATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define STB0899_WIDTH_DECIM_RATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define STB0899_OFF0_BTR_CNTRL 0xf34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define STB0899_BASE_BTR_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define STB0899_BTR_FREQ_CORR (0x7ff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define STB0899_OFFST_BTR_FREQ_CORR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define STB0899_WIDTH_BTR_FREQ_CORR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define STB0899_BTR_CLR_LOCK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define STB0899_OFFST_BTR_CLR_LOCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define STB0899_WIDTH_BTR_CLR_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define STB0899_BTR_SENSE (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define STB0899_OFFST_BTR_SENSE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define STB0899_WIDTH_BTR_SENSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define STB0899_BTR_ERR_ENA (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define STB0899_OFFST_BTR_ERR_ENA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define STB0899_WIDTH_BTR_ERR_ENA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define STB0899_INTRP_PHS_SENSE (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define STB0899_OFFST_INTRP_PHS_SENSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define STB0899_WIDTH_INTRP_PHS_SENSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define STB0899_OFF0_BTR_LOOP_GAIN 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define STB0899_BASE_BTR_LOOP_GAIN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define STB0899_KBTR2_RSHFT (0x0f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define STB0899_OFFST_KBTR2_RSHFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define STB0899_WIDTH_KBTR2_RSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define STB0899_KBTR1 (0x0f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define STB0899_OFFST_KBTR1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define STB0899_WIDTH_KBTR1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define STB0899_KBTR1_RSHFT (0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define STB0899_OFFST_KBTR1_RSHFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define STB0899_WIDTH_KBTR1_RSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define STB0899_KBTR0 (0x0f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define STB0899_OFFST_KBTR0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define STB0899_WIDTH_KBTR0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define STB0899_KBTR0_RSHFT (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define STB0899_OFFST_KBTR0_RSHFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define STB0899_WIDTH_KBTR0_RSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define STB0899_OFF0_BTR_PHS_INIT 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define STB0899_BASE_BTR_PHS_INIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define STB0899_BTR_LD_PHASE_INIT (0x01 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define STB0899_OFFST_BTR_LD_PHASE_INIT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define STB0899_WIDTH_BTR_LD_PHASE_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define STB0899_BTR_INIT_PHASE (0xfffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define STB0899_OFFST_BTR_INIT_PHASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define STB0899_WIDTH_BTR_INIT_PHASE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define STB0899_OFF0_BTR_FREQ_INIT 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define STB0899_BASE_BTR_FREQ_INIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define STB0899_BTR_LD_FREQ_INIT (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define STB0899_OFFST_BTR_LD_FREQ_INIT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define STB0899_WIDTH_BTR_LD_FREQ_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define STB0899_BTR_FREQ_INIT (0xfffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define STB0899_OFFST_BTR_FREQ_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define STB0899_WIDTH_BTR_FREQ_INIT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define STB0899_OFF0_BTR_NOM_FREQ 0xf35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define STB0899_BASE_BTR_NOM_FREQ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define STB0899_BTR_NOM_FREQ (0xfffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define STB0899_OFFST_BTR_NOM_FREQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define STB0899_WIDTH_BTR_NOM_FREQ 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define STB0899_OFF0_BTR_LK_CNTRL 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define STB0899_BASE_BTR_LK_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define STB0899_BTR_MIN_ENERGY (0x0f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define STB0899_OFFST_BTR_MIN_ENERGY 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define STB0899_WIDTH_BTR_MIN_ENERGY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define STB0899_BTR_LOCK_TH_LO (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define STB0899_OFFST_BTR_LOCK_TH_LO 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define STB0899_WIDTH_BTR_LOCK_TH_LO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define STB0899_BTR_LOCK_TH_HI (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define STB0899_OFFST_BTR_LOCK_TH_HI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define STB0899_WIDTH_BTR_LOCK_TH_HI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define STB0899_BTR_LOCK_GAIN (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define STB0899_OFFST_BTR_LOCK_GAIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define STB0899_WIDTH_BTR_LOCK_GAIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define STB0899_BTR_LOCK_LEAK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define STB0899_OFFST_BTR_LOCK_LEAK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define STB0899_WIDTH_BTR_LOCK_LEAK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define STB0899_OFF0_DECN_CNTRL 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define STB0899_BASE_DECN_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define STB0899_OFF0_TP_CNTRL 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define STB0899_BASE_TP_CNTRL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define STB0899_OFF0_TP_BUF_STATUS 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define STB0899_BASE_TP_BUF_STATUS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define STB0899_TP_BUFFER_FULL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define STB0899_OFF0_DC_ESTIM 0xf37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define STB0899_BASE_DC_ESTIM 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define STB0899_I_DC_ESTIMATE (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define STB0899_OFFST_I_DC_ESTIMATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define STB0899_WIDTH_I_DC_ESTIMATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define STB0899_Q_DC_ESTIMATE (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define STB0899_OFFST_Q_DC_ESTIMATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define STB0899_WIDTH_Q_DC_ESTIMATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define STB0899_OFF0_FLL_CNTRL 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define STB0899_BASE_FLL_CNTRL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define STB0899_CRL_FLL_ACC (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define STB0899_OFFST_CRL_FLL_ACC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define STB0899_WIDTH_CRL_FLL_ACC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define STB0899_FLL_AVG_PERIOD (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define STB0899_OFFST_FLL_AVG_PERIOD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define STB0899_WIDTH_FLL_AVG_PERIOD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define STB0899_OFF0_FLL_FREQ_WD 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define STB0899_BASE_FLL_FREQ_WD 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define STB0899_FLL_FREQ_WD (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define STB0899_OFFST_FLL_FREQ_WD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define STB0899_WIDTH_FLL_FREQ_WD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define STB0899_OFF0_ANTI_ALIAS_SEL 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define STB0899_BASE_ANTI_ALIAS_SEL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define STB0899_ANTI_ALIAS_SELB (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define STB0899_OFFST_ANTI_ALIAS_SELB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define STB0899_WIDTH_ANTI_ALIAS_SELB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define STB0899_OFF0_RRC_ALPHA 0xf35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define STB0899_BASE_RRC_ALPHA 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define STB0899_RRC_ALPHA (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define STB0899_OFFST_RRC_ALPHA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define STB0899_WIDTH_RRC_ALPHA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define STB0899_OFF0_DC_ADAPT_LSHFT 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define STB0899_BASE_DC_ADAPT_LSHFT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define STB0899_DC_ADAPT_LSHFT (0x077 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define STB0899_OFFST_DC_ADAPT_LSHFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define STB0899_WIDTH_DC_ADAPT_LSHFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define STB0899_OFF0_IMB_OFFSET 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define STB0899_BASE_IMB_OFFSET 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define STB0899_PHS_IMB_COMP (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define STB0899_OFFST_PHS_IMB_COMP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define STB0899_WIDTH_PHS_IMB_COMP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define STB0899_AMPL_IMB_COMP (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define STB0899_OFFST_AMPL_IMB_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define STB0899_WIDTH_AMPL_IMB_COMP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define STB0899_OFF0_IMB_ESTIMATE 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define STB0899_BASE_IMB_ESTIMATE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define STB0899_PHS_IMB_ESTIMATE (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define STB0899_OFFST_PHS_IMB_ESTIMATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define STB0899_WIDTH_PHS_IMB_ESTIMATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define STB0899_AMPL_IMB_ESTIMATE (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define STB0899_OFFST_AMPL_IMB_ESTIMATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define STB0899_WIDTH_AMPL_IMB_ESTIMATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define STB0899_OFF0_IMB_CNTRL 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define STB0899_BASE_IMB_CNTRL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define STB0899_PHS_ADAPT_LSHFT (0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define STB0899_OFFST_PHS_ADAPT_LSHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define STB0899_WIDTH_PHS_ADAPT_LSHFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define STB0899_AMPL_ADAPT_LSHFT (0x07 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define STB0899_OFFST_AMPL_ADAPT_LSHFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define STB0899_WIDTH_AMPL_ADAPT_LSHFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define STB0899_IMB_COMP (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define STB0899_OFFST_IMB_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define STB0899_WIDTH_IMB_COMP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define STB0899_OFF0_IF_AGC_CNTRL2 0xf374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define STB0899_BASE_IF_AGC_CNTRL2 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define STB0899_IF_AGC_LOCK_TH (0xff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define STB0899_OFFST_IF_AGC_LOCK_TH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define STB0899_WIDTH_IF_AGC_LOCK_TH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define STB0899_IF_AGC_SD_DIV (0xff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define STB0899_OFFST_IF_AGC_SD_DIV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define STB0899_WIDTH_IF_AGC_SD_DIV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define STB0899_IF_AGC_DUMP_PER (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define STB0899_OFFST_IF_AGC_DUMP_PER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define STB0899_WIDTH_IF_AGC_DUMP_PER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define STB0899_OFF0_DMD_CNTRL2 0xf378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define STB0899_BASE_DMD_CNTRL2 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define STB0899_SPECTRUM_INVERT (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define STB0899_OFFST_SPECTRUM_INVERT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define STB0899_WIDTH_SPECTRUM_INVERT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define STB0899_AGC_MODE (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define STB0899_OFFST_AGC_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define STB0899_WIDTH_AGC_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define STB0899_CRL_FREQ_ADJ (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define STB0899_OFFST_CRL_FREQ_ADJ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define STB0899_WIDTH_CRL_FREQ_ADJ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define STB0899_OFF0_TP_BUFFER 0xf300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define STB0899_BASE_TP_BUFFER 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define STB0899_TP_BUFFER_IN (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define STB0899_OFFST_TP_BUFFER_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define STB0899_WIDTH_TP_BUFFER_IN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define STB0899_OFF0_TP_BUFFER1 0xf304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define STB0899_BASE_TP_BUFFER1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define STB0899_OFF0_TP_BUFFER2 0xf308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define STB0899_BASE_TP_BUFFER2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define STB0899_OFF0_TP_BUFFER3 0xf30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define STB0899_BASE_TP_BUFFER3 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define STB0899_OFF0_TP_BUFFER4 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define STB0899_BASE_TP_BUFFER4 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define STB0899_OFF0_TP_BUFFER5 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define STB0899_BASE_TP_BUFFER5 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define STB0899_OFF0_TP_BUFFER6 0xf318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define STB0899_BASE_TP_BUFFER6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define STB0899_OFF0_TP_BUFFER7 0xf31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define STB0899_BASE_TP_BUFFER7 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define STB0899_OFF0_TP_BUFFER8 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define STB0899_BASE_TP_BUFFER8 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define STB0899_OFF0_TP_BUFFER9 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define STB0899_BASE_TP_BUFFER9 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define STB0899_OFF0_TP_BUFFER10 0xf328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define STB0899_BASE_TP_BUFFER10 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define STB0899_OFF0_TP_BUFFER11 0xf32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define STB0899_BASE_TP_BUFFER11 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define STB0899_OFF0_TP_BUFFER12 0xf330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define STB0899_BASE_TP_BUFFER12 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define STB0899_OFF0_TP_BUFFER13 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define STB0899_BASE_TP_BUFFER13 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define STB0899_OFF0_TP_BUFFER14 0xf338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define STB0899_BASE_TP_BUFFER14 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define STB0899_OFF0_TP_BUFFER15 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define STB0899_BASE_TP_BUFFER15 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define STB0899_OFF0_TP_BUFFER16 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define STB0899_BASE_TP_BUFFER16 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define STB0899_OFF0_TP_BUFFER17 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define STB0899_BASE_TP_BUFFER17 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define STB0899_OFF0_TP_BUFFER18 0xf348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define STB0899_BASE_TP_BUFFER18 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define STB0899_OFF0_TP_BUFFER19 0xf34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define STB0899_BASE_TP_BUFFER19 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define STB0899_OFF0_TP_BUFFER20 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define STB0899_BASE_TP_BUFFER20 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define STB0899_OFF0_TP_BUFFER21 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define STB0899_BASE_TP_BUFFER21 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define STB0899_OFF0_TP_BUFFER22 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define STB0899_BASE_TP_BUFFER22 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define STB0899_OFF0_TP_BUFFER23 0xf35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define STB0899_BASE_TP_BUFFER23 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define STB0899_OFF0_TP_BUFFER24 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define STB0899_BASE_TP_BUFFER24 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define STB0899_OFF0_TP_BUFFER25 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define STB0899_BASE_TP_BUFFER25 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define STB0899_OFF0_TP_BUFFER26 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define STB0899_BASE_TP_BUFFER26 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define STB0899_OFF0_TP_BUFFER27 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define STB0899_BASE_TP_BUFFER27 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define STB0899_OFF0_TP_BUFFER28 0xf370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define STB0899_BASE_TP_BUFFER28 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define STB0899_OFF0_TP_BUFFER29 0xf374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define STB0899_BASE_TP_BUFFER29 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define STB0899_OFF0_TP_BUFFER30 0xf378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define STB0899_BASE_TP_BUFFER30 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define STB0899_OFF0_TP_BUFFER31 0xf37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define STB0899_BASE_TP_BUFFER31 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define STB0899_OFF0_TP_BUFFER32 0xf300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define STB0899_BASE_TP_BUFFER32 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define STB0899_OFF0_TP_BUFFER33 0xf304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define STB0899_BASE_TP_BUFFER33 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define STB0899_OFF0_TP_BUFFER34 0xf308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define STB0899_BASE_TP_BUFFER34 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define STB0899_OFF0_TP_BUFFER35 0xf30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define STB0899_BASE_TP_BUFFER35 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define STB0899_OFF0_TP_BUFFER36 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define STB0899_BASE_TP_BUFFER36 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define STB0899_OFF0_TP_BUFFER37 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define STB0899_BASE_TP_BUFFER37 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define STB0899_OFF0_TP_BUFFER38 0xf318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define STB0899_BASE_TP_BUFFER38 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define STB0899_OFF0_TP_BUFFER39 0xf31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define STB0899_BASE_TP_BUFFER39 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define STB0899_OFF0_TP_BUFFER40 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define STB0899_BASE_TP_BUFFER40 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define STB0899_OFF0_TP_BUFFER41 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define STB0899_BASE_TP_BUFFER41 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define STB0899_OFF0_TP_BUFFER42 0xf328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define STB0899_BASE_TP_BUFFER42 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define STB0899_OFF0_TP_BUFFER43 0xf32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define STB0899_BASE_TP_BUFFER43 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define STB0899_OFF0_TP_BUFFER44 0xf330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define STB0899_BASE_TP_BUFFER44 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define STB0899_OFF0_TP_BUFFER45 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define STB0899_BASE_TP_BUFFER45 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define STB0899_OFF0_TP_BUFFER46 0xf338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define STB0899_BASE_TP_BUFFER46 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define STB0899_OFF0_TP_BUFFER47 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define STB0899_BASE_TP_BUFFER47 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define STB0899_OFF0_TP_BUFFER48 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define STB0899_BASE_TP_BUFFER48 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define STB0899_OFF0_TP_BUFFER49 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define STB0899_BASE_TP_BUFFER49 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define STB0899_OFF0_TP_BUFFER50 0xf348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define STB0899_BASE_TP_BUFFER50 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define STB0899_OFF0_TP_BUFFER51 0xf34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define STB0899_BASE_TP_BUFFER51 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define STB0899_OFF0_TP_BUFFER52 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define STB0899_BASE_TP_BUFFER52 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define STB0899_OFF0_TP_BUFFER53 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define STB0899_BASE_TP_BUFFER53 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define STB0899_OFF0_TP_BUFFER54 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define STB0899_BASE_TP_BUFFER54 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define STB0899_OFF0_TP_BUFFER55 0xf35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define STB0899_BASE_TP_BUFFER55 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define STB0899_OFF0_TP_BUFFER56 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define STB0899_BASE_TP_BUFFER56 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define STB0899_OFF0_TP_BUFFER57 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define STB0899_BASE_TP_BUFFER57 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define STB0899_OFF0_TP_BUFFER58 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define STB0899_BASE_TP_BUFFER58 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define STB0899_OFF0_TP_BUFFER59 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define STB0899_BASE_TP_BUFFER59 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define STB0899_OFF0_TP_BUFFER60 0xf370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define STB0899_BASE_TP_BUFFER60 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define STB0899_OFF0_TP_BUFFER61 0xf374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define STB0899_BASE_TP_BUFFER61 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define STB0899_OFF0_TP_BUFFER62 0xf378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define STB0899_BASE_TP_BUFFER62 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define STB0899_OFF0_TP_BUFFER63 0xf37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define STB0899_BASE_TP_BUFFER63 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define STB0899_OFF0_RESET_CNTRL 0xf300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define STB0899_BASE_RESET_CNTRL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define STB0899_DVBS2_RESET (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define STB0899_OFFST_DVBS2_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define STB0899_WIDTH_DVBS2_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define STB0899_OFF0_ACM_ENABLE 0xf304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define STB0899_BASE_ACM_ENABLE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define STB0899_ACM_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define STB0899_OFF0_DESCR_CNTRL 0xf30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define STB0899_BASE_DESCR_CNTRL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define STB0899_OFFST_DESCR_CNTRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define STB0899_WIDTH_DESCR_CNTRL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define STB0899_OFF0_UWP_CNTRL1 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define STB0899_BASE_UWP_CNTRL1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define STB0899_UWP_TH_SOF (0x7fff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define STB0899_OFFST_UWP_TH_SOF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define STB0899_WIDTH_UWP_TH_SOF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define STB0899_UWP_ESN0_QUANT (0xff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define STB0899_OFFST_UWP_ESN0_QUANT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define STB0899_WIDTH_UWP_ESN0_QUANT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define STB0899_UWP_ESN0_AVE (0x03 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define STB0899_OFFST_UWP_ESN0_AVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define STB0899_WIDTH_UWP_ESN0_AVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define STB0899_UWP_START (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define STB0899_OFFST_UWP_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define STB0899_WIDTH_UWP_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define STB0899_OFF0_UWP_CNTRL2 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define STB0899_BASE_UWP_CNTRL2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define STB0899_UWP_MISS_TH (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define STB0899_OFFST_UWP_MISS_TH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define STB0899_WIDTH_UWP_MISS_TH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define STB0899_FE_FINE_TRK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define STB0899_OFFST_FE_FINE_TRK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define STB0899_WIDTH_FE_FINE_TRK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define STB0899_FE_COARSE_TRK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define STB0899_OFFST_FE_COARSE_TRK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define STB0899_WIDTH_FE_COARSE_TRK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define STB0899_OFF0_UWP_STAT1 0xf328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define STB0899_BASE_UWP_STAT1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define STB0899_UWP_STATE (0x03ff << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define STB0899_OFFST_UWP_STATE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define STB0899_WIDTH_UWP_STATE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define STB0899_UW_MAX_PEAK (0x7fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define STB0899_OFFST_UW_MAX_PEAK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define STB0899_WIDTH_UW_MAX_PEAK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define STB0899_OFF0_UWP_STAT2 0xf32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define STB0899_BASE_UWP_STAT2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define STB0899_ESNO_EST (0x07ffff << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define STB0899_OFFST_ESN0_EST 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define STB0899_WIDTH_ESN0_EST 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define STB0899_UWP_DECODE_MOD (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define STB0899_OFFST_UWP_DECODE_MOD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define STB0899_WIDTH_UWP_DECODE_MOD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define STB0899_OFF0_DMD_CORE_ID 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define STB0899_BASE_DMD_CORE_ID 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define STB0899_CORE_ID (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define STB0899_OFFST_CORE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define STB0899_WIDTH_CORE_ID 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define STB0899_OFF0_DMD_VERSION_ID 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define STB0899_BASE_DMD_VERSION_ID 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define STB0899_VERSION_ID (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define STB0899_OFFST_VERSION_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define STB0899_WIDTH_VERSION_ID 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define STB0899_OFF0_DMD_STAT2 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define STB0899_BASE_DMD_STAT2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define STB0899_CSM_LOCK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define STB0899_OFFST_CSM_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define STB0899_WIDTH_CSM_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define STB0899_UWP_LOCK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define STB0899_OFFST_UWP_LOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define STB0899_WIDTH_UWP_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define STB0899_OFF0_FREQ_ADJ_SCALE 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define STB0899_BASE_FREQ_ADJ_SCALE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define STB0899_FREQ_ADJ_SCALE (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define STB0899_OFFST_FREQ_ADJ_SCALE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define STB0899_WIDTH_FREQ_ADJ_SCALE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define STB0899_OFF0_UWP_CNTRL3 0xf34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define STB0899_BASE_UWP_CNTRL3 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define STB0899_UWP_TH_TRACK (0x7fff << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define STB0899_OFFST_UWP_TH_TRACK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define STB0899_WIDTH_UWP_TH_TRACK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define STB0899_UWP_TH_ACQ (0x7fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define STB0899_OFFST_UWP_TH_ACQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define STB0899_WIDTH_UWP_TH_ACQ 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define STB0899_OFF0_SYM_CLK_SEL 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define STB0899_BASE_SYM_CLK_SEL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define STB0899_SYM_CLK_SEL (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define STB0899_OFFST_SYM_CLK_SEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define STB0899_WIDTH_SYM_CLK_SEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define STB0899_OFF0_SOF_SRCH_TO 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define STB0899_BASE_SOF_SRCH_TO 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define STB0899_SOF_SEARCH_TIMEOUT (0x3fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define STB0899_OFFST_SOF_SEARCH_TIMEOUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define STB0899_WIDTH_SOF_SEARCH_TIMEOUT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define STB0899_OFF0_ACQ_CNTRL1 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define STB0899_BASE_ACQ_CNTRL1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define STB0899_FE_FINE_ACQ (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define STB0899_OFFST_FE_FINE_ACQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define STB0899_WIDTH_FE_FINE_ACQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define STB0899_FE_COARSE_ACQ (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define STB0899_OFFST_FE_COARSE_ACQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define STB0899_WIDTH_FE_COARSE_ACQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define STB0899_OFF0_ACQ_CNTRL2 0xf35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define STB0899_BASE_ACQ_CNTRL2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define STB0899_ZIGZAG (0x01 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define STB0899_OFFST_ZIGZAG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define STB0899_WIDTH_ZIGZAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define STB0899_NUM_STEPS (0xff << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define STB0899_OFFST_NUM_STEPS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define STB0899_WIDTH_NUM_STEPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define STB0899_FREQ_STEPSIZE (0x1ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define STB0899_OFFST_FREQ_STEPSIZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define STB0899_WIDTH_FREQ_STEPSIZE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define STB0899_OFF0_ACQ_CNTRL3 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define STB0899_BASE_ACQ_CNTRL3 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define STB0899_THRESHOLD_SCL (0x3f << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define STB0899_OFFST_THRESHOLD_SCL 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define STB0899_WIDTH_THRESHOLD_SCL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define STB0899_UWP_TH_SRCH (0x7fff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define STB0899_OFFST_UWP_TH_SRCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define STB0899_WIDTH_UWP_TH_SRCH 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define STB0899_AUTO_REACQUIRE (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define STB0899_OFFST_AUTO_REACQUIRE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define STB0899_WIDTH_AUTO_REACQUIRE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define STB0899_TRACK_LOCK_SEL (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define STB0899_OFFST_TRACK_LOCK_SEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define STB0899_WIDTH_TRACK_LOCK_SEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define STB0899_ACQ_SEARCH_MODE (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define STB0899_OFFST_ACQ_SEARCH_MODE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define STB0899_WIDTH_ACQ_SEARCH_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define STB0899_CONFIRM_FRAMES (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define STB0899_OFFST_CONFIRM_FRAMES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define STB0899_WIDTH_CONFIRM_FRAMES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define STB0899_OFF0_FE_SETTLE 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define STB0899_BASE_FE_SETTLE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define STB0899_SETTLING_TIME (0x3fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define STB0899_OFFST_SETTLING_TIME 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define STB0899_WIDTH_SETTLING_TIME 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define STB0899_OFF0_AC_DWELL 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define STB0899_BASE_AC_DWELL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define STB0899_DWELL_TIME (0x3fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define STB0899_OFFST_DWELL_TIME 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define STB0899_WIDTH_DWELL_TIME 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define STB0899_OFF0_ACQUIRE_TRIG 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define STB0899_BASE_ACQUIRE_TRIG 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define STB0899_ACQUIRE (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define STB0899_OFFST_ACQUIRE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define STB0899_WIDTH_ACQUIRE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define STB0899_OFF0_LOCK_LOST 0xf370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define STB0899_BASE_LOCK_LOST 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define STB0899_LOCK_LOST (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define STB0899_OFFST_LOCK_LOST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define STB0899_WIDTH_LOCK_LOST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define STB0899_OFF0_ACQ_STAT1 0xf374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define STB0899_BASE_ACQ_STAT1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define STB0899_STEP_FREQ (0x1fffff << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define STB0899_OFFST_STEP_FREQ 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define STB0899_WIDTH_STEP_FREQ 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define STB0899_ACQ_STATE (0x07 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define STB0899_OFFST_ACQ_STATE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define STB0899_WIDTH_ACQ_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define STB0899_UW_DETECT_COUNT (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define STB0899_OFFST_UW_DETECT_COUNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define STB0899_WIDTH_UW_DETECT_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define STB0899_OFF0_ACQ_TIMEOUT 0xf378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define STB0899_BASE_ACQ_TIMEOUT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define STB0899_ACQ_TIMEOUT (0x3fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define STB0899_OFFST_ACQ_TIMEOUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define STB0899_WIDTH_ACQ_TIMEOUT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define STB0899_OFF0_ACQ_TIME 0xf37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define STB0899_BASE_ACQ_TIME 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define STB0899_ACQ_TIME_SYM (0xffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define STB0899_OFFST_ACQ_TIME_SYM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define STB0899_WIDTH_ACQ_TIME_SYM 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define STB0899_OFF0_FINAL_AGC_CNTRL 0xf308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define STB0899_BASE_FINAL_AGC_CNTRL 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define STB0899_FINAL_GAIN_INIT (0x3fff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define STB0899_OFFST_FINAL_GAIN_INIT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define STB0899_WIDTH_FINAL_GAIN_INIT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define STB0899_FINAL_LOOP_GAIN (0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define STB0899_OFFST_FINAL_LOOP_GAIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define STB0899_WIDTH_FINAL_LOOP_GAIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define STB0899_FINAL_LD_GAIN_INIT (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define STB0899_OFFST_FINAL_LD_GAIN_INIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define STB0899_WIDTH_FINAL_LD_GAIN_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define STB0899_FINAL_AGC_REF (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define STB0899_OFFST_FINAL_AGC_REF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define STB0899_WIDTH_FINAL_AGC_REF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define STB0899_OFF0_FINAL_AGC_GAIN 0xf30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define STB0899_BASE_FINAL_AGC_GAIN 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define STB0899_FINAL_AGC_GAIN (0x3fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define STB0899_OFFST_FINAL_AGC_GAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define STB0899_WIDTH_FINAL_AGC_GAIN 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define STB0899_OFF0_EQUALIZER_INIT 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define STB0899_BASE_EQUALIZER_INIT 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define STB0899_EQ_SRST (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define STB0899_OFFST_EQ_SRST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define STB0899_WIDTH_EQ_SRST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define STB0899_EQ_INIT (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define STB0899_OFFST_EQ_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define STB0899_WIDTH_EQ_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define STB0899_OFF0_EQ_CNTRL 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define STB0899_BASE_EQ_CNTRL 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define STB0899_EQ_ADAPT_MODE (0x01 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define STB0899_OFFST_EQ_ADAPT_MODE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define STB0899_WIDTH_EQ_ADAPT_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define STB0899_EQ_DELAY (0x0f << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define STB0899_OFFST_EQ_DELAY 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define STB0899_WIDTH_EQ_DELAY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define STB0899_EQ_QUANT_LEVEL (0xff << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define STB0899_OFFST_EQ_QUANT_LEVEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define STB0899_WIDTH_EQ_QUANT_LEVEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define STB0899_EQ_DISABLE_UPDATE (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define STB0899_OFFST_EQ_DISABLE_UPDATE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define STB0899_WIDTH_EQ_DISABLE_UPDATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define STB0899_EQ_BYPASS (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define STB0899_OFFST_EQ_BYPASS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define STB0899_WIDTH_EQ_BYPASS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define STB0899_EQ_SHIFT (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define STB0899_OFFST_EQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define STB0899_WIDTH_EQ_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define STB0899_OFF0_EQ_I_INIT_COEFF_0 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define STB0899_OFF1_EQ_I_INIT_COEFF_1 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define STB0899_OFF2_EQ_I_INIT_COEFF_2 0xf328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define STB0899_OFF3_EQ_I_INIT_COEFF_3 0xf32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define STB0899_OFF4_EQ_I_INIT_COEFF_4 0xf330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define STB0899_OFF5_EQ_I_INIT_COEFF_5 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define STB0899_OFF6_EQ_I_INIT_COEFF_6 0xf338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define STB0899_OFF7_EQ_I_INIT_COEFF_7 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define STB0899_OFF8_EQ_I_INIT_COEFF_8 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define STB0899_OFF9_EQ_I_INIT_COEFF_9 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define STB0899_OFFa_EQ_I_INIT_COEFF_10 0xf348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define STB0899_BASE_EQ_I_INIT_COEFF_N 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define STB0899_EQ_I_INIT_COEFF_N (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define STB0899_OFFST_EQ_I_INIT_COEFF_N 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define STB0899_WIDTH_EQ_I_INIT_COEFF_N 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define STB0899_OFF0_EQ_Q_INIT_COEFF_0 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define STB0899_OFF1_EQ_Q_INIT_COEFF_1 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define STB0899_OFF2_EQ_Q_INIT_COEFF_2 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define STB0899_OFF3_EQ_Q_INIT_COEFF_3 0xf35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define STB0899_OFF4_EQ_Q_INIT_COEFF_4 0xf360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define STB0899_OFF5_EQ_Q_INIT_COEFF_5 0xf364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define STB0899_OFF6_EQ_Q_INIT_COEFF_6 0xf368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define STB0899_OFF7_EQ_Q_INIT_COEFF_7 0xf36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define STB0899_OFF8_EQ_Q_INIT_COEFF_8 0xf370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define STB0899_OFF9_EQ_Q_INIT_COEFF_9 0xf374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define STB0899_OFFa_EQ_Q_INIT_COEFF_10 0xf378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define STB0899_BASE_EQ_Q_INIT_COEFF_N 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define STB0899_EQ_Q_INIT_COEFF_N (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define STB0899_OFFST_EQ_Q_INIT_COEFF_N 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define STB0899_WIDTH_EQ_Q_INIT_COEFF_N 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define STB0899_OFF0_EQ_I_OUT_COEFF_0 0xf300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define STB0899_OFF1_EQ_I_OUT_COEFF_1 0xf304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define STB0899_OFF2_EQ_I_OUT_COEFF_2 0xf308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define STB0899_OFF3_EQ_I_OUT_COEFF_3 0xf30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define STB0899_OFF4_EQ_I_OUT_COEFF_4 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define STB0899_OFF5_EQ_I_OUT_COEFF_5 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define STB0899_OFF6_EQ_I_OUT_COEFF_6 0xf318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define STB0899_OFF7_EQ_I_OUT_COEFF_7 0xf31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define STB0899_OFF8_EQ_I_OUT_COEFF_8 0xf320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define STB0899_OFF9_EQ_I_OUT_COEFF_9 0xf324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define STB0899_OFFa_EQ_I_OUT_COEFF_10 0xf328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define STB0899_BASE_EQ_I_OUT_COEFF_N 0x00000460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define STB0899_EQ_I_OUT_COEFF_N (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define STB0899_OFFST_EQ_I_OUT_COEFF_N 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define STB0899_WIDTH_EQ_I_OUT_COEFF_N 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define STB0899_OFF0_EQ_Q_OUT_COEFF_0 0xf330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define STB0899_OFF1_EQ_Q_OUT_COEFF_1 0xf334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define STB0899_OFF2_EQ_Q_OUT_COEFF_2 0xf338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define STB0899_OFF3_EQ_Q_OUT_COEFF_3 0xf33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define STB0899_OFF4_EQ_Q_OUT_COEFF_4 0xf340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define STB0899_OFF5_EQ_Q_OUT_COEFF_5 0xf344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define STB0899_OFF6_EQ_Q_OUT_COEFF_6 0xf348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define STB0899_OFF7_EQ_Q_OUT_COEFF_7 0xf34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define STB0899_OFF8_EQ_Q_OUT_COEFF_8 0xf350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define STB0899_OFF9_EQ_Q_OUT_COEFF_9 0xf354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define STB0899_OFFa_EQ_Q_OUT_COEFF_10 0xf358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define STB0899_BASE_EQ_Q_OUT_COEFF_N 0x00000460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define STB0899_EQ_Q_OUT_COEFF_N (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define STB0899_OFFST_EQ_Q_OUT_COEFF_N 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define STB0899_WIDTH_EQ_Q_OUT_COEFF_N 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* S2 FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define STB0899_OFF0_BLOCK_LNGTH 0xfa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define STB0899_BASE_BLOCK_LNGTH 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define STB0899_BLOCK_LENGTH (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define STB0899_OFFST_BLOCK_LENGTH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define STB0899_WIDTH_BLOCK_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define STB0899_OFF0_ROW_STR 0xfa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define STB0899_BASE_ROW_STR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define STB0899_ROW_STRIDE (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define STB0899_OFFST_ROW_STRIDE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define STB0899_WIDTH_ROW_STRIDE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define STB0899_OFF0_MAX_ITER 0xfa0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define STB0899_BASE_MAX_ITER 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define STB0899_MAX_ITERATIONS (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define STB0899_OFFST_MAX_ITERATIONS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define STB0899_WIDTH_MAX_ITERATIONS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define STB0899_OFF0_BN_END_ADDR 0xfa10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define STB0899_BASE_BN_END_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define STB0899_BN_END_ADDR (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define STB0899_OFFST_BN_END_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define STB0899_WIDTH_BN_END_ADDR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define STB0899_OFF0_CN_END_ADDR 0xfa14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define STB0899_BASE_CN_END_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define STB0899_CN_END_ADDR (0x0fff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define STB0899_OFFST_CN_END_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define STB0899_WIDTH_CN_END_ADDR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define STB0899_OFF0_INFO_LENGTH 0xfa1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define STB0899_BASE_INFO_LENGTH 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define STB0899_INFO_LENGTH (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define STB0899_OFFST_INFO_LENGTH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define STB0899_WIDTH_INFO_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define STB0899_OFF0_BOT_ADDR 0xfa20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define STB0899_BASE_BOT_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define STB0899_BOTTOM_BASE_ADDR (0x03ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define STB0899_OFFST_BOTTOM_BASE_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define STB0899_WIDTH_BOTTOM_BASE_ADDR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define STB0899_OFF0_BCH_BLK_LN 0xfa24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define STB0899_BASE_BCH_BLK_LN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define STB0899_BCH_BLOCK_LENGTH (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define STB0899_OFFST_BCH_BLOCK_LENGTH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define STB0899_WIDTH_BCH_BLOCK_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define STB0899_OFF0_BCH_T 0xfa28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define STB0899_BASE_BCH_T 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define STB0899_BCH_T (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define STB0899_OFFST_BCH_T 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define STB0899_WIDTH_BCH_T 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define STB0899_OFF0_CNFG_MODE 0xfa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define STB0899_BASE_CNFG_MODE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define STB0899_MODCOD (0x1f << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define STB0899_OFFST_MODCOD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define STB0899_WIDTH_MODCOD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define STB0899_MODCOD_SEL (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define STB0899_OFFST_MODCOD_SEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define STB0899_WIDTH_MODCOD_SEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define STB0899_CONFIG_MODE (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define STB0899_OFFST_CONFIG_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define STB0899_WIDTH_CONFIG_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define STB0899_OFF0_LDPC_STAT 0xfa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define STB0899_BASE_LDPC_STAT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define STB0899_ITERATION (0xff << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define STB0899_OFFST_ITERATION 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define STB0899_WIDTH_ITERATION 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define STB0899_LDPC_DEC_STATE (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define STB0899_OFFST_LDPC_DEC_STATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define STB0899_WIDTH_LDPC_DEC_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define STB0899_OFF0_ITER_SCALE 0xfa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define STB0899_BASE_ITER_SCALE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define STB0899_ITERATION_SCALE (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define STB0899_OFFST_ITERATION_SCALE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define STB0899_WIDTH_ITERATION_SCALE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define STB0899_OFF0_INPUT_MODE 0xfa0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define STB0899_BASE_INPUT_MODE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define STB0899_SD_BLOCK1_STREAM0 (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define STB0899_OFFST_SD_BLOCK1_STREAM0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define STB0899_WIDTH_SD_BLOCK1_STREAM0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define STB0899_OFF0_LDPCDECRST 0xfa10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define STB0899_BASE_LDPCDECRST 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define STB0899_LDPC_DEC_RST (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define STB0899_OFFST_LDPC_DEC_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define STB0899_WIDTH_LDPC_DEC_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define STB0899_OFF0_CLK_PER_BYTE_RW 0xfa14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define STB0899_BASE_CLK_PER_BYTE_RW 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define STB0899_CLKS_PER_BYTE (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define STB0899_OFFST_CLKS_PER_BYTE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define STB0899_WIDTH_CLKS_PER_BYTE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define STB0899_OFF0_BCH_ERRORS 0xfa18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define STB0899_BASE_BCH_ERRORS 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define STB0899_BCH_ERRORS (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define STB0899_OFFST_BCH_ERRORS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define STB0899_WIDTH_BCH_ERRORS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define STB0899_OFF0_LDPC_ERRORS 0xfa1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define STB0899_BASE_LDPC_ERRORS 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define STB0899_LDPC_ERRORS (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define STB0899_OFFST_LDPC_ERRORS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define STB0899_WIDTH_LDPC_ERRORS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define STB0899_OFF0_BCH_MODE 0xfa20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define STB0899_BASE_BCH_MODE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define STB0899_BCH_CORRECT_N (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define STB0899_OFFST_BCH_CORRECT_N 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define STB0899_WIDTH_BCH_CORRECT_N 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define STB0899_FULL_BYPASS (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define STB0899_OFFST_FULL_BYPASS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define STB0899_WIDTH_FULL_BYPASS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define STB0899_OFF0_ERR_ACC_PER 0xfa24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define STB0899_BASE_ERR_ACC_PER 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define STB0899_BCH_ERR_ACC_PERIOD (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define STB0899_OFFST_BCH_ERR_ACC_PERIOD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define STB0899_WIDTH_BCH_ERR_ACC_PERIOD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define STB0899_OFF0_BCH_ERR_ACC 0xfa28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define STB0899_BASE_BCH_ERR_ACC 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define STB0899_BCH_ERR_ACCUM (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define STB0899_OFFST_BCH_ERR_ACCUM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define STB0899_WIDTH_BCH_ERR_ACCUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define STB0899_OFF0_FEC_CORE_ID_REG 0xfa2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define STB0899_BASE_FEC_CORE_ID_REG 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define STB0899_FEC_CORE_ID (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define STB0899_OFFST_FEC_CORE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define STB0899_WIDTH_FEC_CORE_ID 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define STB0899_OFF0_FEC_VER_ID_REG 0xfa34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define STB0899_BASE_FEC_VER_ID_REG 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define STB0899_FEC_VER_ID (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define STB0899_OFFST_FEC_VER_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define STB0899_WIDTH_FEC_VER_ID 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define STB0899_OFF0_FEC_TP_SEL 0xfa38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define STB0899_BASE_FEC_TP_SEL 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define STB0899_OFF0_CSM_CNTRL1 0xf310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define STB0899_BASE_CSM_CNTRL1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define STB0899_CSM_FORCE_FREQLOCK (0x01 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define STB0899_OFFST_CSM_FORCE_FREQLOCK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define STB0899_WIDTH_CSM_FORCE_FREQLOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define STB0899_CSM_FREQ_LOCKSTATE (0x01 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define STB0899_OFFST_CSM_FREQ_LOCKSTATE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define STB0899_WIDTH_CSM_FREQ_LOCKSTATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define STB0899_CSM_AUTO_PARAM (0x01 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define STB0899_OFFST_CSM_AUTO_PARAM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define STB0899_WIDTH_CSM_AUTO_PARAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define STB0899_FE_LOOP_SHIFT (0x07 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define STB0899_OFFST_FE_LOOP_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define STB0899_WIDTH_FE_LOOP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define STB0899_CSM_AGC_SHIFT (0x07 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define STB0899_OFFST_CSM_AGC_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define STB0899_WIDTH_CSM_AGC_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define STB0899_CSM_AGC_GAIN (0x1ff << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define STB0899_OFFST_CSM_AGC_GAIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define STB0899_WIDTH_CSM_AGC_GAIN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define STB0899_CSM_TWO_PASS (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define STB0899_OFFST_CSM_TWO_PASS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define STB0899_WIDTH_CSM_TWO_PASS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define STB0899_CSM_DVT_TABLE (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define STB0899_OFFST_CSM_DVT_TABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define STB0899_WIDTH_CSM_DVT_TABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define STB0899_OFF0_CSM_CNTRL2 0xf314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define STB0899_BASE_CSM_CNTRL2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define STB0899_CSM_GAMMA_RHO_ACQ (0x1ff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define STB0899_OFFST_CSM_GAMMA_RHOACQ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define STB0899_WIDTH_CSM_GAMMA_RHOACQ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define STB0899_CSM_GAMMA_ACQ (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define STB0899_OFFST_CSM_GAMMA_ACQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define STB0899_WIDTH_CSM_GAMMA_ACQ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define STB0899_OFF0_CSM_CNTRL3 0xf318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define STB0899_BASE_CSM_CNTRL3 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define STB0899_CSM_GAMMA_RHO_TRACK (0x1ff << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define STB0899_OFFST_CSM_GAMMA_RHOTRACK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define STB0899_WIDTH_CSM_GAMMA_RHOTRACK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define STB0899_CSM_GAMMA_TRACK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define STB0899_OFFST_CSM_GAMMA_TRACK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define STB0899_WIDTH_CSM_GAMMA_TRACK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define STB0899_OFF0_CSM_CNTRL4 0xf31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define STB0899_BASE_CSM_CNTRL4 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define STB0899_CSM_PHASEDIFF_THRESH (0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define STB0899_OFFST_CSM_PHASEDIFF_THRESH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define STB0899_WIDTH_CSM_PHASEDIFF_THRESH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define STB0899_CSM_LOCKCOUNT_THRESH (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define STB0899_OFFST_CSM_LOCKCOUNT_THRESH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define STB0899_WIDTH_CSM_LOCKCOUNT_THRESH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* Check on chapter 8 page 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define STB0899_ERRCTRL1 0xf574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define STB0899_ERRCTRL2 0xf575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define STB0899_ERRCTRL3 0xf576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define STB0899_ERR_SRC_S1 (0x1f << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define STB0899_OFFST_ERR_SRC_S1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define STB0899_WIDTH_ERR_SRC_S1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define STB0899_ERR_SRC_S2 (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define STB0899_OFFST_ERR_SRC_S2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define STB0899_WIDTH_ERR_SRC_S2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define STB0899_NOE (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define STB0899_OFFST_NOE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define STB0899_WIDTH_NOE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define STB0899_ECNT1M 0xf524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define STB0899_ECNT1L 0xf525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define STB0899_ECNT2M 0xf526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define STB0899_ECNT2L 0xf527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define STB0899_ECNT3M 0xf528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define STB0899_ECNT3L 0xf529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define STB0899_DMONMSK1 0xf57b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define STB0899_DMONMSK1_WAIT_1STEP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define STB0899_DMONMSK1_FREE_14 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define STB0899_DMONMSK1_AVRGVIT_CALC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define STB0899_DMONMSK1_FREE_12 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define STB0899_DMONMSK1_FREE_11 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define STB0899_DMONMSK1_B0DIV_CALC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define STB0899_DMONMSK1_KDIVB1_CALC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define STB0899_DMONMSK1_KDIVB2_CALC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define STB0899_DMONMSK0 0xf57c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define STB0899_DMONMSK0_SMOTTH_CALC (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define STB0899_DMONMSK0_FREE_6 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define STB0899_DMONMSK0_SIGPOWER_CALC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define STB0899_DMONMSK0_QSEUIL_CALC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define STB0899_DMONMSK0_FREE_3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define STB0899_DMONMSK0_FREE_2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define STB0899_DMONMSK0_KVDIVB1_CALC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define STB0899_DMONMSK0_KVDIVB2_CALC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define STB0899_TSULC 0xf549
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define STB0899_ULNOSYNCBYTES (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define STB0899_OFFST_ULNOSYNCBYTES 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define STB0899_WIDTH_ULNOSYNCBYTES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define STB0899_ULPARITY_ON (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define STB0899_OFFST_ULPARITY_ON 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define STB0899_WIDTH_ULPARITY_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define STB0899_ULSYNCOUTRS (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define STB0899_OFFST_ULSYNCOUTRS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define STB0899_WIDTH_ULSYNCOUTRS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define STB0899_ULDSS_PACKETS (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define STB0899_OFFST_ULDSS_PACKETS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define STB0899_WIDTH_ULDSS_PACKETS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define STB0899_TSLPL 0xf54b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define STB0899_LLDVBS2_MODE (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define STB0899_OFFST_LLDVBS2_MODE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define STB0899_WIDTH_LLDVBS2_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define STB0899_LLISSYI_ON (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define STB0899_OFFST_LLISSYI_ON 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define STB0899_WIDTH_LLISSYI_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define STB0899_LLNPD_ON (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define STB0899_OFFST_LLNPD_ON 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define STB0899_WIDTH_LLNPD_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define STB0899_LLCRC8_ON (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define STB0899_OFFST_LLCRC8_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define STB0899_WIDTH_LLCRC8_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define STB0899_TSCFGH 0xf54c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define STB0899_OUTRS_PS (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define STB0899_OFFST_OUTRS_PS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define STB0899_WIDTH_OUTRS_PS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define STB0899_SYNCBYTE (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define STB0899_OFFST_SYNCBYTE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define STB0899_WIDTH_SYNCBYTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define STB0899_PFBIT (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define STB0899_OFFST_PFBIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define STB0899_WIDTH_PFBIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define STB0899_ERR_BIT (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define STB0899_OFFST_ERR_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define STB0899_WIDTH_ERR_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define STB0899_MPEG (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define STB0899_OFFST_MPEG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define STB0899_WIDTH_MPEG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define STB0899_CLK_POL (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define STB0899_OFFST_CLK_POL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define STB0899_WIDTH_CLK_POL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define STB0899_FORCE0 (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define STB0899_OFFST_FORCE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define STB0899_WIDTH_FORCE0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define STB0899_TSCFGM 0xf54d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define STB0899_LLPRIORITY (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define STB0899_OFFST_LLPRIORIY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define STB0899_WIDTH_LLPRIORITY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define STB0899_EN188 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define STB0899_OFFST_EN188 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define STB0899_WIDTH_EN188 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define STB0899_TSCFGL 0xf54e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define STB0899_DEL_ERRPCK (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define STB0899_OFFST_DEL_ERRPCK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define STB0899_WIDTH_DEL_ERRPCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define STB0899_ERRFLAGSTD (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define STB0899_OFFST_ERRFLAGSTD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define STB0899_WIDTH_ERRFLAGSTD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define STB0899_MPEGERR (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define STB0899_OFFST_MPEGERR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define STB0899_WIDTH_MPEGERR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define STB0899_BCH_CHK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define STB0899_OFFST_BCH_CHK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define STB0899_WIDTH_BCH_CHK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define STB0899_CRC8CHK (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define STB0899_OFFST_CRC8CHK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define STB0899_WIDTH_CRC8CHK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define STB0899_SPEC_INFO (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define STB0899_OFFST_SPEC_INFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define STB0899_WIDTH_SPEC_INFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define STB0899_LOW_PRIO_CLK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define STB0899_OFFST_LOW_PRIO_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define STB0899_WIDTH_LOW_PRIO_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define STB0899_ERROR_NORM (0x00 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define STB0899_OFFST_ERROR_NORM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define STB0899_WIDTH_ERROR_NORM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define STB0899_TSOUT 0xf54f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define STB0899_RSSYNCDEL 0xf550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define STB0899_TSINHDELH 0xf551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define STB0899_TSINHDELM 0xf552
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define STB0899_TSINHDELL 0xf553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define STB0899_TSLLSTKM 0xf55a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define STB0899_TSLLSTKL 0xf55b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define STB0899_TSULSTKM 0xf55c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define STB0899_TSULSTKL 0xf55d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define STB0899_TSSTATUS 0xf561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define STB0899_PDELCTRL 0xf600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define STB0899_INVERT_RES (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define STB0899_OFFST_INVERT_RES 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define STB0899_WIDTH_INVERT_RES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define STB0899_FORCE_ACCEPTED (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define STB0899_OFFST_FORCE_ACCEPTED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define STB0899_WIDTH_FORCE_ACCEPTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define STB0899_FILTER_EN (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define STB0899_OFFST_FILTER_EN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define STB0899_WIDTH_FILTER_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define STB0899_LOCKFALL_THRESH (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define STB0899_OFFST_LOCKFALL_THRESH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define STB0899_WIDTH_LOCKFALL_THRESH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define STB0899_HYST_EN (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define STB0899_OFFST_HYST_EN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define STB0899_WIDTH_HYST_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define STB0899_HYST_SWRST (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define STB0899_OFFST_HYST_SWRST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define STB0899_WIDTH_HYST_SWRST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define STB0899_ALGO_EN (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define STB0899_OFFST_ALGO_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define STB0899_WIDTH_ALGO_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define STB0899_ALGO_SWRST (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define STB0899_OFFST_ALGO_SWRST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define STB0899_WIDTH_ALGO_SWRST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define STB0899_PDELCTRL2 0xf601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define STB0899_BBHCTRL1 0xf602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define STB0899_BBHCTRL2 0xf603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define STB0899_HYSTTHRESH 0xf604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define STB0899_MATCSTM 0xf605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define STB0899_MATCSTL 0xf606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define STB0899_UPLCSTM 0xf607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define STB0899_UPLCSTL 0xf608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define STB0899_DFLCSTM 0xf609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define STB0899_DFLCSTL 0xf60a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define STB0899_SYNCCST 0xf60b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define STB0899_SYNCDCSTM 0xf60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define STB0899_SYNCDCSTL 0xf60d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define STB0899_ISI_ENTRY 0xf60e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define STB0899_ISI_BIT_EN 0xf60f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define STB0899_MATSTRM 0xf610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define STB0899_MATSTRL 0xf611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define STB0899_UPLSTRM 0xf612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define STB0899_UPLSTRL 0xf613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define STB0899_DFLSTRM 0xf614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define STB0899_DFLSTRL 0xf615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define STB0899_SYNCSTR 0xf616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define STB0899_SYNCDSTRM 0xf617
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define STB0899_SYNCDSTRL 0xf618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define STB0899_CFGPDELSTATUS1 0xf619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define STB0899_BADDFL (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define STB0899_OFFST_BADDFL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define STB0899_WIDTH_BADDFL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define STB0899_CONTINUOUS_STREAM (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define STB0899_OFFST_CONTINUOUS_STREAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define STB0899_WIDTH_CONTINUOUS_STREAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define STB0899_ACCEPTED_STREAM (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define STB0899_OFFST_ACCEPTED_STREAM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define STB0899_WIDTH_ACCEPTED_STREAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define STB0899_BCH_ERRFLAG (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define STB0899_OFFST_BCH_ERRFLAG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define STB0899_WIDTH_BCH_ERRFLAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define STB0899_CRCRES (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define STB0899_OFFST_CRCRES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define STB0899_WIDTH_CRCRES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define STB0899_CFGPDELSTATUS_LOCK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define STB0899_OFFST_CFGPDELSTATUS_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define STB0899_WIDTH_CFGPDELSTATUS_LOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define STB0899_1STLOCK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define STB0899_OFFST_1STLOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define STB0899_WIDTH_1STLOCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define STB0899_CFGPDELSTATUS2 0xf61a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define STB0899_BBFERRORM 0xf61b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define STB0899_BBFERRORL 0xf61c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define STB0899_UPKTERRORM 0xf61d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define STB0899_UPKTERRORL 0xf61e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define STB0899_TSTCK 0xff10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define STB0899_TSTRES 0xff11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define STB0899_FRESLDPC (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define STB0899_OFFST_FRESLDPC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define STB0899_WIDTH_FRESLDPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define STB0899_FRESRS (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define STB0899_OFFST_FRESRS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define STB0899_WIDTH_FRESRS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define STB0899_FRESVIT (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define STB0899_OFFST_FRESVIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define STB0899_WIDTH_FRESVIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define STB0899_FRESMAS1_2 (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define STB0899_OFFST_FRESMAS1_2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define STB0899_WIDTH_FRESMAS1_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define STB0899_FRESACS (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define STB0899_OFFST_FRESACS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define STB0899_WIDTH_FRESACS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define STB0899_FRESSYM (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define STB0899_OFFST_FRESSYM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define STB0899_WIDTH_FRESSYM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define STB0899_FRESMAS (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define STB0899_OFFST_FRESMAS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define STB0899_WIDTH_FRESMAS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define STB0899_FRESINT (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define STB0899_OFFST_FRESINIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define STB0899_WIDTH_FRESINIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define STB0899_TSTOUT 0xff12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define STB0899_EN_SIGNATURE (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define STB0899_OFFST_EN_SIGNATURE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define STB0899_WIDTH_EN_SIGNATURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define STB0899_BCLK_CLK (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define STB0899_OFFST_BCLK_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define STB0899_WIDTH_BCLK_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define STB0899_SGNL_OUT (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define STB0899_OFFST_SGNL_OUT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define STB0899_WIDTH_SGNL_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define STB0899_TS (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define STB0899_OFFST_TS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define STB0899_WIDTH_TS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define STB0899_CTEST (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define STB0899_OFFST_CTEST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define STB0899_WIDTH_CTEST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define STB0899_TSTIN 0xff13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define STB0899_TEST_IN (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define STB0899_OFFST_TEST_IN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define STB0899_WIDTH_TEST_IN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define STB0899_EN_ADC (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define STB0899_OFFST_EN_ADC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define STB0899_WIDTH_ENADC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define STB0899_SGN_ADC (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define STB0899_OFFST_SGN_ADC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define STB0899_WIDTH_SGN_ADC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define STB0899_BCLK_IN (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define STB0899_OFFST_BCLK_IN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define STB0899_WIDTH_BCLK_IN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define STB0899_JETONIN_MODE (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define STB0899_OFFST_JETONIN_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define STB0899_WIDTH_JETONIN_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define STB0899_BCLK_VALUE (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define STB0899_OFFST_BCLK_VALUE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define STB0899_WIDTH_BCLK_VALUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define STB0899_SGNRST_T12 (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define STB0899_OFFST_SGNRST_T12 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define STB0899_WIDTH_SGNRST_T12 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define STB0899_LOWSP_ENAX (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define STB0899_OFFST_LOWSP_ENAX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define STB0899_WIDTH_LOWSP_ENAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define STB0899_TSTSYS 0xff14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define STB0899_TSTCHIP 0xff15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define STB0899_TSTFREE 0xff16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define STB0899_TSTI2C 0xff17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define STB0899_BITSPEEDM 0xff1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define STB0899_BITSPEEDL 0xff1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define STB0899_TBUSBIT 0xff1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define STB0899_TSTDIS 0xff24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define STB0899_TSTDISRX 0xff25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define STB0899_TSTJETON 0xff28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define STB0899_TSTDCADJ 0xff40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define STB0899_TSTAGC1 0xff41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define STB0899_TSTAGC1N 0xff42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define STB0899_TSTPOLYPH 0xff48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define STB0899_TSTR 0xff49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define STB0899_TSTAGC2 0xff4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define STB0899_TSTCTL1 0xff4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define STB0899_TSTCTL2 0xff4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define STB0899_TSTCTL3 0xff4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define STB0899_TSTDEMAP 0xff50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define STB0899_TSTDEMAP2 0xff51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define STB0899_TSTDEMMON 0xff52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define STB0899_TSTRATE 0xff53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define STB0899_TSTSELOUT 0xff54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define STB0899_TSYNC 0xff55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define STB0899_TSTERR 0xff56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define STB0899_TSTRAM1 0xff58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define STB0899_TSTVSELOUT 0xff59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define STB0899_TSTFORCEIN 0xff5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define STB0899_TSTRS1 0xff5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define STB0899_TSTRS2 0xff5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define STB0899_TSTRS3 0xff53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define STB0899_INTBUFSTATUS 0xf200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define STB0899_INTBUFCTRL 0xf201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define STB0899_PCKLENUL 0xf55e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define STB0899_PCKLENLL 0xf55f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define STB0899_RSPCKLEN 0xf560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* 2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define STB0899_SYNCDCST 0xf60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* DiSEqC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define STB0899_DISCNTRL1 0xf0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define STB0899_TIMOFF (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define STB0899_OFFST_TIMOFF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define STB0899_WIDTH_TIMOFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define STB0899_DISEQCRESET (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define STB0899_OFFST_DISEQCRESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define STB0899_WIDTH_DISEQCRESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define STB0899_TIMCMD (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define STB0899_OFFST_TIMCMD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define STB0899_WIDTH_TIMCMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define STB0899_DISPRECHARGE (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define STB0899_OFFST_DISPRECHARGE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define STB0899_WIDTH_DISPRECHARGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define STB0899_DISEQCMODE (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define STB0899_OFFST_DISEQCMODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define STB0899_WIDTH_DISEQCMODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define STB0899_DISCNTRL2 0xf0a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define STB0899_RECEIVER_ON (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define STB0899_OFFST_RECEIVER_ON 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define STB0899_WIDTH_RECEIVER_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define STB0899_IGNO_SHORT_22K (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define STB0899_OFFST_IGNO_SHORT_22K 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define STB0899_WIDTH_IGNO_SHORT_22K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define STB0899_ONECHIP_TRX (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define STB0899_OFFST_ONECHIP_TRX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define STB0899_WIDTH_ONECHIP_TRX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define STB0899_EXT_ENVELOP (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define STB0899_OFFST_EXT_ENVELOP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define STB0899_WIDTH_EXT_ENVELOP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define STB0899_PIN_SELECT (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define STB0899_OFFST_PIN_SELCT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define STB0899_WIDTH_PIN_SELCT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define STB0899_IRQ_RXEND (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define STB0899_OFFST_IRQ_RXEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define STB0899_WIDTH_IRQ_RXEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define STB0899_IRQ_4NBYTES (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define STB0899_OFFST_IRQ_4NBYTES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define STB0899_WIDTH_IRQ_4NBYTES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define STB0899_DISRX_ST0 0xf0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define STB0899_RXEND (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define STB0899_OFFST_RXEND 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define STB0899_WIDTH_RXEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define STB0899_RXACTIVE (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define STB0899_OFFST_RXACTIVE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define STB0899_WIDTH_RXACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define STB0899_SHORT22K (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define STB0899_OFFST_SHORT22K 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define STB0899_WIDTH_SHORT22K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define STB0899_CONTTONE (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define STB0899_OFFST_CONTTONE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define STB0899_WIDTH_CONTONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define STB0899_4BFIFOREDY (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define STB0899_OFFST_4BFIFOREDY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define STB0899_WIDTH_4BFIFOREDY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define STB0899_FIFOEMPTY (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define STB0899_OFFST_FIFOEMPTY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define STB0899_WIDTH_FIFOEMPTY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define STB0899_ABORTTRX (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define STB0899_OFFST_ABORTTRX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define STB0899_WIDTH_ABORTTRX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define STB0899_DISRX_ST1 0xf0a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define STB0899_RXFAIL (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define STB0899_OFFST_RXFAIL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define STB0899_WIDTH_RXFAIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define STB0899_FIFOPFAIL (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define STB0899_OFFST_FIFOPFAIL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define STB0899_WIDTH_FIFOPFAIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define STB0899_RXNONBYTES (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define STB0899_OFFST_RXNONBYTES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define STB0899_WIDTH_RXNONBYTES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define STB0899_FIFOOVF (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define STB0899_OFFST_FIFOOVF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define STB0899_WIDTH_FIFOOVF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define STB0899_FIFOBYTENBR (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define STB0899_OFFST_FIFOBYTENBR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define STB0899_WIDTH_FIFOBYTENBR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define STB0899_DISPARITY 0xf0a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define STB0899_DISFIFO 0xf0a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define STB0899_DISSTATUS 0xf0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define STB0899_FIFOFULL (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define STB0899_OFFST_FIFOFULL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define STB0899_WIDTH_FIFOFULL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define STB0899_TXIDLE (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define STB0899_OFFST_TXIDLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define STB0899_WIDTH_TXIDLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define STB0899_GAPBURST (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define STB0899_OFFST_GAPBURST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define STB0899_WIDTH_GAPBURST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define STB0899_TXFIFOBYTES (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define STB0899_OFFST_TXFIFOBYTES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define STB0899_WIDTH_TXFIFOBYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define STB0899_DISF22 0xf0a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define STB0899_DISF22RX 0xf0aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* General Purpose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define STB0899_SYSREG 0xf101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define STB0899_ACRPRESC 0xf110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define STB0899_OFFST_RSVD2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define STB0899_WIDTH_RSVD2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define STB0899_OFFST_ACRPRESC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define STB0899_WIDTH_ACRPRESC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define STB0899_OFFST_RSVD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define STB0899_WIDTH_RSVD1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define STB0899_OFFST_ACRPRESC2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define STB0899_WIDTH_ACRPRESC2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define STB0899_ACRDIV1 0xf111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define STB0899_ACRDIV2 0xf112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define STB0899_DACR1 0xf113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define STB0899_DACR2 0xf114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define STB0899_OUTCFG 0xf11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define STB0899_MODECFG 0xf11d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define STB0899_NCOARSE 0xf1b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define STB0899_SYNTCTRL 0xf1b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define STB0899_STANDBY (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define STB0899_OFFST_STANDBY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define STB0899_WIDTH_STANDBY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define STB0899_BYPASSPLL (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define STB0899_OFFST_BYPASSPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define STB0899_WIDTH_BYPASSPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define STB0899_SEL1XRATIO (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define STB0899_OFFST_SEL1XRATIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define STB0899_WIDTH_SEL1XRATIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define STB0899_SELOSCI (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define STB0899_OFFST_SELOSCI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define STB0899_WIDTH_SELOSCI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define STB0899_FILTCTRL 0xf1b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define STB0899_SYSCTRL 0xf1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define STB0899_STOPCLK1 0xf1c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define STB0899_STOP_CKINTBUF108 (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define STB0899_OFFST_STOP_CKINTBUF108 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define STB0899_WIDTH_STOP_CKINTBUF108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define STB0899_STOP_CKINTBUF216 (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define STB0899_OFFST_STOP_CKINTBUF216 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define STB0899_WIDTH_STOP_CKINTBUF216 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define STB0899_STOP_CHK8PSK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define STB0899_OFFST_STOP_CHK8PSK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define STB0899_WIDTH_STOP_CHK8PSK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define STB0899_STOP_CKFEC108 (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define STB0899_OFFST_STOP_CKFEC108 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define STB0899_WIDTH_STOP_CKFEC108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define STB0899_STOP_CKFEC216 (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define STB0899_OFFST_STOP_CKFEC216 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define STB0899_WIDTH_STOP_CKFEC216 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define STB0899_STOP_CKCORE216 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define STB0899_OFFST_STOP_CKCORE216 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define STB0899_WIDTH_STOP_CKCORE216 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define STB0899_STOP_CKADCI108 (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define STB0899_OFFST_STOP_CKADCI108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define STB0899_WIDTH_STOP_CKADCI108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define STB0899_STOP_INVCKADCI108 (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define STB0899_OFFST_STOP_INVCKADCI108 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define STB0899_WIDTH_STOP_INVCKADCI108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define STB0899_STOPCLK2 0xf1c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define STB0899_STOP_CKS2DMD108 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define STB0899_OFFST_STOP_CKS2DMD108 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define STB0899_WIDTH_STOP_CKS2DMD108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define STB0899_STOP_CKPKDLIN108 (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define STB0899_OFFST_STOP_CKPKDLIN108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define STB0899_WIDTH_STOP_CKPKDLIN108 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define STB0899_STOP_CKPKDLIN216 (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define STB0899_OFFST_STOP_CKPKDLIN216 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define STB0899_WIDTH_STOP_CKPKDLIN216 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define STB0899_TSTTNR1 0xf1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define STB0899_BYPASS_ADC (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define STB0899_OFFST_BYPASS_ADC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define STB0899_WIDTH_BYPASS_ADC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define STB0899_INVADCICKOUT (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define STB0899_OFFST_INVADCICKOUT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define STB0899_WIDTH_INVADCICKOUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define STB0899_ADCTEST_VOLTAGE (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define STB0899_OFFST_ADCTEST_VOLTAGE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define STB0899_WIDTH_ADCTEST_VOLTAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define STB0899_ADC_RESET (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define STB0899_OFFST_ADC_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define STB0899_WIDTH_ADC_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define STB0899_TSTTNR1_2 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define STB0899_OFFST_TSTTNR1_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define STB0899_WIDTH_TSTTNR1_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define STB0899_ADCPON (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define STB0899_OFFST_ADCPON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define STB0899_WIDTH_ADCPON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define STB0899_ADCIN_MODE (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define STB0899_OFFST_ADCIN_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define STB0899_WIDTH_ADCIN_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define STB0899_TSTTNR2 0xf1e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define STB0899_TSTTNR2_7 (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define STB0899_OFFST_TSTTNR2_7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define STB0899_WIDTH_TSTTNR2_7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define STB0899_NOT_DISRX_WIRED (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define STB0899_OFFST_NOT_DISRX_WIRED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define STB0899_WIDTH_NOT_DISRX_WIRED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define STB0899_DISEQC_DCURRENT (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define STB0899_OFFST_DISEQC_DCURRENT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define STB0899_WIDTH_DISEQC_DCURRENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define STB0899_DISEQC_ZCURRENT (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define STB0899_OFFST_DISEQC_ZCURRENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define STB0899_WIDTH_DISEQC_ZCURRENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define STB0899_DISEQC_SINC_SOURCE (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define STB0899_OFFST_DISEQC_SINC_SOURCE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define STB0899_WIDTH_DISEQC_SINC_SOURCE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define STB0899_SELIQSRC (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define STB0899_OFFST_SELIQSRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define STB0899_WIDTH_SELIQSRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define STB0899_TSTTNR3 0xf1e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define STB0899_I2CCFG 0xf129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define STB0899_I2CCFGRSVD (0x0f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define STB0899_OFFST_I2CCFGRSVD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define STB0899_WIDTH_I2CCFGRSVD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define STB0899_I2CFASTMODE (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define STB0899_OFFST_I2CFASTMODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define STB0899_WIDTH_I2CFASTMODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define STB0899_STATUSWR (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define STB0899_OFFST_STATUSWR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define STB0899_WIDTH_STATUSWR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define STB0899_I2CADDRINC (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define STB0899_OFFST_I2CADDRINC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define STB0899_WIDTH_I2CADDRINC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define STB0899_I2CRPT 0xf12a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define STB0899_I2CTON (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define STB0899_OFFST_I2CTON 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define STB0899_WIDTH_I2CTON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define STB0899_ENARPTLEVEL (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define STB0899_OFFST_ENARPTLEVEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define STB0899_WIDTH_ENARPTLEVEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define STB0899_SCLTDELAY (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define STB0899_OFFST_SCLTDELAY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define STB0899_WIDTH_SCLTDELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define STB0899_STOPENA (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define STB0899_OFFST_STOPENA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define STB0899_WIDTH_STOPENA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define STB0899_STOPSDAT2SDA (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define STB0899_OFFST_STOPSDAT2SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define STB0899_WIDTH_STOPSDAT2SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define STB0899_IOPVALUE8 0xf136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define STB0899_IOPVALUE7 0xf137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define STB0899_IOPVALUE6 0xf138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define STB0899_IOPVALUE5 0xf139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define STB0899_IOPVALUE4 0xf13a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define STB0899_IOPVALUE3 0xf13b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define STB0899_IOPVALUE2 0xf13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define STB0899_IOPVALUE1 0xf13d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define STB0899_IOPVALUE0 0xf13e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define STB0899_GPIO00CFG 0xf140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define STB0899_GPIO01CFG 0xf141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define STB0899_GPIO02CFG 0xf142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define STB0899_GPIO03CFG 0xf143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define STB0899_GPIO04CFG 0xf144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define STB0899_GPIO05CFG 0xf145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define STB0899_GPIO06CFG 0xf146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define STB0899_GPIO07CFG 0xf147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define STB0899_GPIO08CFG 0xf148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define STB0899_GPIO09CFG 0xf149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define STB0899_GPIO10CFG 0xf14a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define STB0899_GPIO11CFG 0xf14b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define STB0899_GPIO12CFG 0xf14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define STB0899_GPIO13CFG 0xf14d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define STB0899_GPIO14CFG 0xf14e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define STB0899_GPIO15CFG 0xf14f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #define STB0899_GPIO16CFG 0xf150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define STB0899_GPIO17CFG 0xf151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define STB0899_GPIO18CFG 0xf152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define STB0899_GPIO19CFG 0xf153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define STB0899_GPIO20CFG 0xf154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define STB0899_SDATCFG 0xf155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define STB0899_SCLTCFG 0xf156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define STB0899_AGCRFCFG 0xf157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define STB0899_GPIO22 0xf158 /* AGCBB2CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define STB0899_GPIO21 0xf159 /* AGCBB1CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define STB0899_DIRCLKCFG 0xf15a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define STB0899_CLKOUT27CFG 0xf15b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define STB0899_STDBYCFG 0xf15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define STB0899_CS0CFG 0xf15d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define STB0899_CS1CFG 0xf15e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define STB0899_DISEQCOCFG 0xf15f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define STB0899_GPIO32CFG 0xf160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define STB0899_GPIO33CFG 0xf161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define STB0899_GPIO34CFG 0xf162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #define STB0899_GPIO35CFG 0xf163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define STB0899_GPIO36CFG 0xf164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #define STB0899_GPIO37CFG 0xf165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define STB0899_GPIO38CFG 0xf166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #define STB0899_GPIO39CFG 0xf167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #define STB0899_IRQSTATUS_3 0xf120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define STB0899_IRQSTATUS_2 0xf121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define STB0899_IRQSTATUS_1 0xf122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define STB0899_IRQSTATUS_0 0xf123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define STB0899_IRQMSK_3 0xf124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define STB0899_IRQMSK_2 0xf125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define STB0899_IRQMSK_1 0xf126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #define STB0899_IRQMSK_0 0xf127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #define STB0899_IRQCFG 0xf128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) #define STB0899_GHOSTREG 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define STB0899_S2DEMOD 0xf3fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define STB0899_S2FEC 0xfafc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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